SHIFT16
#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
((responseQueue & OBID_MASK) << SHIFT16) |
((responseQueue & OBID_MASK) << SHIFT16) |
ret = (saRoot->OBQnumber << SHIFT16) | saRoot->IBQnumber;
((responseQueue & OBID_MASK) << SHIFT16) |
regVal = (ossaHwRegReadExt(agRoot, PCIBAR3, HDA_RSP_OFFSET1MB+HDA_CMD_CODE_OFFSET) & HDA_SEQ_ID_BITS ) >> SHIFT16;
regVal = (HDA_C_PA << SHIFT24) | (regVal << SHIFT16) | HDAC_EXEC_CMD;
hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_DMA;
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
hdacmd.C_PA_SEQ_ID_CMD_CODE = ( SPC_V_HDAC_PA << SHIFT24 ) | ( seq_id << SHIFT16 )| SPC_V_HDAC_EXEC;
hda_command_complete = ((ossaHwRegReadExt(agRoot, PCIBAR0, SPC_V_HDA_RESPONSE_OFFSET+28) & SPC_V_HDAR_SEQID_MASK ) >> SHIFT16) == seq_id;
(enable64 << SHIFT16) |
(queueConfig->generalEventQueue << SHIFT16) |
(queueConfig->sasHwEventQueue[2] << SHIFT16) |
(queueConfig->sasHwEventQueue[6] << SHIFT16) |
(queueConfig->sataNCQErrorEventQueue[2] << SHIFT16) |
(queueConfig->sataNCQErrorEventQueue[6] << SHIFT16) |
(config->inboundQueues[qIdx].elementSize << SHIFT16) |
(config->outboundQueues[qIdx].elementSize << SHIFT16);
((config->outboundQueues[qIdx].interruptThreshold & INT_THR_BITS ) << SHIFT16) |
GSTLenMPIS = GSTLenMPIS >> SHIFT16;
ExpSignature = ('P') | ('M' << SHIFT8) | ('C' << SHIFT16) | ('S' << SHIFT24);
saRoot->ControllerInfo.maxDevices = (config->MDevMaxSGL & MAX_DEV_BITS) >> SHIFT16;
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
(( controllerStatus->fatalErrorInfo.errorInfo3 & 0x3) << SHIFT16) | /* bit 16 17 */
((( controllerStatus->fatalErrorInfo.errorInfo3 >> SHIFT16) & 0xFF) << SHIFT24) );/* bit 24 31 */
SA_DBG1(("saGetControllerStatus: bootStatus Encryption Cap %x\n", ((controllerStatus->bootStatus & 0x30000 ) >> SHIFT16) ));
IR_IP_OV_res_phyId_DPdLen_res = (pSMPFrame->outFrameLen << SHIFT16) | pSMPFrame->flag;
UDTR5_UDTR2 = (( diag->udrtArray[5] << SHIFT24) | (diag->udrtArray[4] << SHIFT16) | (diag->udrtArray[3] << SHIFT8) | diag->udrtArray[2]);
UDT5_UDT2 = (( diag->udtArray[5] << SHIFT24) | (diag->udtArray[4] << SHIFT16) | (diag->udtArray[3] << SHIFT8) | diag->udtArray[2]);
UDTR1_UDT0 = (( diag->udrtArray[1] << SHIFT24) | (diag->udrtArray[0] << SHIFT16) | (diag->udtArray[1] << SHIFT8) | diag->udtArray[0]);
controllerInfo->maxDevices = controllerInfo->maxDevices >> SHIFT16;
mcn = (flag & 0xF0000) >>SHIFT16;
ha << SHIFT16 | \
(NVMDInfo->TWIDeviceAddress << SHIFT16) | (NVMDInfo->TWIBusNumber << SHIFT12) |
(NVMDInfo->TWIDeviceAddress << SHIFT16) | (NVMDInfo->TWIBusNumber << SHIFT12) |
(NVMDInfo->TWIDeviceAddress << SHIFT16) | (NVMDInfo->TWIBusNumber << SHIFT12) |
(agSASConfig->openRejectRetriesCmd << SHIFT16) | agSASConfig->openRejectRetriesData);
agDifEncOffload->dif.udrtArray[0] << SHIFT16 |
agDifEncOffload->dif.udtArray[4] << SHIFT16 |
agDifEncOffload->dif.udrtArray[4] << SHIFT16 |
agDifEncOffload->dif.DIFPerLARegion0SecCount << SHIFT16 |
dw15 = agDifEncOffload->encrypt.EncryptionPerLRegion0SecCount << SHIFT16 |
Sscd = (agPhyConfig->phyProperties & 0xf0000) >> SHIFT16;
phyId = (npipps & PHY_ID_V_BITS) >> SHIFT16;
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16) | (linkRate << SHIFT8);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16) | (linkRate << SHIFT8);
phyId |= (npipps & PHY_IN_PORT_MASK) | ((npipps & PORT_STATE_MASK) << SHIFT16);
commonDevInfo.firstBurstSize = (bit16)((IRMcnITNexusTimeOut >> SHIFT16) & FIRST_BURST_MCN);
(bit16)((IRMcnITNexusTimeOut >> SHIFT16) & FIRST_BURST);
(bit16)((FirstBurstSizeITNexusTimeOut >> SHIFT16) & FIRST_BURST);
(bit16)((FirstBurstSizeITNexusTimeOut >> SHIFT16) & FIRST_BURST);
(bit16)((iniTagSSPIul >> SHIFT16) & INITTAG_BITS),
((TlrHdsa >> SHIFT16) & TLR_BITS),
(bit16)((iniTagSSPIul >> SHIFT16) & INITTAG_BITS),
((TlrHdsa >> SHIFT16) & TLR_BITS),
HostAssignedId = (FwdDeviceId & 0xFFFF0000) >> SHIFT16;
HostAssignedId = (FwdDeviceId & 0xFFFF0000) >> SHIFT16;
SASReconfig.openRejectRetriesCmd = (bit16)((openRejReCmdData & 0xFFFF0000) >> SHIFT16);
errorQualifier = (errorQualifierPage & 0xFFFF0000) >> SHIFT16;
encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16;
encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16;
status |= ((npipps & PORT_STATE_MASK) << SHIFT16);
status |= ((npipps & PORT_STATE_MASK) << SHIFT16);
encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16;
encryptInfo->status = (ScratchPad3 & SCRATCH_PAD3_V_ERR_CODE ) >> SHIFT16;
(newKekIndex << SHIFT24) | (wrapperKekIndex << SHIFT16) | blobFormat << SHIFT14 | (flags << SHIFT8) | KEK_MGMT_SUBOP_UPDATE);
(1 << SHIFT24) | (1 << SHIFT16) | (1 << SHIFT8) | KEK_MGMT_SUBOP_KEYCARDUPDATE);
kekIndex << SHIFT16 | KEK_MGMT_SUBOP_INVALIDATE);
(agTag << SHIFT16) |
(agTag << SHIFT16) |
encryptFlags |= (agSATAReq->encrypt.EncryptionPerLRegion0SecCount << SHIFT16);
IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16);
IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16);
IR_IP_OV_res_phyId_DPdLen_res |= (((pSMPFrame->outFrameLen) & 0xff) << SHIFT16);
pIRequest->dif.udtArray[4] << SHIFT16 |
pIRequest->dif.udrtArray[0] << SHIFT16 );
pIRequest->dif.udrtArray[4] << SHIFT16 |
((pIRequest->dif.DIFPerLARegion0SecCount << SHIFT16) |
encryptFlags |= (pIRequest->encrypt.EncryptionPerLRegion0SecCount) << SHIFT16;
pTRequest->dif.udtArray[4] << SHIFT16 |
pTRequest->dif.udrtArray[0] << SHIFT16 );
pTRequest->dif.udrtArray[4] << SHIFT16 |
((pTRequest->dif.DIFPerLARegion0SecCount << SHIFT16) |
(pTResponse->agTag << SHIFT16) | ods | (ip << SHIFT10) | (an << SHIFT2));