sys/dev/bce/if_bce.c

10124

cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);

sys/dev/bce/if_bce.c

10125

ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);

sys/dev/bce/if_bce.c

10128

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);

sys/dev/bce/if_bce.c

10137

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);

sys/dev/bce/if_bce.c

10146

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);

sys/dev/bce/if_bce.c

10151

cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);

sys/dev/bce/if_bce.c

10152

ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);

sys/dev/bce/if_bce.c

10155

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);

sys/dev/bce/if_bce.c

10160

cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);

sys/dev/bce/if_bce.c

10161

ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);

sys/dev/bce/if_bce.c

10164

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);

sys/dev/bce/if_bce.c

10169

cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);

sys/dev/bce/if_bce.c

10170

ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);

sys/dev/bce/if_bce.c

10173

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);

sys/dev/bce/if_bce.c

10178

cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);

sys/dev/bce/if_bce.c

10179

ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);

sys/dev/bce/if_bce.c

10182

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);

sys/dev/bce/if_bce.c

10187

cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);

sys/dev/bce/if_bce.c

10188

ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);

sys/dev/bce/if_bce.c

10191

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);

sys/dev/bce/if_bce.c

10196

cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);

sys/dev/bce/if_bce.c

10197

ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);

sys/dev/bce/if_bce.c

10200

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);

sys/dev/bce/if_bce.c

10209

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);

sys/dev/bce/if_bce.c

10214

cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);

sys/dev/bce/if_bce.c

10215

ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);

sys/dev/bce/if_bce.c

10218

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);

sys/dev/bce/if_bce.c

10227

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);

sys/dev/bce/if_bce.c

10236

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);

sys/dev/bce/if_bce.c

10245

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);

sys/dev/bce/if_bce.c

10254

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);

sys/dev/bce/if_bce.c

10263

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);

sys/dev/bce/if_bce.c

10283

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);

sys/dev/bce/if_bce.c

10292

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);

sys/dev/bce/if_bce.c

10297

cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);

sys/dev/bce/if_bce.c

10298

ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);

sys/dev/bce/if_bce.c

10301

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);

sys/dev/bce/if_bce.c

10307

cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);

sys/dev/bce/if_bce.c

10308

ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);

sys/dev/bce/if_bce.c

10311

valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);

sys/dev/bce/if_bce.c

10784

val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);

sys/dev/bce/if_bce.c

10788

val = REG_RD(sc, BCE_DMA_STATUS);

sys/dev/bce/if_bce.c

10792

val = REG_RD(sc, BCE_CTX_STATUS);

sys/dev/bce/if_bce.c

10796

val = REG_RD(sc, BCE_EMAC_STATUS);

sys/dev/bce/if_bce.c

10800

val = REG_RD(sc, BCE_RPM_STATUS);

sys/dev/bce/if_bce.c

10805

val = REG_RD(sc, 0x2004);

sys/dev/bce/if_bce.c

10809

val = REG_RD(sc, BCE_RV2P_STATUS);

sys/dev/bce/if_bce.c

10814

val = REG_RD(sc, 0x2c04);

sys/dev/bce/if_bce.c

10818

val = REG_RD(sc, BCE_TBDR_STATUS);

sys/dev/bce/if_bce.c

10822

val = REG_RD(sc, BCE_TDMA_STATUS);

sys/dev/bce/if_bce.c

10826

val = REG_RD(sc, BCE_HC_STATUS);

sys/dev/bce/if_bce.c

10866

i, REG_RD(sc, i), REG_RD(sc, i + 0x4),

sys/dev/bce/if_bce.c

10867

REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));

sys/dev/bce/if_bce.c

10934

i, REG_RD(sc, i), REG_RD(sc, i + 0x4),

sys/dev/bce/if_bce.c

10935

REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));

sys/dev/bce/if_bce.c

1160

sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);

sys/dev/bce/if_bce.c

1263

val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);

sys/dev/bce/if_bce.c

1269

clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);

sys/dev/bce/if_bce.c

1746

val = REG_RD(sc, BCE_CTX_CTX_CTRL);

sys/dev/bce/if_bce.c

1757

val = REG_RD(sc, BCE_CTX_CTX_DATA);

sys/dev/bce/if_bce.c

1760

val = REG_RD(sc, BCE_CTX_DATA);

sys/dev/bce/if_bce.c

1797

val = REG_RD(sc, BCE_CTX_CTX_CTRL);

sys/dev/bce/if_bce.c

1842

val = REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1846

REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1859

val = REG_RD(sc, BCE_EMAC_MDIO_COMM);

sys/dev/bce/if_bce.c

1863

val = REG_RD(sc, BCE_EMAC_MDIO_COMM);

sys/dev/bce/if_bce.c

1875

val = REG_RD(sc, BCE_EMAC_MDIO_COMM);

sys/dev/bce/if_bce.c

1879

val = REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1883

REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1922

val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1926

REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1939

val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);

sys/dev/bce/if_bce.c

1951

val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

1955

REG_RD(sc, BCE_EMAC_MDIO_MODE);

sys/dev/bce/if_bce.c

2000

val = REG_RD(sc, BCE_EMAC_MODE);

sys/dev/bce/if_bce.c

2096

val = REG_RD(sc, BCE_NVM_SW_ARB);

sys/dev/bce/if_bce.c

2136

val = REG_RD(sc, BCE_NVM_SW_ARB);

sys/dev/bce/if_bce.c

2169

val = REG_RD(sc, BCE_MISC_CFG);

sys/dev/bce/if_bce.c

2181

val = REG_RD(sc, BCE_NVM_COMMAND);

sys/dev/bce/if_bce.c

2212

val = REG_RD(sc, BCE_MISC_CFG);

sys/dev/bce/if_bce.c

2236

val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);

sys/dev/bce/if_bce.c

2259

val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);

sys/dev/bce/if_bce.c

2308

val = REG_RD(sc, BCE_NVM_COMMAND);

sys/dev/bce/if_bce.c

2366

val = REG_RD(sc, BCE_NVM_COMMAND);

sys/dev/bce/if_bce.c

2368

val = REG_RD(sc, BCE_NVM_READ);

sys/dev/bce/if_bce.c

2432

if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)

sys/dev/bce/if_bce.c

2470

val = REG_RD(sc, BCE_NVM_CFG1);

sys/dev/bce/if_bce.c

3022

u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);

sys/dev/bce/if_bce.c

4671

val = REG_RD(sc, BCE_CTX_COMMAND);

sys/dev/bce/if_bce.c

4695

val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);

sys/dev/bce/if_bce.c

4830

REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);

sys/dev/bce/if_bce.c

4873

emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;

sys/dev/bce/if_bce.c

4881

val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);

sys/dev/bce/if_bce.c

4886

val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);

sys/dev/bce/if_bce.c

4904

val = REG_RD(sc, BCE_MISC_ID);

sys/dev/bce/if_bce.c

4909

REG_RD(sc, BCE_MISC_COMMAND);

sys/dev/bce/if_bce.c

4924

val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);

sys/dev/bce/if_bce.c

4943

val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);

sys/dev/bce/if_bce.c

4966

val = REG_RD(sc, BCE_EMAC_MODE);

sys/dev/bce/if_bce.c

5030

val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;

sys/dev/bce/if_bce.c

5039

val = REG_RD(sc, BCE_MQ_CONFIG);

sys/dev/bce/if_bce.c

5061

val = REG_RD(sc, BCE_TBDR_CONFIG);

sys/dev/bce/if_bce.c

5202

val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);

sys/dev/bce/if_bce.c

5219

val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &

sys/dev/bce/if_bce.c

5232

REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);

sys/dev/bce/if_bce.c

5236

sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);

sys/dev/bce/if_bce.c

5670

val = REG_RD(sc, BCE_MQ_MAP_L2_5);

sys/dev/bce/if_bce.c

6888

REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);

sys/dev/bce/if_bce.c

7057

REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);

sys/dev/bce/if_bce.c

7697

status = REG_RD(sc, BCE_EMAC_RX_STATUS);

sys/dev/bce/if_bce.c

7790

(REG_RD(sc, BCE_PCICFG_MISC_STATUS) &

sys/dev/bce/if_bce.c

7826

REG_RD(sc, BCE_HC_COMMAND);

sys/dev/bce/if_bce.c

8774

val = REG_RD(sc, result);

sys/dev/bce/if_bce.c

9504

val = REG_RD(sc, BCE_MISC_COMMAND);

sys/dev/bce/if_bce.c

9520

val = REG_RD(sc, BCE_MISC_COMMAND);

sys/dev/bce/if_bcereg.h

1071

REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))

sys/dev/bce/if_bcereg.h

1073

REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))

sys/dev/bxe/bxe.c

10226

uint32_t val = REG_RD(sc, addr);

sys/dev/bxe/bxe.c

1027

lock_status = REG_RD(sc, hw_lock_control_reg);

sys/dev/bxe/bxe.c

10302

val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);

sys/dev/bxe/bxe.c

1037

lock_status = REG_RD(sc, hw_lock_control_reg);

sys/dev/bxe/bxe.c

10372

uint32_t val = REG_RD(sc, addr);

sys/dev/bxe/bxe.c

10402

if (REG_RD(sc, addr) != val) {

sys/dev/bxe/bxe.c

10410

uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);

sys/dev/bxe/bxe.c

10422

if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) {

sys/dev/bxe/bxe.c

10478

REG_RD(sc,

sys/dev/bxe/bxe.c

10658

lock_status = REG_RD(sc, hw_lock_control_reg);

sys/dev/bxe/bxe.c

10715

val = REG_RD(sc, HC_REG_CONFIG_1);

sys/dev/bxe/bxe.c

10720

val = REG_RD(sc, HC_REG_CONFIG_0);

sys/dev/bxe/bxe.c

10726

val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);

sys/dev/bxe/bxe.c

1073

lock_status = REG_RD(sc, hw_lock_control_reg);

sys/dev/bxe/bxe.c

10748

pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS);

sys/dev/bxe/bxe.c

10802

shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);

sys/dev/bxe/bxe.c

10836

REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);

sys/dev/bxe/bxe.c

10998

sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT);

sys/dev/bxe/bxe.c

10999

blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT);

sys/dev/bxe/bxe.c

11000

port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0);

sys/dev/bxe/bxe.c

11001

port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1);

sys/dev/bxe/bxe.c

11002

pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2);

sys/dev/bxe/bxe.c

11004

tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32);

sys/dev/bxe/bxe.c

1129

val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);

sys/dev/bxe/bxe.c

1165

val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);

sys/dev/bxe/bxe.c

1191

val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);

sys/dev/bxe/bxe.c

1203

val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);

sys/dev/bxe/bxe.c

1244

val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);

sys/dev/bxe/bxe.c

1247

val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);

sys/dev/bxe/bxe.c

13111

val = REG_RD(sc, BAR_ME_REGISTER);

sys/dev/bxe/bxe.c

13208

(REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;

sys/dev/bxe/bxe.c

1359

val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);

sys/dev/bxe/bxe.c

13923

val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);

sys/dev/bxe/bxe.c

13979

(((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |

sys/dev/bxe/bxe.c

13980

((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) |

sys/dev/bxe/bxe.c

13981

(((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) |

sys/dev/bxe/bxe.c

13982

((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0));

sys/dev/bxe/bxe.c

13985

if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {

sys/dev/bxe/bxe.c

14004

val = (REG_RD(sc, 0x2874) & 0x55);

sys/dev/bxe/bxe.c

14023

val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);

sys/dev/bxe/bxe.c

14027

val = REG_RD(sc, MISC_REG_PORT4MODE_EN);

sys/dev/bxe/bxe.c

14042

REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);

sys/dev/bxe/bxe.c

14044

REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 :

sys/dev/bxe/bxe.c

14105

val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);

sys/dev/bxe/bxe.c

14141

val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION);

sys/dev/bxe/bxe.c

14152

while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) {

sys/dev/bxe/bxe.c

14157

if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) {

sys/dev/bxe/bxe.c

14254

sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR);

sys/dev/bxe/bxe.c

14259

REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);

sys/dev/bxe/bxe.c

14263

REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);

sys/dev/bxe/bxe.c

15260

val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS);

sys/dev/bxe/bxe.c

15445

reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2);

sys/dev/bxe/bxe.c

15448

val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);

sys/dev/bxe/bxe.c

15463

wb_data[0] = REG_RD(sc, base_addr + offset);

sys/dev/bxe/bxe.c

15464

wb_data[1] = REG_RD(sc, base_addr + offset + 0x4);

sys/dev/bxe/bxe.c

15475

vals->emac_val = REG_RD(sc, vals->emac_addr);

sys/dev/bxe/bxe.c

15482

val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI);

sys/dev/bxe/bxe.c

15486

vals->xmac_val = REG_RD(sc, vals->xmac_addr);

sys/dev/bxe/bxe.c

15496

vals->umac_val = REG_RD(sc, vals->umac_addr);

sys/dev/bxe/bxe.c

15518

uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port));

sys/dev/bxe/bxe.c

15553

reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1);

sys/dev/bxe/bxe.c

15568

tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST);

sys/dev/bxe/bxe.c

15575

REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0);

sys/dev/bxe/bxe.c

15580

tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);

sys/dev/bxe/bxe.c

15584

tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS);

sys/dev/bxe/bxe.c

15699

hw_lock_val = (REG_RD(sc, hw_lock_reg));

sys/dev/bxe/bxe.c

15712

if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) {

sys/dev/bxe/bxe.c

1641

REG_RD(sc, (src_addr + (i * 4)));

sys/dev/bxe/bxe.c

16540

while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) {

sys/dev/bxe/bxe.c

16544

if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) {

sys/dev/bxe/bxe.c

16615

uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION);

sys/dev/bxe/bxe.c

16673

REG_RD(sc, pretend_reg);

sys/dev/bxe/bxe.c

16761

val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);

sys/dev/bxe/bxe.c

16816

val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);

sys/dev/bxe/bxe.c

16828

val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);

sys/dev/bxe/bxe.c

16835

REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);

sys/dev/bxe/bxe.c

16838

val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);

sys/dev/bxe/bxe.c

16903

val = REG_RD(sc, MISC_REG_SPIO_INT);

sys/dev/bxe/bxe.c

16908

val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);

sys/dev/bxe/bxe.c

17079

val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);

sys/dev/bxe/bxe.c

17085

val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);

sys/dev/bxe/bxe.c

17208

val = REG_RD(sc, ATC_REG_ATC_INIT_DONE);

sys/dev/bxe/bxe.c

17451

REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);

sys/dev/bxe/bxe.c

17698

val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);

sys/dev/bxe/bxe.c

17702

val = REG_RD(sc, reg_addr);

sys/dev/bxe/bxe.c

17719

while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) {

sys/dev/bxe/bxe.c

17829

if (REG_RD(sc, comp_addr)) {

sys/dev/bxe/bxe.c

17845

(REG_RD(sc, comp_addr)));

sys/dev/bxe/bxe.c

17864

crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed);

sys/dev/bxe/bxe.c

17865

crd = crd_start = REG_RD(sc, regs->crd);

sys/dev/bxe/bxe.c

17866

init_crd = REG_RD(sc, regs->init_crd);

sys/dev/bxe/bxe.c

17877

crd = REG_RD(sc, regs->crd);

sys/dev/bxe/bxe.c

17878

crd_freed = REG_RD(sc, regs->crd_freed);

sys/dev/bxe/bxe.c

17899

occup = to_free = REG_RD(sc, regs->lines_occup);

sys/dev/bxe/bxe.c

17900

freed = freed_start = REG_RD(sc, regs->lines_freed);

sys/dev/bxe/bxe.c

17909

occup = REG_RD(sc, regs->lines_occup);

sys/dev/bxe/bxe.c

17910

freed = REG_RD(sc, regs->lines_freed);

sys/dev/bxe/bxe.c

17995

val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF);

sys/dev/bxe/bxe.c

17998

val = REG_RD(sc, PBF_REG_DISABLE_PF);

sys/dev/bxe/bxe.c

18001

val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN);

sys/dev/bxe/bxe.c

18004

val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN);

sys/dev/bxe/bxe.c

18007

val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK);

sys/dev/bxe/bxe.c

18010

val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);

sys/dev/bxe/bxe.c

18013

val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);

sys/dev/bxe/bxe.c

18016

val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);

sys/dev/bxe/bxe.c

1809

return (REG_RD(sc, reg_addr));

sys/dev/bxe/bxe.c

18096

val = REG_RD(sc, addr);

sys/dev/bxe/bxe.c

18337

val = REG_RD(sc, main_mem_prty_clr);

sys/dev/bxe/bxe.c

18353

REG_RD(sc, main_mem_prty_clr);

sys/dev/bxe/bxe.c

18411

val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);

sys/dev/bxe/bxe.c

18498

if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4))

sys/dev/bxe/bxe.c

1869

spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT);

sys/dev/bxe/bxe.c

18812

*p++ = REG_RD(sc, addr);

sys/dev/bxe/bxe.c

18846

*p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4);

sys/dev/bxe/bxe.c

18855

*p++ = REG_RD(sc, reg_addrs[i].addr + j*4);

sys/dev/bxe/bxe.c

18863

*p++ = REG_RD(sc, wreg_addr_p->addr + i*4);

sys/dev/bxe/bxe.c

18870

*p++ = REG_RD(sc, addr + j*4);

sys/dev/bxe/bxe.c

19059

reg_val = REG_RD(sc, reg_addr);

sys/dev/bxe/bxe.c

1908

int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&

sys/dev/bxe/bxe.c

1909

REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);

sys/dev/bxe/bxe.c

1923

gpio_reg = REG_RD(sc, MISC_REG_GPIO);

sys/dev/bxe/bxe.c

1936

int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&

sys/dev/bxe/bxe.c

19360

reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id);

sys/dev/bxe/bxe.c

1937

REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);

sys/dev/bxe/bxe.c

1953

gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);

sys/dev/bxe/bxe.c

2004

gpio_reg = REG_RD(sc, MISC_REG_GPIO);

sys/dev/bxe/bxe.c

2048

int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) &&

sys/dev/bxe/bxe.c

2049

REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port);

sys/dev/bxe/bxe.c

2065

gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);

sys/dev/bxe/bxe.c

4136

val = REG_RD(sc, addr);

sys/dev/bxe/bxe.c

4140

val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK);

sys/dev/bxe/bxe.c

6607

val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6618

val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6627

uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6642

val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6660

val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6673

uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6690

uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6715

val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6747

val = REG_RD(sc, BXE_RECOVERY_GLOB_REG);

sys/dev/bxe/bxe.c

6827

loaded_fw = REG_RD(sc, XSEM_REG_PRAM);

sys/dev/bxe/bxe.c

6923

val = REG_RD(sc, GRCBASE_MCP + 0x9c);

sys/dev/bxe/bxe.c

7066

aeu_mask = REG_RD(sc, aeu_addr);

sys/dev/bxe/bxe.c

7088

nig_mask = REG_RD(sc, nig_int_mask_addr);

sys/dev/bxe/bxe.c

7166

igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS);

sys/dev/bxe/bxe.c

7532

attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

7533

attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

7534

attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

7535

attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

7541

attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0

sys/dev/bxe/bxe.c

7548

attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

7561

val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);

sys/dev/bxe/bxe.c

7585

val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR);

sys/dev/bxe/bxe.c

7825

row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i));

sys/dev/bxe/bxe.c

7826

row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4);

sys/dev/bxe/bxe.c

7827

row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8);

sys/dev/bxe/bxe.c

7828

row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12);

sys/dev/bxe/bxe.c

7848

row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i));

sys/dev/bxe/bxe.c

7849

row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4);

sys/dev/bxe/bxe.c

7850

row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8);

sys/dev/bxe/bxe.c

7851

row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12);

sys/dev/bxe/bxe.c

7871

row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i));

sys/dev/bxe/bxe.c

7872

row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4);

sys/dev/bxe/bxe.c

7873

row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8);

sys/dev/bxe/bxe.c

7874

row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12);

sys/dev/bxe/bxe.c

7894

row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i));

sys/dev/bxe/bxe.c

7895

row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4);

sys/dev/bxe/bxe.c

7896

row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8);

sys/dev/bxe/bxe.c

7897

row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12);

sys/dev/bxe/bxe.c

7992

val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN);

sys/dev/bxe/bxe.c

7996

val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN);

sys/dev/bxe/bxe.c

8014

val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);

sys/dev/bxe/bxe.c

8024

val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);

sys/dev/bxe/bxe.c

8033

val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1);

sys/dev/bxe/bxe.c

8047

mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0);

sys/dev/bxe/bxe.c

8048

val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1);

sys/dev/bxe/bxe.c

8049

mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1);

sys/dev/bxe/bxe.c

8050

val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0);

sys/dev/bxe/bxe.c

8061

val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);

sys/dev/bxe/bxe.c

8089

val = REG_RD(sc, reg_offset);

sys/dev/bxe/bxe.c

8116

val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);

sys/dev/bxe/bxe.c

8129

val = REG_RD(sc, reg_offset);

sys/dev/bxe/bxe.c

8158

val = REG_RD(sc, reg_offset);

sys/dev/bxe/bxe.c

8176

val = REG_RD(sc, reg_offset);

sys/dev/bxe/bxe.c

8224

attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

8225

attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

8226

attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

8227

attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

8229

attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);

sys/dev/bxe/bxe.c

8279

aeu_mask = REG_RD(sc, reg_addr);

sys/dev/bxe/bxe.c

9812

REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index)));

sys/dev/bxe/bxe.c

9822

REG_RD(sc, (reg_offset_en5 + (0x4 * index)));

sys/dev/bxe/bxe.h

1916

#define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))

sys/dev/bxe/bxe.h

1923

(sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \

sys/dev/bxe/bxe.h

1925

#define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))

sys/dev/bxe/bxe.h

1930

#define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))

sys/dev/bxe/bxe.h

2277

val = REG_RD(sc, reg);

sys/dev/bxe/bxe.h

2379

uint32_t result = REG_RD(sc, hc_addr);

sys/dev/bxe/bxe.h

2389

uint32_t result = REG_RD(sc, igu_addr);

sys/dev/bxe/bxe_elink.c

1000

link_status = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

10135

swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);

sys/dev/bxe/bxe_elink.c

10136

swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);

sys/dev/bxe/bxe_elink.c

10260

tx_en_mode = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

1029

saved_val = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

10290

uint32_t val = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

1038

saved_val = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

1047

saved_val = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

1057

cur_speed_cap_mask = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

1070

REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

1080

eee_status = REG_RD(sc, params->shmem2_base +

sys/dev/bxe/bxe_elink.c

11015

(REG_RD(sc, params->shmem2_base +

sys/dev/bxe/bxe_elink.c

11036

pair_swap = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

11067

reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +

sys/dev/bxe/bxe_elink.c

11080

reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +

sys/dev/bxe/bxe_elink.c

11099

uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +

sys/dev/bxe/bxe_elink.c

1111

gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);

sys/dev/bxe/bxe_elink.c

1114

*en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;

sys/dev/bxe/bxe_elink.c

1128

gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);

sys/dev/bxe/bxe_elink.c

11288

uint32_t cms_enable = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

1137

gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);

sys/dev/bxe/bxe_elink.c

11623

if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +

sys/dev/bxe/bxe_elink.c

11691

if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +

sys/dev/bxe/bxe_elink.c

11858

cfg_pin = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

12099

cfg_pin = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

12968

rx = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

12972

tx = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

12976

rx = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

12980

tx = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

13001

ext_phy_config = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

13006

ext_phy_config = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

13022

uint32_t switch_cfg = (REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

13026

chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |

sys/dev/bxe/bxe_elink.c

13027

((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);

sys/dev/bxe/bxe_elink.c

13032

phy_addr = REG_RD(sc,

sys/dev/bxe/bxe_elink.c

13035

if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)

sys/dev/bxe/bxe_elink.c

13040

serdes_net_if = (REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

13125

phy_addr = REG_RD(sc,

sys/dev/bxe/bxe_elink.c

13131

phy_addr = REG_RD(sc,

sys/dev/bxe/bxe_elink.c

13239

config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,

sys/dev/bxe/bxe_elink.c

13250

uint32_t size = REG_RD(sc, shmem2_base);

sys/dev/bxe/bxe_elink.c

13271

uint32_t raw_ver = REG_RD(sc, phy->ver_addr);

sys/dev/bxe/bxe_elink.c

13305

link_config = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

13308

phy->speed_cap_mask = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

13313

link_config = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

13316

phy->speed_cap_mask = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

13461

media_types = REG_RD(sc, sync_offset);

sys/dev/bxe/bxe_elink.c

13846

lfa_sts = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

13925

tmp_val = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

13933

lfa_sts = REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

14166

if (REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

14241

swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);

sys/dev/bxe/bxe_elink.c

14242

swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);

sys/dev/bxe/bxe_elink.c

14366

val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);

sys/dev/bxe/bxe_elink.c

14409

uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

14461

swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);

sys/dev/bxe/bxe_elink.c

14462

swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);

sys/dev/bxe/bxe_elink.c

14638

val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);

sys/dev/bxe/bxe_elink.c

14642

phy_ver = REG_RD(sc, shmem_base_path[0] +

sys/dev/bxe/bxe_elink.c

14674

cfg_pin = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

14790

(REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))

sys/dev/bxe/bxe_elink.c

14794

(REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

14808

if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))

sys/dev/bxe/bxe_elink.c

14814

} else if (REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

14845

cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,

sys/dev/bxe/bxe_elink.c

14988

if ((REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

15088

swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);

sys/dev/bxe/bxe_elink.c

15089

swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);

sys/dev/bxe/bxe_elink.c

15109

aeu_mask = REG_RD(sc, offset);

sys/dev/bxe/bxe_elink.c

15114

val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);

sys/dev/bxe/bxe_elink.c

2158

val_xoff = REG_RD(sc, emac_base +

sys/dev/bxe/bxe_elink.c

2161

val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);

sys/dev/bxe/bxe_elink.c

2167

val_xoff = REG_RD(sc, emac_base +

sys/dev/bxe/bxe_elink.c

2170

val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);

sys/dev/bxe/bxe_elink.c

2206

cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);

sys/dev/bxe/bxe_elink.c

2232

port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);

sys/dev/bxe/bxe_elink.c

2238

return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);

sys/dev/bxe/bxe_elink.c

2271

val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);

sys/dev/bxe/bxe_elink.c

2276

val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);

sys/dev/bxe/bxe_elink.c

2317

if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

2320

val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);

sys/dev/bxe/bxe_elink.c

2445

(REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

2499

if (REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

2505

pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);

sys/dev/bxe/bxe_elink.c

2511

val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);

sys/dev/bxe/bxe_elink.c

2652

val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);

sys/dev/bxe/bxe_elink.c

2683

val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);

sys/dev/bxe/bxe_elink.c

2712

val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);

sys/dev/bxe/bxe_elink.c

2951

xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :

sys/dev/bxe/bxe_elink.c

3060

val = REG_RD(sc, MISC_REG_RESET_REG_2);

sys/dev/bxe/bxe_elink.c

3271

uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);

sys/dev/bxe/bxe_elink.c

3278

if (REG_RD(sc, MISC_REG_RESET_REG_2) &

sys/dev/bxe/bxe_elink.c

3304

init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);

sys/dev/bxe/bxe_elink.c

3305

crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);

sys/dev/bxe/bxe_elink.c

3310

crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);

sys/dev/bxe/bxe_elink.c

3313

crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);

sys/dev/bxe/bxe_elink.c

3385

if (REG_RD(sc, NIG_REG_PORT_SWAP))

sys/dev/bxe/bxe_elink.c

3391

if (REG_RD(sc, NIG_REG_PORT_SWAP))

sys/dev/bxe/bxe_elink.c

3420

mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);

sys/dev/bxe/bxe_elink.c

3433

tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3456

mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);

sys/dev/bxe/bxe_elink.c

3469

val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3497

chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |

sys/dev/bxe/bxe_elink.c

3498

((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);

sys/dev/bxe/bxe_elink.c

3514

val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3536

val = REG_RD(sc, phy->mdio_ctrl +

sys/dev/bxe/bxe_elink.c

3574

chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |

sys/dev/bxe/bxe_elink.c

3575

((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);

sys/dev/bxe/bxe_elink.c

3592

tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);

sys/dev/bxe/bxe_elink.c

3613

tmp = REG_RD(sc, phy->mdio_ctrl +

sys/dev/bxe/bxe_elink.c

3648

if (REG_RD(sc, params->shmem2_base) <=

sys/dev/bxe/bxe_elink.c

3713

eee_mode = ((REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

3889

board_cfg = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

3897

sfp_ctrl = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

3926

val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);

sys/dev/bxe/bxe_elink.c

3943

val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);

sys/dev/bxe/bxe_elink.c

3946

val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);

sys/dev/bxe/bxe_elink.c

3967

val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);

sys/dev/bxe/bxe_elink.c

3970

val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);

sys/dev/bxe/bxe_elink.c

3981

data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));

sys/dev/bxe/bxe_elink.c

4058

path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);

sys/dev/bxe/bxe_elink.c

4062

path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);

sys/dev/bxe/bxe_elink.c

4068

port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);

sys/dev/bxe/bxe_elink.c

4072

port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);

sys/dev/bxe/bxe_elink.c

4082

REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);

sys/dev/bxe/bxe_elink.c

4087

REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);

sys/dev/bxe/bxe_elink.c

4645

if (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

4685

wc_lane_config = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

4836

cfg_tap_val = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

5171

cfg_pin = (REG_RD(sc, shmem_base +

sys/dev/bxe/bxe_elink.c

5248

serdes_net_if = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

5311

cfg_pin = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

5332

serdes_net_if = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

5648

vars->link_status = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

5658

vars->eee_status = REG_RD(sc, params->shmem2_base +

sys/dev/bxe/bxe_elink.c

5668

media_types = REG_RD(sc, sync_offset);

sys/dev/bxe/bxe_elink.c

5686

vars->aeu_int_mask = REG_RD(sc, sync_offset);

sys/dev/bxe/bxe_elink.c

6938

REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));

sys/dev/bxe/bxe_elink.c

6940

REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),

sys/dev/bxe/bxe_elink.c

6941

REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),

sys/dev/bxe/bxe_elink.c

6942

REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));

sys/dev/bxe/bxe_elink.c

6944

REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),

sys/dev/bxe/bxe_elink.c

6945

REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));

sys/dev/bxe/bxe_elink.c

6958

latch_status = REG_RD(sc,

sys/dev/bxe/bxe_elink.c

7082

spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);

sys/dev/bxe/bxe_elink.c

7092

spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);

sys/dev/bxe/bxe_elink.c

7121

md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +

sys/dev/bxe/bxe_elink.c

7662

val = REG_RD(sc, addr) + 1;

sys/dev/bxe/bxe_elink.c

7709

REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));

sys/dev/bxe/bxe_elink.c

7712

REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),

sys/dev/bxe/bxe_elink.c

7713

REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,

sys/dev/bxe/bxe_elink.c

7714

REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));

sys/dev/bxe/bxe_elink.c

7717

REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),

sys/dev/bxe/bxe_elink.c

7718

REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));

sys/dev/bxe/bxe_elink.c

8314

if (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

8674

swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);

sys/dev/bxe/bxe_elink.c

8675

swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);

sys/dev/bxe/bxe_elink.c

8689

tx_en_mode = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

8821

pin_cfg = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

9128

media_types = REG_RD(sc, sync_offset);

sys/dev/bxe/bxe_elink.c

9173

val = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

9438

uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

9471

pin_cfg = (REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

953

uint32_t val = REG_RD(sc, reg);

sys/dev/bxe/bxe_elink.c

9593

uint32_t val = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_elink.c

962

uint32_t val = REG_RD(sc, reg);

sys/dev/bxe/bxe_elink.c

985

REG_RD(sc, params->lfa_base +

sys/dev/bxe/bxe_elink.c

9887

tx_en_mode = REG_RD(sc, params->shmem_base +

sys/dev/bxe/bxe_stats.c

1625

REG_RD(sc, NIG_REG_STAT0_BRB_DISCARD + port*0x38);

sys/dev/bxe/bxe_stats.c

1627

REG_RD(sc, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);

sys/dev/bxe/bxe_stats.c

918

estats->eee_tx_lpi += REG_RD(sc, lpi_reg);

sys/dev/bxe/ecore_init.h

251

uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4);

sys/dev/bxe/ecore_init.h

278

reg_bit_map = REG_RD(sc, reg_addr);

sys/dev/bxe/ecore_init.h

283

reg_bit_map = REG_RD(sc, reg_addr);

sys/dev/bxe/ecore_init.h

290

reg_bit_map = REG_RD(sc, reg_addr);

sys/dev/bxe/ecore_init.h

750

reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr);

sys/dev/bxe/ecore_init.h

815

reg_val = REG_RD(sc, ecore_blocks_parity_data[i].

sys/dev/bxe/ecore_init.h

826

reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP);

sys/dev/bxe/ecore_init_ops.h

281

REG_RD(sc, addr);

sys/dev/bxe/ecore_init_ops.h

547

val = REG_RD(sc, write_arb_addr[i].l);

sys/dev/bxe/ecore_init_ops.h

551

val = REG_RD(sc, write_arb_addr[i].add);

sys/dev/bxe/ecore_init_ops.h

555

val = REG_RD(sc, write_arb_addr[i].ubound);

sys/dev/bxe/ecore_init_ops.h

616

val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);

sys/dev/qlnx/qlnxe/ecore_dev.c

2721

if (REG_RD(p_hwfn, addr)) {

sys/dev/qlnx/qlnxe/ecore_dev.c

2734

while (!REG_RD(p_hwfn, addr) && count--)

sys/dev/qlnx/qlnxe/ecore_dev.c

2737

if (REG_RD(p_hwfn, addr))

sys/dev/qlnx/qlnxe/ecore_dev.c

4524

p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_dev.c

4527

p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR);

sys/dev/qlnx/qlnxe/ecore_dev.c

5862

if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {

sys/dev/qlnx/qlnxe/ecore_hw.c

264

is_empty = REG_RD(p_hwfn, bar_addr) == 0;

sys/dev/qlnx/qlnxe/ecore_hw.c

307

val = REG_RD(p_hwfn, bar_addr);

sys/dev/qlnx/qlnxe/ecore_int.c

2533

intr_status_lo = REG_RD(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_int.c

2536

intr_status_hi = REG_RD(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_vf.c

532

p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, reg);

sys/dev/qlnx/qlnxe/ecore_vf.c

535

p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, reg);