sys/dev/hwpmc/hwpmc_mod.c

1934

PMCDBG2(LOG,REG,1,"%s %p", (char *)km->pm_file,

sys/dev/hwpmc/hwpmc_mod.c

2879

PMCDBG2(PMC,REG,1, "register-owner pmc-owner=%p pmc=%p",

sys/dev/hwpmc/hwpmc_mod.c

546

DBG_SET_FLAG_MIN("register", REG);

sys/dev/pccbb/pccbb.c

112

#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \

sys/dev/pccbb/pccbb.c

113

pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)

sys/dev/pccbb/pccbb.c

114

#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \

sys/dev/pccbb/pccbb.c

115

pci_write_config(DEV, REG, ( \

sys/dev/pccbb/pccbb.c

116

pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)

sys/dev/pccbb/pccbb_pci.c

112

#define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \

sys/dev/pccbb/pccbb_pci.c

113

pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)

sys/dev/pccbb/pccbb_pci.c

114

#define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \

sys/dev/pccbb/pccbb_pci.c

115

pci_write_config(DEV, REG, ( \

sys/dev/pccbb/pccbb_pci.c

116

pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)

sys/dev/pci/pci.c

1010

val = REG(ptr + PCIER_FLAGS, 2);

sys/dev/pci/pci.c

1056

while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {

sys/dev/pci/pci.c

1061

*data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));

sys/dev/pci/pci.c

1076

while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {

sys/dev/pci/pci.c

4274

if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)

sys/dev/pci/pci.c

4276

hdrtype = REG(PCIR_HDRTYPE, 1);

sys/dev/pci/pci.c

4317

if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)

sys/dev/pci/pci.c

4320

hdrtype = REG(PCIR_HDRTYPE, 1);

sys/dev/pci/pci.c

4326

if (REG(PCIR_VENDOR, 2) == PCIV_INVALID)

sys/dev/pci/pci.c

690

cfg->subvendor = REG(PCIR_SUBVEND_0, 2);

sys/dev/pci/pci.c

691

cfg->subdevice = REG(PCIR_SUBDEV_0, 2);

sys/dev/pci/pci.c

692

cfg->mingnt = REG(PCIR_MINGNT, 1);

sys/dev/pci/pci.c

693

cfg->maxlat = REG(PCIR_MAXLAT, 1);

sys/dev/pci/pci.c

697

cfg->bridge.br_seclat = REG(PCIR_SECLAT_1, 1);

sys/dev/pci/pci.c

698

cfg->bridge.br_subbus = REG(PCIR_SUBBUS_1, 1);

sys/dev/pci/pci.c

699

cfg->bridge.br_secbus = REG(PCIR_SECBUS_1, 1);

sys/dev/pci/pci.c

700

cfg->bridge.br_pribus = REG(PCIR_PRIBUS_1, 1);

sys/dev/pci/pci.c

701

cfg->bridge.br_control = REG(PCIR_BRIDGECTL_1, 2);

sys/dev/pci/pci.c

705

cfg->bridge.br_seclat = REG(PCIR_SECLAT_2, 1);

sys/dev/pci/pci.c

706

cfg->bridge.br_subbus = REG(PCIR_SUBBUS_2, 1);

sys/dev/pci/pci.c

707

cfg->bridge.br_secbus = REG(PCIR_SECBUS_2, 1);

sys/dev/pci/pci.c

708

cfg->bridge.br_pribus = REG(PCIR_PRIBUS_2, 1);

sys/dev/pci/pci.c

709

cfg->bridge.br_control = REG(PCIR_BRIDGECTL_2, 2);

sys/dev/pci/pci.c

710

cfg->subvendor = REG(PCIR_SUBVEND_2, 2);

sys/dev/pci/pci.c

711

cfg->subdevice = REG(PCIR_SUBDEV_2, 2);

sys/dev/pci/pci.c

725

vid = REG(PCIR_VENDOR, 2);

sys/dev/pci/pci.c

729

did = REG(PCIR_DEVICE, 2);

sys/dev/pci/pci.c

759

cfg->cmdreg = REG(PCIR_COMMAND, 2);

sys/dev/pci/pci.c

760

cfg->statreg = REG(PCIR_STATUS, 2);

sys/dev/pci/pci.c

761

cfg->baseclass = REG(PCIR_CLASS, 1);

sys/dev/pci/pci.c

762

cfg->subclass = REG(PCIR_SUBCLASS, 1);

sys/dev/pci/pci.c

763

cfg->progif = REG(PCIR_PROGIF, 1);

sys/dev/pci/pci.c

764

cfg->revid = REG(PCIR_REVID, 1);

sys/dev/pci/pci.c

765

cfg->hdrtype = REG(PCIR_HDRTYPE, 1);

sys/dev/pci/pci.c

766

cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);

sys/dev/pci/pci.c

767

cfg->lattimer = REG(PCIR_LATTIMER, 1);

sys/dev/pci/pci.c

768

cfg->intpin = REG(PCIR_INTPIN, 1);

sys/dev/pci/pci.c

769

cfg->intline = REG(PCIR_INTLINE, 1);

sys/dev/pci/pci.c

780

if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)

sys/dev/pci/pci.c

831

num_ent = REG(PCIR_EA_NUM_ENT, 2);

sys/dev/pci/pci.c

846

val = REG(ptr, 4);

sys/dev/pci/pci.c

851

dw[b] = REG(ptr, 4);

sys/dev/pci/pci.c

907

nextptr = REG(ptrptr, 1); /* sanity check? */

sys/dev/pci/pci.c

921

nextptr = REG(ptr + PCICAP_NEXTPTR, 1);

sys/dev/pci/pci.c

924

switch (REG(ptr + PCICAP_ID, 1)) {

sys/dev/pci/pci.c

927

cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);

sys/dev/pci/pci.c

931

val = REG(ptr + PCIR_HT_COMMAND, 2);

sys/dev/pci/pci.c

941

addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,

sys/dev/pci/pci.c

944

addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,

sys/dev/pci/pci.c

964

cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);

sys/dev/pci/pci.c

968

cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);

sys/dev/pci/pci.c

969

val = REG(ptr + PCIR_MSIX_TABLE, 4);

sys/dev/pci/pci.c

973

val = REG(ptr + PCIR_MSIX_PBA, 4);

sys/dev/pci/pci.c

985

val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);

sys/dev/sym/sym_defs.h

729

(0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/sym/sym_defs.h

732

(0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/sym/sym_defs.h

735

(0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))

sys/dev/sym/sym_defs.h

800

(0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/sym/sym_defs.h

803

(0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))

sys/dev/sym/sym_fw.h

201

#define RADDR_1(label) (RELOC_REGISTER | REG(label))

sys/dev/sym/sym_fw.h

202

#define RADDR_2(label,ofs) (RELOC_REGISTER | ((REG(label))+(ofs)))

sys/dev/uart/uart_dev_imx.c

100

GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),

sys/dev/uart/uart_dev_imx.c

101

GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));

sys/dev/uart/uart_dev_imx.c

131

i = (GETREG(bas, REG(UFCR)) & IMXUART_UFCR_RFDIV_MASK) >>

sys/dev/uart/uart_dev_imx.c

134

ubir = GETREG(bas, REG(UBIR)) + 1;

sys/dev/uart/uart_dev_imx.c

135

ubmr = GETREG(bas, REG(UBMR)) + 1;

sys/dev/uart/uart_dev_imx.c

158

SET(bas, REG(UCR1), FLD(UCR1, UARTEN));

sys/dev/uart/uart_dev_imx.c

159

SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN));

sys/dev/uart/uart_dev_imx.c

203

reg = GETREG(bas, REG(UFCR));

sys/dev/uart/uart_dev_imx.c

205

SETREG(bas, REG(UFCR), reg);

sys/dev/uart/uart_dev_imx.c

206

SETREG(bas, REG(UBIR), 15);

sys/dev/uart/uart_dev_imx.c

207

SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);

sys/dev/uart/uart_dev_imx.c

215

reg = GETREG(bas, REG(UFCR));

sys/dev/uart/uart_dev_imx.c

219

SETREG(bas, REG(UFCR), reg);

sys/dev/uart/uart_dev_imx.c

234

SETREG(bas, REG(UTXD), c);

sys/dev/uart/uart_dev_imx.c

253

c = GETREG(bas, REG(URXD));

sys/dev/uart/uart_dev_imx.c

394

SETREG(bas, REG(USR1), 0xffff);

sys/dev/uart/uart_dev_imx.c

395

SETREG(bas, REG(USR2), 0xffff);

sys/dev/uart/uart_dev_imx.c

432

SETREG(&sc->sc_bas, REG(UCR4), 0);

sys/dev/uart/uart_dev_imx.c

455

bes = GETREG(&sc->sc_bas, REG(USR2));

sys/dev/uart/uart_dev_imx.c

504

usr1 = GETREG(bas, REG(USR1));

sys/dev/uart/uart_dev_imx.c

505

usr2 = GETREG(bas, REG(USR2));

sys/dev/uart/uart_dev_imx.c

507

SETREG(bas, REG(USR1), usr1);

sys/dev/uart/uart_dev_imx.c

508

SETREG(bas, REG(USR2), usr2);

sys/dev/uart/uart_dev_imx.c

510

ucr1 = GETREG(bas, REG(UCR1));

sys/dev/uart/uart_dev_imx.c

511

ucr2 = GETREG(bas, REG(UCR2));

sys/dev/uart/uart_dev_imx.c

512

ucr4 = GETREG(bas, REG(UCR4));

sys/dev/uart/uart_dev_imx.c

595

xc = GETREG(bas, REG(URXD));

sys/dev/uart/uart_dev_imx.c

638

SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);

sys/dev/uart/uart_dev_imx.c

99

GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),

sys/dev/uart/uart_dev_imx.h

213

#define ENA(_bas, _r, _b) SET((_bas), REG(_r), FLD(_r, _b))

sys/dev/uart/uart_dev_imx.h

214

#define DIS(_bas, _r, _b) CLR((_bas), REG(_r), FLD(_r, _b))

sys/dev/uart/uart_dev_imx.h

215

#define IS(_bas, _r, _b) IS_SET((_bas), REG(_r), FLD(_r, _b))