sys/arm/freescale/imx/imx6_sdma.c

214

reg = READ4(sc, SDMAARM_EVTOVR);

sys/arm/freescale/imx/imx6_sdma.c

222

reg = READ4(sc, SDMAARM_HOSTOVR);

sys/arm/freescale/imx/imx6_sdma.c

230

reg = READ4(sc, SDMAARM_DSPOVR);

sys/arm/freescale/imx/imx6_sdma.c

333

while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {

sys/arm/freescale/imx/imx6_sdma.c

442

while (!(ret = READ4(sc, SDMAARM_INTR) & 1)) {

sys/arm/freescale/imx/imx6_sdma.c

94

pending = READ4(sc, SDMAARM_INTR);

sys/arm/freescale/imx/imx6_ssi.c

546

reg = READ4(sc, SSI_SIER);

sys/arm/freescale/imx/imx6_ssi.c

667

READ4(sc, SSI_SISR));

sys/arm/freescale/imx/imx6_ssi.c

676

reg = READ4(sc, SSI_STCCR);

sys/arm/freescale/imx/imx6_ssi.c

687

reg = READ4(sc, SSI_SFCSR);

sys/arm/freescale/imx/imx6_ssi.c

692

reg = READ4(sc, SSI_STCR);

sys/arm/freescale/imx/imx6_ssi.c

705

reg = READ4(sc, SSI_SCR);

sys/arm/freescale/imx/imx_gpio.c

380

wrk = READ4(sc, reg);

sys/arm/freescale/imx/imx_gpio.c

470

interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG);

sys/arm/freescale/imx/imx_gpio.c

549

pad = READ4(sc, IMX_GPIO_PSR_REG);

sys/arm/freescale/imx/imx_gpio.c

551

pad = READ4(sc, IMX_GPIO_DR_REG);

sys/arm/freescale/imx/imx_gpio.c

690

*val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1;

sys/arm/freescale/imx/imx_gpio.c

692

*val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1;

sys/arm/freescale/imx/imx_gpio.c

709

(READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin)));

sys/arm/freescale/imx/imx_gpio.c

727

*orig_pins = READ4(sc, IMX_GPIO_DR_REG);

sys/arm/freescale/imx/imx_gpio.c

732

(READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins);

sys/arm/freescale/imx/imx_gpio.c

753

pads = READ4(sc, IMX_GPIO_DR_REG);

sys/arm/freescale/imx/imx_gpio.c

76

WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))

sys/arm/freescale/imx/imx_gpio.c

773

(READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset);

sys/arm/freescale/imx/imx_gpio.c

775

(READ4(sc, IMX_GPIO_OE_REG) & ~oeclr) | oeset);

sys/arm/freescale/imx/imx_gpio.c

78

WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))

sys/arm/freescale/imx/imx_gpio.c

854

(READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT :

sys/arm/freescale/imx/imx_gpt.c

213

while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)

sys/arm/freescale/imx/imx_gpt.c

235

sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));

sys/arm/freescale/imx/imx_gpt.c

254

t1 = READ4(sc, IMX_GPT_CNT);

sys/arm/freescale/imx/imx_gpt.c

256

t2 = READ4(sc, IMX_GPT_CNT);

sys/arm/freescale/imx/imx_gpt.c

295

WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);

sys/arm/freescale/imx/imx_gpt.c

310

WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks);

sys/arm/freescale/imx/imx_gpt.c

343

status = READ4(sc, IMX_GPT_SR);

sys/arm/freescale/imx/imx_gpt.c

365

WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) +

sys/arm/freescale/imx/imx_gpt.c

378

return (READ4(sc, IMX_GPT_CNT));

sys/arm/freescale/imx/imx_gpt.c

411

curcnt = startcnt = READ4(sc, IMX_GPT_CNT);

sys/arm/freescale/imx/imx_gpt.c

414

curcnt = READ4(sc, IMX_GPT_CNT);

sys/arm/freescale/imx/imx_gpt.c

55

WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))

sys/arm/freescale/imx/imx_gpt.c

57

WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))

sys/arm/freescale/vybrid/vf_adc.c

155

return (READ4(sc, ADC_R0));

sys/arm/freescale/vybrid/vf_adc.c

168

reg = READ4(sc, ADC_HC0);

sys/arm/freescale/vybrid/vf_adc.c

205

reg = READ4(sc, ADC_CFG);

sys/arm/freescale/vybrid/vf_adc.c

211

reg = READ4(sc, ADC_GC);

sys/arm/freescale/vybrid/vf_adc.c

216

reg = READ4(sc, ADC_HC0);

sys/arm/freescale/vybrid/vf_anadig.c

134

reg = READ4(sc, pll_ctrl);

sys/arm/freescale/vybrid/vf_anadig.c

143

while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED))

sys/arm/freescale/vybrid/vf_anadig.c

146

reg = READ4(sc, pll_ctrl);

sys/arm/freescale/vybrid/vf_anadig.c

165

reg = READ4(sc, ANADIG_PLL4_CTRL);

sys/arm/freescale/vybrid/vf_anadig.c

206

reg = READ4(sc, ANADIG_REG_3P0);

sys/arm/freescale/vybrid/vf_anadig.c

211

reg = READ4(sc, USB_MISC(0));

sys/arm/freescale/vybrid/vf_anadig.c

215

reg = READ4(sc, USB_MISC(1));

sys/arm/freescale/vybrid/vf_anadig.c

221

READ4(sc, USB_ANALOG_USB_MISC(0)));

sys/arm/freescale/vybrid/vf_anadig.c

223

READ4(sc, USB_ANALOG_USB_MISC(1)));

sys/arm/freescale/vybrid/vf_ccm.c

377

reg = READ4(sc, clk->sel_reg);

sys/arm/freescale/vybrid/vf_ccm.c

383

reg = READ4(sc, clk->reg);

sys/arm/freescale/vybrid/vf_ccm.c

459

reg = READ4(sc, CCM_CCR);

sys/arm/freescale/vybrid/vf_ccm.c

465

if (READ4(sc, CCM_CSR) & FXOSC_RDY) {

sys/arm/freescale/vybrid/vf_dcu4.c

228

reg = READ4(sc, DCU_INT_STATUS);

sys/arm/freescale/vybrid/vf_dcu4.c

350

reg = READ4(sc, DCU_DCU_MODE);

sys/arm/freescale/vybrid/vf_edma.c

100

interrupts = READ4(sc, DMA_INT);

sys/arm/freescale/vybrid/vf_edma.c

125

/* reg = */ READ4(sc, DMA_ERR);

sys/arm/freescale/vybrid/vf_edma.c

129

reg, READ4(sc, DMA_ES));

sys/arm/freescale/vybrid/vf_edma.c

198

reg = READ4(sc, DMA_ERQ);

sys/arm/freescale/vybrid/vf_edma.c

245

reg = READ4(sc, DMA_ERQ);

sys/arm/freescale/vybrid/vf_edma.c

250

reg = READ4(sc, DMA_EEI);

sys/arm/freescale/vybrid/vf_gpio.c

144

(READ4(sc, GPIO_PDOR(i)) & (1 << (i % 32))) ?

sys/arm/freescale/vybrid/vf_gpio.c

261

*val = (READ4(sc, GPIO_PDIR(i)) & (1 << (i % 32))) ? 1 : 0;

sys/arm/freescale/vybrid/vf_port.c

116

reg = READ4(sc, PORT_PCR(i));

sys/arm/freescale/vybrid/vf_port.c

173

reg = READ4(sc, PORT_PCR(pnum));

sys/arm/freescale/vybrid/vf_sai.c

355

reg = READ4(sc, I2S_TCR2);

sys/arm/freescale/vybrid/vf_sai.c

609

READ4(sc, I2S_TCSR));

sys/arm/freescale/vybrid/vf_sai.c

621

reg = READ4(sc, I2S_TCSR);

sys/arm/freescale/vybrid/vf_sai.c

625

reg = READ4(sc, I2S_TCR3);

sys/arm/freescale/vybrid/vf_sai.c

632

reg = READ4(sc, I2S_TCR2);

sys/arm/freescale/vybrid/vf_sai.c

640

reg = READ4(sc, I2S_TCR3);

sys/arm/freescale/vybrid/vf_sai.c

645

reg = READ4(sc, I2S_TCR4);

sys/arm/freescale/vybrid/vf_sai.c

653

reg = READ4(sc, I2S_TCR5);

sys/arm/freescale/vybrid/vf_sai.c

663

reg = READ4(sc, I2S_TCSR);

sys/arm/freescale/vybrid/vf_spi.c

160

reg = READ4(sc, SPI_MCR);

sys/arm/freescale/vybrid/vf_spi.c

168

reg = READ4(sc, SPI_RSER);

sys/arm/freescale/vybrid/vf_spi.c

172

reg = READ4(sc, SPI_MCR);

sys/arm/freescale/vybrid/vf_spi.c

176

reg = READ4(sc, SPI_CTAR0);

sys/arm/freescale/vybrid/vf_spi.c

194

reg = READ4(sc, SPI_CTAR0);

sys/arm/freescale/vybrid/vf_spi.c

229

while((READ4(sc, SPI_SR) & SR_EOQF) == 0)

sys/arm/freescale/vybrid/vf_spi.c

232

reg = READ4(sc, SPI_SR);

sys/arm/freescale/vybrid/vf_spi.c

238

while((READ4(sc, SPI_SR) & SR_RFDF) == 0)

sys/arm/ti/clk/ti_clk_clkctrl.c

100

READ4(clk, sc->register_offset, &val);

sys/arm/ti/clk/ti_clk_clkctrl.c

118

READ4(clk, sc->register_offset, &val);

sys/arm/ti/clk/ti_clk_clkctrl.c

150

READ4(clk, sc->register_offset, &val);

sys/arm/ti/clk/ti_clk_clkctrl.c

158

READ4(clk, sc->register_offset, &val);

sys/arm/ti/clk/ti_clk_dpll.c

215

READ4(clk, sc->ti_idlest_offset, &val);

sys/arm/ti/clk/ti_clk_dpll.c

224

READ4(clk, sc->ti_clksel_offset, &val);

sys/arm/ti/clk/ti_clk_dpll.c

248

READ4(clk, sc->ti_idlest_offset, &val);

sys/arm/ti/clk/ti_clk_dpll.c

271

READ4(clk, sc->ti_clksel_offset, &val);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

102

READ4(clk, sc->offset, &val);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

123

READ4(clk, sc->offset, &val);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

141

READ4(clk, sc->offset, &reg);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

266

READ4(clk, sc->offset, &val);

sys/arm64/freescale/imx/clk/imx_clk_composite.c

83

READ4(clk, sc->offset, &val);

sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c

100

READ4(clk, sc->offset + CFG0, &cfg0);

sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c

122

READ4(clk, sc->offset + CFG0, &cfg0);

sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c

123

READ4(clk, sc->offset + CFG1, &cfg1);

sys/arm64/freescale/imx/clk/imx_clk_frac_pll.c

90

READ4(clk, sc->offset + CFG0, &cfg0);

sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c

109

READ4(clk, sc->offset + CFG0, &cfg0);

sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c

131

READ4(clk, sc->offset + CFG0, &cfg0);

sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c

132

READ4(clk, sc->offset + CFG2, &cfg2);

sys/arm64/freescale/imx/clk/imx_clk_sscg_pll.c

99

READ4(clk, sc->offset + CFG0, &cfg0);

sys/dev/agp/agp_amd.c

370

} while (READ4(AGP_AMD751_TLBCTRL));

sys/dev/agp/agp_ati.c

342

(void)READ4(ATI_GART_CACHE_CNTRL);

sys/dev/clk/allwinner/aw_clk_frac.c

111

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_frac.c

135

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_frac.c

264

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_frac.c

296

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_frac.c

317

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_frac.c

87

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_m.c

101

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_m.c

124

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_m.c

207

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_m.c

231

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_m.c

79

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_mipi.c

172

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_mipi.c

196

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_mipi.c

217

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_mipi.c

96

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

106

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

129

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

197

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

239

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

284

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

299

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

308

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

331

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nkmp.c

84

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nm.c

102

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nm.c

125

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nm.c

237

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nm.c

251

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nm.c

273

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nm.c

80

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nmm.c

172

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nmm.c

189

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nmm.c

211

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_nmm.c

89

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_np.c

164

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_np.c

178

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_np.c

200

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_np.c

88

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_prediv_mux.c

115

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_prediv_mux.c

78

READ4(clk, sc->offset, &val);

sys/dev/clk/allwinner/aw_clk_prediv_mux.c

97

READ4(clk, sc->offset, &val);

sys/dev/clk/rockchip/rk_clk_armclk.c

127

READ4(clk, sc->muxdiv_offset, &reg);

sys/dev/clk/rockchip/rk_clk_armclk.c

88

READ4(clk, sc->muxdiv_offset, &val);

sys/dev/clk/rockchip/rk_clk_composite.c

133

READ4(clk, sc->muxdiv_offset, &val);

sys/dev/clk/rockchip/rk_clk_composite.c

176

READ4(clk, sc->muxdiv_offset, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

128

READ4(clk, sc->mode_reg, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

167

READ4(clk, sc->base_offset, &raw0);

sys/dev/clk/rockchip/rk_clk_pll.c

168

READ4(clk, sc->base_offset + 4, &raw1);

sys/dev/clk/rockchip/rk_clk_pll.c

169

READ4(clk, sc->base_offset + 8, &raw2);

sys/dev/clk/rockchip/rk_clk_pll.c

170

READ4(clk, sc->mode_reg, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

250

READ4(clk, sc->base_offset + 4, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

270

READ4(clk, sc->base_offset + 0x4, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

389

READ4(clk, sc->base_offset, &raw1);

sys/dev/clk/rockchip/rk_clk_pll.c

390

READ4(clk, sc->base_offset + 4, &raw2);

sys/dev/clk/rockchip/rk_clk_pll.c

391

READ4(clk, sc->base_offset + 8, &raw3);

sys/dev/clk/rockchip/rk_clk_pll.c

474

READ4(clk, sc->base_offset + 0x8, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

482

READ4(clk, sc->base_offset + 0x4, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

596

READ4(clk, sc->base_offset, &con1);

sys/dev/clk/rockchip/rk_clk_pll.c

597

READ4(clk, sc->base_offset + 4, &con2);

sys/dev/clk/rockchip/rk_clk_pll.c

598

READ4(clk, sc->base_offset + 8, &con3);

sys/dev/clk/rockchip/rk_clk_pll.c

599

READ4(clk, sc->base_offset + 0xC, &con4);

sys/dev/clk/rockchip/rk_clk_pll.c

710

READ4(clk, sc->base_offset + 0x8, &reg);

sys/dev/clk/rockchip/rk_clk_pll.c

722

READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, &reg);

sys/dev/clk/starfive/jh7110_clk.c

117

reg = READ4(sc, sc_clk->offset);

sys/dev/clk/starfive/jh7110_clk.c

142

reg = READ4(sc, sc_clk->offset);

sys/dev/clk/starfive/jh7110_clk.c

173

reg = READ4(sc, sc_clk->offset) & ~JH7110_MUX_MASK;

sys/dev/clk/starfive/jh7110_clk.c

198

divisor = READ4(sc, sc_clk->offset) & JH7110_DIV_MASK;

sys/dev/clk/starfive/jh7110_clk.c

231

divisor |= READ4(sc, sc_clk->offset) & ~JH7110_DIV_MASK;

sys/dev/clk/starfive/jh7110_clk.c

68

regvalue = READ4(sc, offset);

sys/dev/clk/starfive/jh7110_clk.c

92

regvalue = READ4(sc, offset);

sys/dev/dwc/dwc1000_core.c

106

if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {

sys/dev/dwc/dwc1000_core.c

107

rv = READ4(sc, GMII_DATA);

sys/dev/dwc/dwc1000_core.c

134

if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {

sys/dev/dwc/dwc1000_core.c

166

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

215

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

226

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

240

reg = READ4(sc, MAC_CONFIGURATION);

sys/dev/dwc/dwc1000_core.c

368

lo = READ4(sc, MAC_ADDRESS_LOW(0));

sys/dev/dwc/dwc1000_core.c

369

hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;

sys/dev/dwc/dwc1000_core.c

397

reg = READ4(sc, MMC_CONTROL);

sys/dev/dwc/dwc1000_core.c

415

READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +

sys/dev/dwc/dwc1000_core.c

416

READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +

sys/dev/dwc/dwc1000_core.c

417

READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +

sys/dev/dwc/dwc1000_core.c

418

READ4(sc, RXLENGTHERROR));

sys/dev/dwc/dwc1000_core.c

421

READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +

sys/dev/dwc/dwc1000_core.c

422

READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));

sys/dev/dwc/dwc1000_core.c

425

READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));

sys/dev/dwc/dwc1000_core.c

437

reg = READ4(sc, INTERRUPT_STATUS);

sys/dev/dwc/dwc1000_core.c

439

READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);

sys/dev/dwc/dwc1000_dma.c

545

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

554

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

570

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

575

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

580

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

591

reg = READ4(sc, BUS_MODE);

sys/dev/dwc/dwc1000_dma.c

596

if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)

sys/dev/dwc/dwc1000_dma.c

633

reg = READ4(sc, HW_FEATURE);

sys/dev/dwc/dwc1000_dma.c

640

reg = READ4(sc, OPERATION_MODE);

sys/dev/dwc/dwc1000_dma.c

862

reg = READ4(sc, DMA_STATUS);

sys/dev/flash/cqspi.c

150

pending = READ4(sc, CQSPI_IRQSTAT);

sys/dev/flash/cqspi.c

237

if ((READ4(sc, CQSPI_FLASHCMD) & FLASHCMD_CMDEXECSTAT) == 0) {

sys/dev/flash/cqspi.c

244

__func__, READ4(sc, CQSPI_FLASHCMD));

sys/dev/flash/cqspi.c

325

data = READ4(sc, CQSPI_FLASHCMDRDDATALO);

sys/dev/flash/cqspi.c

379

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

526

READ4(sc, CQSPI_MODULEID));

sys/dev/flash/cqspi.c

551

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

555

reg = READ4(sc, CQSPI_DEVSZ);

sys/dev/flash/cqspi.c

564

reg = READ4(sc, CQSPI_CFG);

sys/dev/flash/cqspi.c

577

READ4(sc, CQSPI_RDDATACAP);

sys/dev/flash/cqspi.c

583

reg = READ4(sc, CQSPI_CFG);

sys/dev/gpio/dwgpio/dwgpio.c

151

version = READ4(sc, GPIO_VER_ID_CODE);

sys/dev/gpio/dwgpio/dwgpio.c

156

cfg2 = READ4(sc, GPIO_CONFIG_REG2);

sys/dev/gpio/dwgpio/dwgpio.c

165

(READ4(sc, GPIO_SWPORT_DDR(sc->port)) & (1 << i)) ?

sys/dev/gpio/dwgpio/dwgpio.c

284

*val = (READ4(sc, GPIO_EXT_PORT(sc->port)) & (1 << i)) ? 1 : 0;

sys/dev/gpio/dwgpio/dwgpio.c

307

reg = READ4(sc, GPIO_SWPORT_DR(sc->port));

sys/dev/gpio/dwgpio/dwgpio.c

331

reg = READ4(sc, GPIO_SWPORT_DDR(sc->port));

sys/dev/gpio/dwgpio/dwgpio.c

386

reg = READ4(sc, GPIO_SWPORT_DR(sc->port));

sys/dev/mmc/host/dwmmc.c

1045

status = READ4(sc, SDMMC_STATUS);

sys/dev/mmc/host/dwmmc.c

1048

*p++ = READ4(sc, SDMMC_DATA);

sys/dev/mmc/host/dwmmc.c

1072

status = READ4(sc, SDMMC_STATUS);

sys/dev/mmc/host/dwmmc.c

1209

while (READ4(sc, SDMMC_STATUS) & (SDMMC_STATUS_DATA_BUSY))

sys/dev/mmc/host/dwmmc.c

214

reg = READ4(sc, SDMMC_CTRL);

sys/dev/mmc/host/dwmmc.c

220

if (!(READ4(sc, SDMMC_CTRL) & reset_bits))

sys/dev/mmc/host/dwmmc.c

326

cmd->resp[3] = READ4(sc, SDMMC_RESP0);

sys/dev/mmc/host/dwmmc.c

327

cmd->resp[2] = READ4(sc, SDMMC_RESP1);

sys/dev/mmc/host/dwmmc.c

328

cmd->resp[1] = READ4(sc, SDMMC_RESP2);

sys/dev/mmc/host/dwmmc.c

329

cmd->resp[0] = READ4(sc, SDMMC_RESP3);

sys/dev/mmc/host/dwmmc.c

334

cmd->resp[0] = READ4(sc, SDMMC_RESP0);

sys/dev/mmc/host/dwmmc.c

382

reg = READ4(sc, SDMMC_MINTSTS);

sys/dev/mmc/host/dwmmc.c

415

READ4(sc, SDMMC_CDETECT) == 0 ? true : false);

sys/dev/mmc/host/dwmmc.c

431

reg = READ4(sc, SDMMC_IDSTS);

sys/dev/mmc/host/dwmmc.c

475

if (READ4(sc, SDMMC_CDETECT) == 0 ||

sys/dev/mmc/host/dwmmc.c

693

READ4(sc, SDMMC_VERID) & 0xffff);

sys/dev/mmc/host/dwmmc.c

705

((READ4(sc, SDMMC_FIFOTH) >> SDMMC_FIFOTH_RXWMARK_S) & 0xfff);

sys/dev/mmc/host/dwmmc.c

823

} while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);

sys/dev/mmc/host/dwmmc.c

843

} while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);

sys/dev/mmc/host/dwmmc.c

855

} while (READ4(sc, SDMMC_CMD) & SDMMC_CMD_START);

sys/dev/mmc/host/dwmmc.c

900

reg = READ4(sc, SDMMC_UHS_REG);

sys/dev/mmc/host/dwmmc.c

944

reg = READ4(sc, SDMMC_CTRL);

sys/dev/mmc/host/dwmmc.c

949

reg = READ4(sc, SDMMC_BMOD);

sys/dev/mmc/host/dwmmc.c

966

reg = READ4(sc, SDMMC_INTMASK);

sys/dev/mmc/host/dwmmc.c

994

reg = READ4(sc, SDMMC_CTRL);

sys/dev/mmc/host/dwmmc.c

999

reg = READ4(sc, SDMMC_BMOD);

sys/dev/rtsx/rtsx.c

1344

reg = READ4(sc, RTSX_HAIMR);

sys/dev/rtsx/rtsx.c

1400

reg = READ4(sc, RTSX_HAIMR);

sys/dev/rtsx/rtsx.c

556

status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */

sys/dev/rtsx/rtsx.c

713

status = READ4(sc, RTSX_BIPR);

sys/dev/xdma/controller/pl330.c

164

pending = READ4(sc, INTMIS);

sys/dev/xdma/controller/pl330.c

167

__func__, pending, READ4(sc, LC0(0)),

sys/dev/xdma/controller/pl330.c

168

READ4(sc, SAR(0)), READ4(sc, DAR(0)));

sys/dev/xilinx/axi_quad_spi.c

172

while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY))

sys/dev/xilinx/axi_quad_spi.c

175

data = READ4(sc, SPI_DRR);

sys/dev/xilinx/axi_quad_spi.c

203

reg = READ4(sc, SPI_SSR);

sys/dev/xilinx/axi_quad_spi.c

214

reg = READ4(sc, SPI_SSR);