sys/arm/nvidia/tegra124/tegra124_clk_pll.c

218

PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

229

PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

242

PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

255

PLL(TEGRA124_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

266

PLL(TEGRA124_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

277

PLL(TEGRA124_CLK_PLL_C4, "pllC4_out0", "pllC4_src"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

290

PLL(TEGRA124_CLK_PLL_P, "pllP_out0", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

300

PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

310

PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

321

PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

331

PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

344

PLL(0, "pllREFE_out", "osc_div_clk"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

357

PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),

sys/arm/nvidia/tegra124/tegra124_clk_pll.c

367

PLL(0, "pllDP_out0", "pllDP_src"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

272

PLL(TEGRA210_CLK_PLL_M, "pllM_out0", "osc"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

284

PLL(TEGRA210_CLK_PLL_M, "pllMB_out0", "osc"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

296

PLL(TEGRA210_CLK_PLL_X, "pllX_out0", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

308

PLL(TEGRA210_CLK_PLL_C, "pllC_out0", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

319

PLL(TEGRA210_CLK_PLL_C2, "pllC2_out0", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

330

PLL(TEGRA210_CLK_PLL_C3, "pllC3_out0", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

341

PLL(TEGRA210_CLK_PLL_C4, "pllC4", "pllC4_src"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

358

PLL(TEGRA210_CLK_PLL_P, "pllP_out0", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

370

PLL(TEGRA210_CLK_PLL_A, "pllA", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

382

PLL(TEGRA210_CLK_PLL_A1, "pllA1_out0", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

393

PLL(TEGRA210_CLK_PLL_U, "pllU", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

406

PLL(TEGRA210_CLK_PLL_D, "pllD_out", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

418

PLL(TEGRA210_CLK_PLL_D2, "pllD2_out", "pllD2_src"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

431

PLL(0, "pllREFE", "osc_div_clk"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

444

PLL(TEGRA210_CLK_PLL_E, "pllE_out0", "pllE_src"),

sys/arm64/nvidia/tegra210/tegra210_clk_pll.c

454

PLL(0, "pllDP_out0", "pllDP_src"),

sys/arm64/qoriq/clk/lx2160a_clkgen.c

67

PLL(QORIQ_TYPE_PLATFORM_PLL, 0, "platform_pll", 0x60080, plt_divs);

sys/arm64/qoriq/clk/lx2160a_clkgen.c

69

PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cga_divs);

sys/arm64/qoriq/clk/lx2160a_clkgen.c

71

PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cga_divs);

sys/arm64/qoriq/clk/lx2160a_clkgen.c

73

PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cgb_divs);

sys/arm64/qoriq/clk/lx2160a_clkgen.c

75

PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cgb_divs);

sys/arm64/qoriq/clk/lx2160a_clkgen.c

87

{PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll1", 0x80, cg_divs)},

sys/arm64/qoriq/clk/lx2160a_clkgen.c

89

{PLL(QORIQ_TYPE_INTERNAL, 0, "cga_pll2", 0xA0, cg_divs)},

sys/arm64/qoriq/clk/lx2160a_clkgen.c

91

{PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll1", 0x10080, cg_divs)},

sys/arm64/qoriq/clk/lx2160a_clkgen.c

93

{PLL(QORIQ_TYPE_INTERNAL, 0, "cgb_pll2", 0x100A0, cg_divs)},

sys/dev/clk/rockchip/rk3288_cru.c

581

PLL(PLL_APLL, "apll", CRU_APLL_CON(0), 0),

sys/dev/clk/rockchip/rk3288_cru.c

582

PLL(PLL_DPLL, "dpll", CRU_DPLL_CON(0), 4),

sys/dev/clk/rockchip/rk3288_cru.c

583

PLL(PLL_CPLL, "cpll", CRU_CPLL_CON(0), 8),

sys/dev/clk/rockchip/rk3288_cru.c

584

PLL(PLL_GPLL, "gpll", CRU_GPLL_CON(0), 12),

sys/dev/clk/rockchip/rk3288_cru.c

585

PLL(PLL_NPLL, "npll", CRU_NPLL_CON(0), 14),

sys/dev/clk/rockchip/rk3399_cru.c

783

PLL(PLL_APLLL, "lpll", 0x00),

sys/dev/clk/rockchip/rk3399_cru.c

784

PLL(PLL_APLLB, "bpll", 0x20),

sys/dev/clk/rockchip/rk3399_cru.c

785

PLL(PLL_DPLL, "dpll", 0x40),

sys/dev/clk/rockchip/rk3399_cru.c

786

PLL(PLL_CPLL, "cpll", 0x60),

sys/dev/clk/rockchip/rk3399_cru.c

787

PLL(PLL_GPLL, "gpll", 0x80),

sys/dev/clk/rockchip/rk3399_cru.c

788

PLL(PLL_NPLL, "npll", 0xA0),

sys/dev/clk/rockchip/rk3399_cru.c

789

PLL(PLL_VPLL, "vpll", 0xC0),

sys/dev/clk/starfive/jh7110_clk_pll.c

50

sc->dacpd_mask = PLL## id ##_DACPD_MASK; \

sys/dev/clk/starfive/jh7110_clk_pll.c

51

sc->dsmpd_mask = PLL## id ##_DSMPD_MASK; \

sys/dev/clk/starfive/jh7110_clk_pll.c

52

sc->fbdiv_mask = PLL## id ##_FBDIV_MASK; \

sys/dev/clk/starfive/jh7110_clk_pll.c

53

sc->frac_mask = PLL## id ##_FRAC_MASK; \

sys/dev/clk/starfive/jh7110_clk_pll.c

54

sc->prediv_mask = PLL## id ##_PREDIV_MASK; \

sys/dev/clk/starfive/jh7110_clk_pll.c

55

sc->postdiv1_mask = PLL## id ##_POSTDIV1_MASK; \

sys/dev/clk/starfive/jh7110_clk_pll.c

60

sc->dacpd_shift = PLL## id ##_DACPD_SHIFT; \

sys/dev/clk/starfive/jh7110_clk_pll.c

61

sc->dsmpd_shift = PLL## id ##_DSMPD_SHIFT; \

sys/dev/clk/starfive/jh7110_clk_pll.c

62

sc->fbdiv_shift = PLL## id ##_FBDIV_SHIFT; \

sys/dev/clk/starfive/jh7110_clk_pll.c

63

sc->frac_shift = PLL## id ##_FRAC_SHIFT; \

sys/dev/clk/starfive/jh7110_clk_pll.c

64

sc->prediv_shift = PLL## id ##_PREDIV_SHIFT; \

sys/dev/clk/starfive/jh7110_clk_pll.c

65

sc->postdiv1_shift = PLL## id ##_POSTDIV1_SHIFT; \

sys/riscv/sifive/sifive_prci.c

118

#define PLL_END PLL(0, NULL, 0)

sys/riscv/sifive/sifive_prci.c

177

PLL(FU540_PRCI_CORECLK, "coreclk", FU540_PRCI_COREPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

178

PLL(FU540_PRCI_DDRCLK, "ddrclk", FU540_PRCI_DDRPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

179

PLL(FU540_PRCI_GEMGXLCLK, "gemgxlclk", FU540_PRCI_GEMGXLPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

224

PLL(FU740_PRCI_CORECLK, "coreclk", FU740_PRCI_COREPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

225

PLL(FU740_PRCI_DDRCLK, "ddrclk", FU740_PRCI_DDRPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

226

PLL(FU740_PRCI_GEMGXLCLK, "gemgxlclk", FU740_PRCI_GEMGXLPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

227

PLL(FU740_PRCI_DVFSCORECLK, "dvfscoreclk", FU740_PRCI_DVFSCOREPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

228

PLL(FU740_PRCI_HFPCLK, "hfpclk", FU740_PRCI_HFPCLKPLL_CFG0),

sys/riscv/sifive/sifive_prci.c

229

PLL(FU740_PRCI_CLTXCLK, "cltxclk", FU740_PRCI_CLTXPLL_CFG0),