sys/arm/mv/mv_pci.c

782

mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,

sys/dev/pci/pci.c

5672

case PCIR_IOBASEL_1:

sys/dev/pci/pci.c

5763

case PCIR_IOBASEL_1:

sys/dev/pci/pci_pci.c

1619

pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);

sys/dev/pci/pci_pci.c

214

val = pci_read_config(dev, PCIR_IOBASEL_1, 1);

sys/dev/pci/pci_pci.c

221

pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);

sys/dev/pci/pci_pci.c

501

val = pci_read_config(dev, PCIR_IOBASEL_1, 1);

sys/dev/pci/pci_pci.c

507

pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);

sys/dev/pci/pci_pci.c

508

if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {

sys/dev/pci/pci_pci.c

510

pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);

sys/dev/pci/pci_pci.c

517

sc->io.reg = PCIR_IOBASEL_1;

sys/riscv/sifive/fu740_pci_dw.c

304

pci_dw_dbi_wr2(sc->dev, PCIR_IOBASEL_1,

usr.sbin/pciconf/pciconf.c

644

val = read_config(fd, &p->pc_sel, PCIR_IOBASEL_1, 1);

usr.sbin/pciconf/pciconf.c

660

print_window(PCIR_IOBASEL_1, "I/O Port", range, base, limit);