sys/arm/mv/a37x0_spi.c

174

A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);

sys/arm/mv/a37x0_spi.c

178

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_FIFO_FLUSH);

sys/arm/mv/a37x0_spi.c

189

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_SRST);

sys/arm/mv/a37x0_spi.c

193

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

196

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_MASK, 0);

sys/arm/mv/a37x0_spi.c

198

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);

sys/arm/mv/a37x0_spi.c

279

A37X0_SPI_WRITE(sc, A37X0_SPI_DATA_OUT, p[written]);

sys/arm/mv/a37x0_spi.c

295

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

308

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

333

A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);

sys/arm/mv/a37x0_spi.c

356

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, status);

sys/arm/mv/a37x0_spi.c

419

A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, 1 << (A37X0_SPI_CS_SHIFT + cs));

sys/arm/mv/a37x0_spi.c

429

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);

sys/arm/mv/a37x0_spi.c

451

A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);

sys/arm/mv/a37x0_spi.c

452

A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_MASK, 0);