MLX5_ST_SZ_DW
u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
u32 match_value[MLX5_ST_SZ_DW(fte_match_param)];
u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
u32 in[MLX5_ST_SZ_DW(create_ipsec_obj_in)] = {};
u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {};
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
u32 in[MLX5_ST_SZ_DW(modify_ipsec_obj_in)] = {};
u32 out[MLX5_ST_SZ_DW(query_ipsec_obj_out)];
u32 match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { };
u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { };
u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { };
u32 in[MLX5_ST_SZ_DW(query_cong_status_in)] = { };
u32 out[MLX5_ST_SZ_DW(modify_cong_status_out)] = { };
u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {0};
u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {};
u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {};
u32 out[MLX5_ST_SZ_DW(create_encryption_key_out)] = {};
u32 in[MLX5_ST_SZ_DW(destroy_encryption_key_in)] = {};
u32 out[MLX5_ST_SZ_DW(destroy_encryption_key_out)] = {};
u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)] = {0};
int in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
int out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {};
u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {};
u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {};
u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {};
u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {};
u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {};
u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {};
u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {0};
u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {};
u32 out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {};
u32 in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {};
u32 in[MLX5_ST_SZ_DW(dealloc_flow_counter_in)] = {};
u32 in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {};
u32 in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {};
u32 out[MLX5_ST_SZ_DW(alloc_packet_reformat_context_out)] = {};
u32 in[MLX5_ST_SZ_DW(dealloc_packet_reformat_context_in)] = {};
u32 out[MLX5_ST_SZ_DW(alloc_modify_header_context_out)] = {};
u32 in[MLX5_ST_SZ_DW(dealloc_modify_header_context_in)] = {};
u32 in[MLX5_ST_SZ_DW(init_hca_in)];
u32 out[MLX5_ST_SZ_DW(init_hca_out)];
u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
u32 out[MLX5_ST_SZ_DW(mcc_reg)];
u32 in[MLX5_ST_SZ_DW(mcc_reg)];
u32 out[MLX5_ST_SZ_DW(mcc_reg)];
u32 in[MLX5_ST_SZ_DW(mcc_reg)];
u32 out[MLX5_ST_SZ_DW(mcda_reg)];
u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
int offset = MLX5_ST_SZ_DW(mcqi_reg);
u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {0};
u32 out[MLX5_ST_SZ_DW(attach_to_mcg_out)] = {0};
u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {0};
u32 out[MLX5_ST_SZ_DW(detach_from_mcg_out)] = {0};
u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {};
u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {};
u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {};
u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {};
u32 out[MLX5_ST_SZ_DW(destroy_mkey_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {0};
u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {0};
u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_psv_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {0};
u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_pages_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_pages_out)] = {0};
u32 out[MLX5_ST_SZ_DW(manage_pages_out)] = {0};
u32 in[MLX5_ST_SZ_DW(manage_pages_in)] = {0};
u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {0};
u32 out[MLX5_ST_SZ_DW(dealloc_pd_out)] = {0};
u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {};
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = {0};
u32 out[MLX5_ST_SZ_DW(set_diagnostic_params_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_diagnostic_counters_in)] = {0};
u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
u32 out[MLX5_ST_SZ_DW(qpts_reg)] = {};
u32 in[MLX5_ST_SZ_DW(qpts_reg)] = {};
u32 in[MLX5_ST_SZ_DW(pddr_reg)] = {0};
u32 pddr_reg[MLX5_ST_SZ_DW(pddr_reg)] = {};
u32 pddr_reg[MLX5_ST_SZ_DW(pddr_reg)] = {};
u32 out[MLX5_ST_SZ_DW(pddr_reg)] = {0};
u32 mfrl[MLX5_ST_SZ_DW(mfrl_reg)] = {};
u32 mfrl[MLX5_ST_SZ_DW(mfrl_reg)] = {};
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 in[MLX5_ST_SZ_DW(ptys_reg)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(paos_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(paos_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(paos_reg)];
u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(pmtu_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {};
u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)] = {0};
u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_delay_drop_params_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_delay_drop_params_out)] = {0};
u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)] = {0};
u32 out[MLX5_ST_SZ_DW(set_delay_drop_params_out)] = {0};
u32 in[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(pmlp_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(mcia_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(mcia_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {};
u32 in[MLX5_ST_SZ_DW(add_vxlan_udp_dport_in)] = {0};
u32 out[MLX5_ST_SZ_DW(add_vxlan_udp_dport_out)] = {0};
u32 in[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_in)] = {0};
u32 out[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_cong_status_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_cong_status_out)] = {0};
u32 in[MLX5_ST_SZ_DW(modify_cong_status_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_cong_status_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = {0};
u32 in[MLX5_ST_SZ_DW(qetc_reg)];
u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {};
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {};
u32 in[MLX5_ST_SZ_DW(qtct_reg)];
u32 out[MLX5_ST_SZ_DW(qtct_reg)];
u32 in[MLX5_ST_SZ_DW(qtct_reg)] = {};
u32 out[MLX5_ST_SZ_DW(qtct_reg)];
u32 in[MLX5_ST_SZ_DW(qetc_reg)] = {};
u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {};
u32 out[MLX5_ST_SZ_DW(qetc_reg)];
u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
u32 dout[MLX5_ST_SZ_DW(destroy_qp_out)] = {0};
u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_qp_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {0};
u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {0};
u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {0};
u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {0};
u32 out[MLX5_ST_SZ_DW(dealloc_xrcd_out)] = {0};
u32 dout[MLX5_ST_SZ_DW(destroy_dct_out)] = {0};
u32 din[MLX5_ST_SZ_DW(destroy_dct_in)] = {0};
u32 out[MLX5_ST_SZ_DW(drain_dct_out)] = {0};
u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_dct_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {0};
u32 out[MLX5_ST_SZ_DW(arm_dct_out)] = {0};
u32 in[MLX5_ST_SZ_DW(arm_dct_in)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {};
u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {};
u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {};
u32 out[MLX5_ST_SZ_DW(destroy_sq_out)] = {};
u32 in[MLX5_ST_SZ_DW(set_rate_limit_in)] = {};
u32 out[MLX5_ST_SZ_DW(set_rate_limit_out)] = {};
u32 in[MLX5_ST_SZ_DW(query_pp_rate_limit_in)] = {};
u32 out[MLX5_ST_SZ_DW(query_pp_rate_limit_out)] = {};
u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0};
u32 srq_out[MLX5_ST_SZ_DW(destroy_srq_out)] = {0};
u32 srq_in[MLX5_ST_SZ_DW(destroy_srq_in)] = {0};
u32 srq_in[MLX5_ST_SZ_DW(query_srq_in)] = {0};
u32 srq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0};
u32 srq_out[MLX5_ST_SZ_DW(arm_xrc_srq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_sq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_tir_out)] = {0};
u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_tis_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_tis_out)] = {0};
u32 out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_rmp_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_rmp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_rmp_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_rmp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(create_xrc_srq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_xrc_srq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_xrc_srq_in)] = {0};
u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
u32 in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(arm_xrc_srq_out)] = {0};
u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {0};
u32 out[MLX5_ST_SZ_DW(dealloc_transport_domain_out)] = {0};
u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0};
u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0};
u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0};
u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0};
u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0};
u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_hca_vport_context_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_esw_vport_context_out)] = {0};
u32 in[MLX5_ST_SZ_DW(modify_esw_vport_context_in)];
u32 in[MLX5_ST_SZ_DW(alloc_q_counter_in)] = {0};
u32 out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
u32 in[MLX5_ST_SZ_DW(dealloc_q_counter_in)] = {0};
u32 out[MLX5_ST_SZ_DW(dealloc_q_counter_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {0};
u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
u32 in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {0};
u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0};
u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_vport_state_out)] = {0};
u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {0};
u32 rqc [MLX5_ST_SZ_DW(rqc)];
u32 sqc [MLX5_ST_SZ_DW(sqc)];
u32 cqc [MLX5_ST_SZ_DW(cqc)];
u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
u32 out_cap[MLX5_ST_SZ_DW(mtcap)] = {};
u32 out_sensor[MLX5_ST_SZ_DW(mtmp_reg)] = {};
u32 out[MLX5_ST_SZ_DW(create_cq_out)];
u32 in[MLX5_ST_SZ_DW(create_tis_in)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
u32 in[MLX5_ST_SZ_DW(create_tis_in)];
u32 fpga_qpc[MLX5_ST_SZ_DW(fpga_qpc)];
u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)];
u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)];
u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)];
u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_destroy_qp_out)];
u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_query_qp_counters_out)];
u32 in[MLX5_ST_SZ_DW(fpga_shell_counters)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_shell_counters)];
#define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
u32 temp_cqc[MLX5_ST_SZ_DW(cqc)] = {0};
u32 temp_qpc[MLX5_ST_SZ_DW(qpc)] = {0};
u32 caps[MLX5_ST_SZ_DW(ipsec_extended_cap)];
u32 header[MLX5_ST_SZ_DW(fpga_shell_qp_packet)];
CTASSERT(MLX5_FPGA_CAP_ARR_SZ == MLX5_ST_SZ_DW(fpga_cap));
u32 fpga_cap[MLX5_ST_SZ_DW(fpga_cap)] = {0};
u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
uint32_t out[MLX5_ST_SZ_DW(query_cong_status_out)] = {};
uint32_t in[MLX5_ST_SZ_DW(modify_cong_status_in)] = {};
u32 out[MLX5_ST_SZ_DW(create_cq_out)];
#define MLX5_MAX_DESTROY_INBOX_SIZE_DW MLX5_ST_SZ_DW(delete_fte_in)
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
u32 dinbox[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)];
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {0};
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {0};
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {};
u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
u32 out[MLX5_ST_SZ_DW(create_cq_out)];
u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};