MII_OFFSET_ANY
awg_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
emac_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
cpswp_ifmedia_sts, BMSR_DEFCAPMASK, sc->phy, MII_OFFSET_ANY, 0);
gen_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
MII_OFFSET_ANY, 0);
age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
MII_OFFSET_ANY, 0);
alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY,
ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
MII_OFFSET_ANY, MIIF_DOPAUSE);
bfe_ifmedia_sts, BMSR_DEFCAPMASK, sc->bfe_phyaddr, MII_OFFSET_ANY,
MII_OFFSET_ANY, MIIF_DOPAUSE);
MII_PHY_ANY, MII_OFFSET_ANY, 0);
MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
dc_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
MII_OFFSET_ANY, 0);
MII_OFFSET_ANY, 0);
MII_OFFSET_ANY, 0);
MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy_addr, MII_OFFSET_ANY, MIIF_DOPAUSE);
MII_OFFSET_ANY, 0))) {
et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
phy, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
port + sc->phy_base, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy + sc->smi_offset, MII_OFFSET_ANY, 0);
phy_addr, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
i, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phy + sc->phyoffset, MII_OFFSET_ANY, 0);
ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY,
MII_PHY_ANY, MII_OFFSET_ANY, flags);
MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
MII_OFFSET_ANY, MIIF_DOPAUSE);
GEM_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
MII_OFFSET_ANY, mii_flags);
lge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phyaddr, MII_OFFSET_ANY, MIIF_DOPAUSE);
mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
if (phyloc != MII_PHY_ANY && offloc != MII_OFFSET_ANY) {
if (offloc != MII_OFFSET_ANY && (offloc < 0 || offloc >= MII_NPHY)) {
if (offloc != MII_OFFSET_ANY && offloc != ivars->mii_offset)
msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, MIIF_DOPAUSE);
nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
sge_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
sk_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
MII_PHY_ANY, MII_OFFSET_ANY, 0);
ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY,
BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE);
MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0);
BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY,
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
MII_OFFSET_ANY, 0);
xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,