A37X0_SPI_CONTROL
reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);
A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);
A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, 1 << (A37X0_SPI_CS_SHIFT + cs));
reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);
reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);
A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);