sys/dev/drm/amd/amdgpu/amdgpu.h
1124
uint32_t tmp_ = RREG32(reg); \
sys/dev/drm/amd/amdgpu/amdgpu.h
1158
WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/drm/amd/amdgpu/amdgpu.h
1161
WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
262
while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
336
value = RREG32(mmRLC_CP_SCHEDULERS);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
398
(*dump)[i++][1] = RREG32(addr); \
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
439
data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
447
data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
452
data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
531
act = RREG32(mmCP_HQD_ACTIVE);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
536
if (low == RREG32(mmCP_HQD_PQ_BASE) &&
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
537
high == RREG32(mmCP_HQD_PQ_BASE_HI))
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
554
sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
604
temp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
633
temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
652
temp = RREG32(mmCP_HQD_ACTIVE);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
679
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
684
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
694
RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
697
m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
708
reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
718
reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
861
tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
865
RREG32(mmVM_INVALIDATE_RESPONSE);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
883
RREG32(mmVM_INVALIDATE_RESPONSE);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
315
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
332
while (!(RREG32(SOC15_REG_OFFSET(
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
425
value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS));
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
508
(*dump)[i++][1] = RREG32(addr); \
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
552
data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
559
data = RREG32(sdmax_gfx_context_cntl);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
643
act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
648
if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
649
high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
667
sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
710
temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
738
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
743
temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
753
RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) |
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
756
m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
758
RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
769
reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
780
reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
830
while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ACK)) &
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
834
while (!(RREG32(SOC15_REG_OFFSET(MMHUB, 0,
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1691
bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1710
bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1711
bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1729
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1741
u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7);
sys/dev/drm/amd/amdgpu/amdgpu_atombios.c
1920
r = RREG32(reg);
sys/dev/drm/amd/amdgpu/amdgpu_cgs.c
46
return RREG32(offset);
sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c
165
value = RREG32(*pos >> 2);
sys/dev/drm/amd/amdgpu/amdgpu_device.c
481
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
108
val = RREG32(rec->y_clk_reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
123
val = RREG32(rec->y_data_reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
137
val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
150
val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
50
temp = RREG32(rec->mask_clk_reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
56
temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
59
temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
63
temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
66
temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
70
temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
72
temp = RREG32(rec->mask_clk_reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
74
temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
76
temp = RREG32(rec->mask_data_reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
89
temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
91
temp = RREG32(rec->mask_clk_reg);
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
93
temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
sys/dev/drm/amd/amdgpu/amdgpu_i2c.c
95
temp = RREG32(rec->mask_data_reg);
sys/dev/drm/amd/amdgpu/amdgpu_psp.c
104
val = RREG32(reg_index);
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
448
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
805
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
sys/dev/drm/amd/amdgpu/amdgpu_vcn.c
888
tmp = RREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9));
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1834
bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1879
bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1927
bios_0_scratch = RREG32(mmBIOS_SCRATCH_0);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1928
bios_3_scratch = RREG32(mmBIOS_SCRATCH_3);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
1929
bios_6_scratch = RREG32(mmBIOS_SCRATCH_6);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
44
bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
sys/dev/drm/amd/amdgpu/atombios_encoders.c
58
bios_2_scratch = RREG32(mmBIOS_SCRATCH_2);
sys/dev/drm/amd/amdgpu/ci_dpm.c
1825
*parameter = RREG32(mmSMC_MSG_ARG_0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
195
return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2018
pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2019
pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2020
pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2021
pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2022
pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2023
pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2024
pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2025
pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2026
pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2077
if (RREG32(mmSMC_RESP_0) == 1)
sys/dev/drm/amd/amdgpu/ci_dpm.c
213
mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
sys/dev/drm/amd/amdgpu/ci_dpm.c
214
mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
sys/dev/drm/amd/amdgpu/ci_dpm.c
215
burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK) >>
sys/dev/drm/amd/amdgpu/ci_dpm.c
219
mc_arb_dram_timing = RREG32(mmMC_ARB_DRAM_TIMING_1);
sys/dev/drm/amd/amdgpu/ci_dpm.c
220
mc_arb_dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2_1);
sys/dev/drm/amd/amdgpu/ci_dpm.c
221
burst_time = (RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE1_MASK) >>
sys/dev/drm/amd/amdgpu/ci_dpm.c
245
mc_cg_config = RREG32(mmMC_CG_CONFIG) | 0x0000000F;
sys/dev/drm/amd/amdgpu/ci_dpm.c
2640
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2669
dram_timing = RREG32(mmMC_ARB_DRAM_TIMING);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2670
dram_timing2 = RREG32(mmMC_ARB_DRAM_TIMING2);
sys/dev/drm/amd/amdgpu/ci_dpm.c
2671
burst_time = RREG32(mmMC_ARB_BURST_TIME) & MC_ARB_BURST_TIME__STATE0_MASK;
sys/dev/drm/amd/amdgpu/ci_dpm.c
3074
(RREG32(mmDPG_PIPE_STUTTER_CONTROL) & DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK) &&
sys/dev/drm/amd/amdgpu/ci_dpm.c
3095
((RREG32(mmMC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/drm/amd/amdgpu/ci_dpm.c
3096
dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/amd/amdgpu/ci_dpm.c
3098
dll_state_on = ((RREG32(mmMC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/drm/amd/amdgpu/ci_dpm.c
3104
dll_state_on = ((RREG32(mmMC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/amd/amdgpu/ci_dpm.c
4501
temp_reg = RREG32(mmMC_PMG_CMD_EMRS);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4512
temp_reg = RREG32(mmMC_PMG_CMD_MRS);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4536
temp_reg = RREG32(mmMC_PMG_CMD_MRS1);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4690
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4764
tmp = RREG32(mmMC_SEQ_IO_DEBUG_DATA);
sys/dev/drm/amd/amdgpu/ci_dpm.c
4785
WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4786
WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4787
WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4788
WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4789
WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4790
WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4791
WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4792
WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4793
WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4794
WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4795
WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4796
WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4797
WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4798
WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4799
WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4800
WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4801
WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4802
WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4803
WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));
sys/dev/drm/amd/amdgpu/ci_dpm.c
4804
WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));
sys/dev/drm/amd/amdgpu/ci_dpm.c
6553
clock = RREG32(mmSMC_MSG_ARG_0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
6569
clock = RREG32(mmSMC_MSG_ARG_0);
sys/dev/drm/amd/amdgpu/ci_dpm.c
713
data = RREG32(config_regs->offset);
sys/dev/drm/amd/amdgpu/ci_smc.c
180
tmp = RREG32(mmSMC_RESP_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
185
tmp = RREG32(mmSMC_RESP_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
260
*value = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/ci_smc.c
91
original_data = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/cik.c
1050
val = RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/cik.c
107
r = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/cik.c
1117
return RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/cik.c
1150
save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);
sys/dev/drm/amd/amdgpu/cik.c
1151
save->gmcon_misc = RREG32(mmGMCON_MISC);
sys/dev/drm/amd/amdgpu/cik.c
1152
save->gmcon_misc3 = RREG32(mmGMCON_MISC3);
sys/dev/drm/amd/amdgpu/cik.c
1254
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
sys/dev/drm/amd/amdgpu/cik.c
129
r = RREG32(mmUVD_CTX_DATA);
sys/dev/drm/amd/amdgpu/cik.c
1295
return RREG32(mmCONFIG_MEMSIZE);
sys/dev/drm/amd/amdgpu/cik.c
151
r = RREG32(mmDIDT_IND_DATA);
sys/dev/drm/amd/amdgpu/cik.c
1711
return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
sys/dev/drm/amd/amdgpu/cik.c
1725
RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
sys/dev/drm/amd/amdgpu/cik.c
1736
RREG32(mmHDP_DEBUG0);
sys/dev/drm/amd/amdgpu/cik.c
82
(void)RREG32(mmPCIE_INDEX);
sys/dev/drm/amd/amdgpu/cik.c
83
r = RREG32(mmPCIE_DATA);
sys/dev/drm/amd/amdgpu/cik.c
882
tmp = RREG32(mmCONFIG_CNTL);
sys/dev/drm/amd/amdgpu/cik.c
899
bus_cntl = RREG32(mmBUS_CNTL);
sys/dev/drm/amd/amdgpu/cik.c
901
d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/drm/amd/amdgpu/cik.c
902
d2vga_control = RREG32(mmD2VGA_CONTROL);
sys/dev/drm/amd/amdgpu/cik.c
903
vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/cik.c
94
(void)RREG32(mmPCIE_INDEX);
sys/dev/drm/amd/amdgpu/cik.c
96
(void)RREG32(mmPCIE_DATA);
sys/dev/drm/amd/amdgpu/cik.c
960
dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/cik_ih.c
115
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/drm/amd/amdgpu/cik_ih.c
201
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cik_ih.c
379
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cik_ih.c
395
tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
sys/dev/drm/amd/amdgpu/cik_ih.c
408
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cik_ih.c
414
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_ih.c
418
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_ih.c
424
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_ih.c
60
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/cik_ih.c
61
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cik_ih.c
79
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cik_ih.c
80
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1059
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1075
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/cik_sdma.c
1089
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1093
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1100
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1107
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1111
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1117
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1137
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1142
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1153
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
1158
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
181
return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
sys/dev/drm/amd/amdgpu/cik_sdma.c
314
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/cik_sdma.c
373
f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/cik_sdma.c
411
me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/cik_sdma.c
906
orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
911
orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
924
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
929
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
934
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cik_sdma.c
939
orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/cz_ih.c
115
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
147
ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
203
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
358
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cz_ih.c
374
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cz_ih.c
386
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/cz_ih.c
393
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cz_ih.c
397
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cz_ih.c
403
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/cz_ih.c
60
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
61
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
79
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/cz_ih.c
80
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1112
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1115
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1122
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1207
tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1467
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1470
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1474
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1477
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1481
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1484
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1532
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1576
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1582
tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1609
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1615
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1622
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1627
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1634
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1641
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1646
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1659
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1663
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1667
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1699
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1706
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1710
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
179
r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1803
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/drm/amd/amdgpu/dce_v10_0.c
1996
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
201
return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2017
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2077
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2096
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2101
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2105
tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2109
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2138
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2144
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2149
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2154
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2164
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2267
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
239
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
250
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
259
*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
260
*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
282
if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2927
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2931
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2937
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2958
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2964
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2987
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
2993
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3017
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3022
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
306
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3093
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3121
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3167
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3182
tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3197
tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3207
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
3253
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
341
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
347
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
351
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
386
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
407
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
409
crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
417
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
436
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
444
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
478
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/drm/amd/amdgpu/dce_v10_0.c
482
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
615
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
619
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
624
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v10_0.c
657
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1138
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1141
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1148
tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1233
tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1509
tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1512
tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1516
tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1519
tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1523
tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1526
tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1574
tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1618
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1624
tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1651
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1657
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1664
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1669
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1676
tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1683
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1688
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1701
tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1705
tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1709
tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1741
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1748
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1752
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
1845
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/drm/amd/amdgpu/dce_v11_0.c
197
r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2038
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2059
tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2119
tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2138
tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2142
tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2146
tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2174
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2180
tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2184
tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2188
tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
219
return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2197
tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
2346
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
257
tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
268
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
277
*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
278
*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
300
if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3053
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3057
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3063
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3084
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3090
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3113
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3119
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3143
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3148
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3219
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
324
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3247
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3293
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3308
tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3323
tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3333
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
3380
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
359
tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
365
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
369
tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
403
tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
423
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
425
crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
433
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
452
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
460
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
504
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/drm/amd/amdgpu/dce_v11_0.c
508
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
641
tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
645
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
650
tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
sys/dev/drm/amd/amdgpu/dce_v11_0.c
683
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1047
wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1056
tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
127
r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
149
return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1530
val = RREG32(mmHDMI_CONTROL + offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
1732
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
sys/dev/drm/amd/amdgpu/dce_v8_0.c
195
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
204
*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
205
*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2170
cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
227
if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) &
sys/dev/drm/amd/amdgpu/dce_v8_0.c
251
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
279
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2815
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2819
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2825
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2870
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2875
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
290
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2921
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2926
lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2949
dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
2954
dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3018
uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3062
reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3090
if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3139
disp_int = RREG32(interrupt_status_offsets[hpd].reg);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
3143
tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
321
tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
341
if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) {
sys/dev/drm/amd/amdgpu/dce_v8_0.c
342
crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
350
tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
369
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
377
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
418
crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
sys/dev/drm/amd/amdgpu/dce_v8_0.c
422
tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/amd/amdgpu/dce_v8_0.c
559
if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/drm/amd/amdgpu/dce_v8_0.c
592
u32 tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1624
data = RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1625
data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1830
RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1832
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1834
RREG32(mmPA_SC_RASTER_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1836
RREG32(mmPA_SC_RASTER_CONFIG_1);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1966
tmp = RREG32(mmSPI_CONFIG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1974
tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1978
tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
1982
tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2015
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2084
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2348
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2635
return RREG32(mmCP_RB0_WPTR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2643
(void)RREG32(mmCP_RB0_WPTR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2863
tmp = RREG32(mmCP_HPD_EOP_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2877
if (RREG32(mmCP_HQD_ACTIVE) & 1) {
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2880
if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2915
RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2926
mqd->cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2935
mqd->cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2970
RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2989
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2995
mqd->cp_hqd_ib_control = RREG32(mmCP_HQD_IB_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2996
mqd->cp_hqd_ib_base_addr_lo = RREG32(mmCP_HQD_IB_BASE_ADDR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2997
mqd->cp_hqd_ib_base_addr_hi = RREG32(mmCP_HQD_IB_BASE_ADDR_HI);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2998
mqd->cp_hqd_ib_rptr = RREG32(mmCP_HQD_IB_RPTR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
2999
mqd->cp_hqd_persistent_state = RREG32(mmCP_HQD_PERSISTENT_STATE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3000
mqd->cp_hqd_sema_cmd = RREG32(mmCP_HQD_SEMA_CMD);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3001
mqd->cp_hqd_msg_type = RREG32(mmCP_HQD_MSG_TYPE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3002
mqd->cp_hqd_atomic0_preop_lo = RREG32(mmCP_HQD_ATOMIC0_PREOP_LO);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3003
mqd->cp_hqd_atomic0_preop_hi = RREG32(mmCP_HQD_ATOMIC0_PREOP_HI);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3004
mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3005
mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3006
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3007
mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3008
mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3009
mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3010
mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3027
tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3088
tmp = RREG32(mmCP_CPF_DEBUG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3142
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3379
tmp = RREG32(mmRLC_LB_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3397
if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3411
if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3421
tmp = RREG32(mmRLC_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3430
orig = data = RREG32(mmRLC_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3439
if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3460
if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3466
if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3514
u32 tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3552
tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3595
orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3621
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3622
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3623
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3624
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3641
orig = data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3648
orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3668
orig = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3683
orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3688
data = RREG32(mmRLC_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3694
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3700
orig = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3739
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3753
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3766
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3779
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3862
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3867
orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3872
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3877
orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3882
data = RREG32(mmDB_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3904
data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3905
data |= RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3921
tmp = RREG32(mmRLC_MAX_PG_CU);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3932
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3946
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3979
orig = data = RREG32(mmRLC_PG_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3987
data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
3995
data = RREG32(mmRLC_PG_DELAY_2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4000
data = RREG32(mmRLC_AUTO_PG_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4162
clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4163
((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4226
return RREG32(mmSQ_IND_DATA);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4241
*(out++) = RREG32(mmSQ_IND_DATA);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4407
mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4408
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4415
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4419
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4673
if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4687
tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4703
tmp = RREG32(mmGRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4719
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4724
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4743
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4747
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4753
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4757
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4761
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4767
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4782
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4787
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4833
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4838
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4856
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4861
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4881
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
4886
cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v7_0.c
5148
adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1635
tmp = RREG32(mmGB_EDC_MODE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1764
tmp = RREG32(mmCC_GC_EDC_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1771
RREG32(sec_ded_counter_registers[i]);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1923
mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1924
adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1931
tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
1935
tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3554
data = RREG32(mmCC_RB_BACKEND_DISABLE) |
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3555
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3759
RREG32(mmCC_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3761
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3763
RREG32(mmPA_SC_RASTER_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3765
RREG32(mmPA_SC_RASTER_CONFIG_1);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3901
tmp = RREG32(mmSPI_ARB_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3922
if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3944
if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
3953
u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4189
u32 tmp = RREG32(mmCP_ME_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4305
tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4412
tmp = RREG32(mmRLC_CP_SCHEDULERS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4488
if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) {
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4491
if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4528
tmp = RREG32(mmCP_HQD_EOP_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4535
tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4547
tmp = RREG32(mmCP_MQD_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4557
tmp = RREG32(mmCP_HQD_PQ_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4585
tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4602
mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4607
tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4612
tmp = RREG32(mmCP_HQD_IB_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4617
tmp = RREG32(mmCP_HQD_IQ_TIMER);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4621
tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4626
mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4627
mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4628
mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4629
mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4630
mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4631
mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4632
mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4633
mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4634
mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4635
mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4636
mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4637
mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4638
mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4639
mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4640
mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4915
if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4916
|| RREG32(mmGRBM_STATUS2) != 0x8)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
4926
if (RREG32(mmGRBM_STATUS2) != 0x8)
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5008
tmp = RREG32(mmGRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5025
tmp = RREG32(mmGRBM_STATUS2);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5044
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5119
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5127
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5131
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5137
tmp = RREG32(mmGRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5141
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5145
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5151
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5155
tmp = RREG32(mmGMCON_DEBUG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5221
clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5222
((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5273
return RREG32(mmSQ_IND_DATA);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5288
*(out++) = RREG32(mmSQ_IND_DATA);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5421
RREG32(mmDB_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5517
data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5522
data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5531
data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5540
data = RREG32(mmRLC_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5545
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5560
data = RREG32(mmRLC_SERDES_WR_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5603
data = RREG32(mmRLC_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5614
if ((RREG32(mmRLC_GPM_STAT) &
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5624
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5637
data = RREG32(mmRLC_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5651
if (!REG_GET_FIELD(RREG32(mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5681
temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5703
temp = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5722
temp = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5731
data = RREG32(mmRLC_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5738
data = RREG32(mmCP_MEM_SLP_CNTL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5745
temp = data = RREG32(mmCGTS_SM_CTRL_REG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5771
temp = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5776
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5800
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5821
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5828
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5829
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5830
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
5831
RREG32(mmCB_CGTT_SCLK_CTRL);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6074
return RREG32(mmCP_RB0_WPTR);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6087
(void)RREG32(mmCP_RB0_WPTR);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6273
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6565
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6570
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
6811
sq_edc_source = REG_GET_FIELD(RREG32(mmSQ_EDC_INFO), SQ_EDC_INFO, SOURCE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
7055
adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
7098
data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
7099
RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
sys/dev/drm/amd/amdgpu/gfx_v8_0.c
860
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2152
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2236
default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2264
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2277
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2282
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2287
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2304
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2318
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2332
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2345
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2358
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2367
data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2375
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
2388
default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
417
tmp = RREG32(scratch);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4213
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4576
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/drm/amd/amdgpu/gfx_v9_0.c
4582
mec_int_cntl = RREG32(mec_int_cntl_reg);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1074
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
111
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1168
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1185
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1202
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1222
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1226
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1232
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1260
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1264
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1270
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1274
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1291
addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1292
status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
1293
mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
200
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
223
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
229
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
242
u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
277
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
282
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
302
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
306
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
329
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
335
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
369
adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
370
adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
382
adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
519
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
550
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
620
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
628
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
642
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
654
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
684
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
696
tmp = RREG32(mmCHUB_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
741
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
747
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
827
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
844
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
882
orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
898
orig = data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
93
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
963
u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
969
u32 viewport = RREG32(mmVIEWPORT_SIZE);
sys/dev/drm/amd/amdgpu/gmc_v7_0.c
989
u32 tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1081
u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1087
u32 viewport = RREG32(mmVIEWPORT_SIZE);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1113
tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1115
tmp = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1200
u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1302
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1319
tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1337
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1385
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1389
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1395
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1432
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1436
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1442
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1446
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1470
addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1471
status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1472
mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1530
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1534
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1538
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1542
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1546
data = RREG32(mmATC_MISC_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1550
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1554
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1558
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1562
data = RREG32(mmVM_L2_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1566
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1570
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1574
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1578
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1582
data = RREG32(mmATC_MISC_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1586
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1590
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1594
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1598
data = RREG32(mmVM_L2_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1610
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1614
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1618
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1622
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1626
data = RREG32(mmATC_MISC_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1630
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1634
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1638
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1642
data = RREG32(mmVM_L2_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1646
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1650
data = RREG32(mmMC_HUB_MISC_SIP_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1654
data = RREG32(mmMC_HUB_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1658
data = RREG32(mmMC_XPB_CLK_GAT);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1662
data = RREG32(mmATC_MISC_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1666
data = RREG32(mmMC_CITF_MISC_WR_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1670
data = RREG32(mmMC_CITF_MISC_RD_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1674
data = RREG32(mmMC_CITF_MISC_VM_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1678
data = RREG32(mmVM_L2_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
1720
data = RREG32(mmMC_HUB_MISC_HUB_CG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
181
blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
199
tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
325
running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
348
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
354
if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
394
data = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
418
data = RREG32(mmMC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
433
base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
468
tmp = RREG32(mmVGA_HDP_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
473
tmp = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
504
tmp = RREG32(mmHDP_MISC_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
508
tmp = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
531
tmp = RREG32(mmMC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
537
tmp = RREG32(mmMC_SHARED_CHMAP);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
571
adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
572
adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
584
adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
744
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
777
tmp = RREG32(mmVM_PRT_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
847
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
855
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
864
tmp = RREG32(mmVM_L2_CNTL2);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
870
tmp = RREG32(mmVM_L2_CNTL3);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
876
tmp = RREG32(mmVM_L2_CNTL4);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
897
tmp = RREG32(mmVM_CONTEXT0_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
927
tmp = RREG32(mmVM_CONTEXT1_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
985
tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v8_0.c
991
tmp = RREG32(mmVM_L2_CNTL);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
224
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
235
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
259
status = RREG32(hub->vm_l2_pro_fault_status);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
635
reg_val = RREG32(reg_addr);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
653
reg_val = RREG32(reg_addr);
sys/dev/drm/amd/amdgpu/gmc_v9_0.c
672
reg_val = RREG32(reg_addr);
sys/dev/drm/amd/amdgpu/iceland_ih.c
115
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
147
ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
203
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
358
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/iceland_ih.c
374
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/iceland_ih.c
386
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/iceland_ih.c
393
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/iceland_ih.c
397
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/iceland_ih.c
403
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/iceland_ih.c
60
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
61
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
79
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/iceland_ih.c
80
u32 ih_cntl = RREG32(mmIH_CNTL);
sys/dev/drm/amd/amdgpu/kv_dpm.c
126
u32 v = RREG32(mmDOUT_SCRATCH3);
sys/dev/drm/amd/amdgpu/kv_dpm.c
433
data = RREG32(config_regs->offset);
sys/dev/drm/amd/amdgpu/kv_smc.c
102
*value = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/kv_smc.c
143
original_data = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/kv_smc.c
197
original_data = RREG32(mmSMC_IND_DATA_0);
sys/dev/drm/amd/amdgpu/kv_smc.c
41
if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0)
sys/dev/drm/amd/amdgpu/kv_smc.c
45
tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
sys/dev/drm/amd/amdgpu/nbio_v6_1.c
79
u32 doorbell_range = RREG32(reg);
sys/dev/drm/amd/amdgpu/nbio_v7_0.c
77
u32 doorbell_range = RREG32(reg);
sys/dev/drm/amd/amdgpu/nbio_v7_4.c
75
u32 doorbell_range = RREG32(reg);
sys/dev/drm/amd/amdgpu/psp_v10_0.c
436
fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
sys/dev/drm/amd/amdgpu/psp_v11_0.c
501
fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
sys/dev/drm/amd/amdgpu/psp_v3_1.c
556
fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1003
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1009
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1029
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1034
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1045
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
1050
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
207
u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
345
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
348
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
387
f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
433
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
466
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
951
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
967
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
981
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
985
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
992
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v2_4.c
999
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1237
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1253
tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1267
u32 tmp = RREG32(mmSRBM_STATUS2);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1334
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1338
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1344
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1364
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1369
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1380
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1385
sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1457
temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1471
temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1496
temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1504
temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1551
data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
1556
data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
369
wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
519
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
522
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
580
f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
622
f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
671
rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
698
doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
716
wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
734
ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1417
u32 tmp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1433
sdma0 = RREG32(sdma_v4_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1434
sdma1 = RREG32(sdma_v4_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1461
sdma_cntl = RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1529
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1542
def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1556
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1570
def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1594
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1601
def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1608
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1615
def = data = RREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1673
data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
1678
data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
373
lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)) >> 2;
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
374
highbit = RREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
572
rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
575
ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
634
f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
669
f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
703
rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
739
doorbell = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
740
doorbell_offset = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
761
temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
767
temp = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
778
wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
789
ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
825
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
832
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
844
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
850
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
856
def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL));
sys/dev/drm/amd/amdgpu/si_dpm.c
2199
cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
2767
reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
2852
data = RREG32(config_regs->offset);
sys/dev/drm/amd/amdgpu/si_dpm.c
3089
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/amd/amdgpu/si_dpm.c
3090
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/amd/amdgpu/si_dpm.c
3091
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
3094
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
sys/dev/drm/amd/amdgpu/si_dpm.c
3095
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
sys/dev/drm/amd/amdgpu/si_dpm.c
3096
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
3099
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
sys/dev/drm/amd/amdgpu/si_dpm.c
3100
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
sys/dev/drm/amd/amdgpu/si_dpm.c
3101
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
3104
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
sys/dev/drm/amd/amdgpu/si_dpm.c
3105
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
sys/dev/drm/amd/amdgpu/si_dpm.c
3106
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
3137
mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
sys/dev/drm/amd/amdgpu/si_dpm.c
3394
return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
sys/dev/drm/amd/amdgpu/si_dpm.c
3668
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/amd/amdgpu/si_dpm.c
3674
width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
sys/dev/drm/amd/amdgpu/si_dpm.c
3676
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/amd/amdgpu/si_dpm.c
4030
si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4031
si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/amd/amdgpu/si_dpm.c
4032
si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/drm/amd/amdgpu/si_dpm.c
4033
si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
sys/dev/drm/amd/amdgpu/si_dpm.c
4034
si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/amd/amdgpu/si_dpm.c
4035
si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/amd/amdgpu/si_dpm.c
4036
si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4037
si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4038
si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4039
si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4040
si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4041
si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
sys/dev/drm/amd/amdgpu/si_dpm.c
4042
si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
sys/dev/drm/amd/amdgpu/si_dpm.c
4043
si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/drm/amd/amdgpu/si_dpm.c
4044
si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/drm/amd/amdgpu/si_dpm.c
4080
if (RREG32(SMC_RESP_0) == 1)
sys/dev/drm/amd/amdgpu/si_dpm.c
4151
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/amd/amdgpu/si_dpm.c
4164
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/drm/amd/amdgpu/si_dpm.c
4265
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/amd/amdgpu/si_dpm.c
4743
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
4750
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
sys/dev/drm/amd/amdgpu/si_dpm.c
4771
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/amd/amdgpu/si_dpm.c
4772
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/amd/amdgpu/si_dpm.c
4773
burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
5465
(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
sys/dev/drm/amd/amdgpu/si_dpm.c
5484
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/drm/amd/amdgpu/si_dpm.c
5485
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/amd/amdgpu/si_dpm.c
5487
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/drm/amd/amdgpu/si_dpm.c
5495
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/amd/amdgpu/si_dpm.c
5826
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/drm/amd/amdgpu/si_dpm.c
5837
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/drm/amd/amdgpu/si_dpm.c
5861
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/drm/amd/amdgpu/si_dpm.c
5998
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/drm/amd/amdgpu/si_dpm.c
5999
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/drm/amd/amdgpu/si_dpm.c
6000
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/drm/amd/amdgpu/si_dpm.c
6001
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/drm/amd/amdgpu/si_dpm.c
6002
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/drm/amd/amdgpu/si_dpm.c
6003
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/drm/amd/amdgpu/si_dpm.c
6004
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/drm/amd/amdgpu/si_dpm.c
6005
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/drm/amd/amdgpu/si_dpm.c
6006
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/drm/amd/amdgpu/si_dpm.c
6007
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/drm/amd/amdgpu/si_dpm.c
6008
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/drm/amd/amdgpu/si_dpm.c
6009
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/drm/amd/amdgpu/si_dpm.c
6010
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/drm/amd/amdgpu/si_dpm.c
6011
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/drm/amd/amdgpu/si_dpm.c
6395
u32 thermal_int = RREG32(CG_THERMAL_INT);
sys/dev/drm/amd/amdgpu/si_dpm.c
6446
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6448
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6453
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6457
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6478
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6514
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6570
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6571
duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6604
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6613
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6647
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6664
tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
sys/dev/drm/amd/amdgpu/si_dpm.c
6693
tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6709
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6713
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6733
tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
6738
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/drm/amd/amdgpu/si_dpm.c
7488
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/amd/amdgpu/si_dpm.c
7854
temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
sys/dev/drm/amd/amdgpu/si_dpm.c
7989
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/amd/amdgpu/soc15.c
102
(void)RREG32(address);
sys/dev/drm/amd/amdgpu/soc15.c
1032
data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
sys/dev/drm/amd/amdgpu/soc15.c
1037
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
sys/dev/drm/amd/amdgpu/soc15.c
104
(void)RREG32(data);
sys/dev/drm/amd/amdgpu/soc15.c
1042
data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
sys/dev/drm/amd/amdgpu/soc15.c
1047
data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
sys/dev/drm/amd/amdgpu/soc15.c
118
r = RREG32(data);
sys/dev/drm/amd/amdgpu/soc15.c
146
r = RREG32(data);
sys/dev/drm/amd/amdgpu/soc15.c
263
dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
sys/dev/drm/amd/amdgpu/soc15.c
308
val = RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/soc15.c
327
return RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/soc15.c
379
tmp = RREG32(reg);
sys/dev/drm/amd/amdgpu/soc15.c
87
(void)RREG32(address);
sys/dev/drm/amd/amdgpu/soc15.c
88
r = RREG32(data);
sys/dev/drm/amd/amdgpu/soc15.c
884
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL));
sys/dev/drm/amd/amdgpu/soc15.c
900
def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS));
sys/dev/drm/amd/amdgpu/soc15.c
916
def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
sys/dev/drm/amd/amdgpu/soc15.c
945
def = data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL));
sys/dev/drm/amd/amdgpu/soc15.c
961
def = data = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0));
sys/dev/drm/amd/amdgpu/soc15_common.h
32
(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
sys/dev/drm/amd/amdgpu/soc15_common.h
36
RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
sys/dev/drm/amd/amdgpu/soc15_common.h
39
RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
sys/dev/drm/amd/amdgpu/soc15_common.h
53
uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
sys/dev/drm/amd/amdgpu/soc15_common.h
62
tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
sys/dev/drm/amd/amdgpu/tonga_ih.c
111
interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
sys/dev/drm/amd/amdgpu/tonga_ih.c
150
ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
sys/dev/drm/amd/amdgpu/tonga_ih.c
214
tmp = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/tonga_ih.c
381
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/tonga_ih.c
397
tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/tonga_ih.c
409
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/tonga_ih.c
456
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/tonga_ih.c
460
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/tonga_ih.c
466
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/tonga_ih.c
60
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/tonga_ih.c
77
u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
218
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
293
tmp = RREG32(mmUVD_MPC_CNTL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
322
status = RREG32(mmUVD_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
363
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
393
status = RREG32(mmUVD_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
404
status = RREG32(mmUVD_LMI_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
418
status = RREG32(mmUVD_LMI_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
496
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
595
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
604
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
618
tmp = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
62
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
642
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
651
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
sys/dev/drm/amd/amdgpu/uvd_v4_2.c
76
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
215
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
366
status = RREG32(mmUVD_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
420
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
512
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
565
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
574
if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
59
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
615
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
616
data3 = RREG32(mmUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
661
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
662
data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
709
data = RREG32(mmUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
710
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
73
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
755
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
764
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v5_0.c
832
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
111
return RREG32(mmUVD_RBC_RB_WPTR);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1125
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1145
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1149
(RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK))
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1184
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1188
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1194
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
126
return RREG32(mmUVD_RB_WPTR);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1260
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1261
data3 = RREG32(mmUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
128
return RREG32(mmUVD_RB_WPTR2);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1315
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1316
data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1364
data = RREG32(mmUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1365
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1412
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1421
orig = data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
1494
data = RREG32(mmUVD_CGC_CTRL);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
548
if (RREG32(mmUVD_STATUS) != 0)
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
627
data = RREG32(mmUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
628
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
789
status = RREG32(mmUVD_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
81
return RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
843
ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
96
return RREG32(mmUVD_RB_RPTR);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
98
return RREG32(mmUVD_RB_RPTR2);
sys/dev/drm/amd/amdgpu/uvd_v6_0.c
981
tmp = RREG32(mmUVD_CONTEXT_ID);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1444
return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1464
u32 tmp = RREG32(mmSRBM_STATUS);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1505
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1509
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/uvd_v7_0.c
1515
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
105
uint32_t status = RREG32(mmVCE_LMI_STATUS);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
122
uint32_t status = RREG32(mmVCE_STATUS);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
151
tmp = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
157
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
162
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
208
return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
294
status = RREG32(mmVCE_LMI_STATUS);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
315
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
319
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
323
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
329
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
334
tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
339
tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
352
tmp = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
365
orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
371
orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
60
return RREG32(mmVCE_RB_RPTR);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
62
return RREG32(mmVCE_RB_RPTR2);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
77
return RREG32(mmVCE_RB_WPTR);
sys/dev/drm/amd/amdgpu/vce_v2_0.c
79
return RREG32(mmVCE_RB_WPTR2);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
123
v = RREG32(mmVCE_RB_WPTR);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
125
v = RREG32(mmVCE_RB_WPTR2);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
127
v = RREG32(mmVCE_RB_WPTR3);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
183
data = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
188
data = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
193
data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
198
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
202
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
209
data = RREG32(mmVCE_CLOCK_GATING_B);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
214
data = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
218
data = RREG32(mmVCE_UENC_CLOCK_GATING_2);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
222
data = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
226
data = RREG32(mmVCE_UENC_DMA_DCLK_CTRL);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
242
uint32_t status = RREG32(mmVCE_STATUS);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
589
return !(RREG32(mmSRBM_STATUS2) & mask);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
630
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/vce_v3_0.c
635
if (RREG32(mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/vce_v3_0.c
663
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
667
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
673
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
764
uint32_t data = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
770
data = RREG32(mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
832
data = RREG32(mmVCE_CLOCK_GATING_A);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
91
v = RREG32(mmVCE_RB_RPTR);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
93
v = RREG32(mmVCE_RB_RPTR2);
sys/dev/drm/amd/amdgpu/vce_v3_0.c
95
v = RREG32(mmVCE_RB_RPTR3);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
131
RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
167
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
186
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
190
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
66
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
674
return !(RREG32(mmSRBM_STATUS2) & mask);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
68
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
70
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
715
if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/vce_v4_0.c
720
if (RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS) & AMDGPU_VCE_STATUS_BUSY_MASK) {
sys/dev/drm/amd/amdgpu/vce_v4_0.c
748
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
752
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
758
tmp = RREG32(mmSRBM_SOFT_RESET);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
796
tmp = data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
820
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
825
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
830
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
835
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
839
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
846
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
851
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
855
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
859
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
863
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
88
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
90
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2));
sys/dev/drm/amd/amdgpu/vce_v4_0.c
910
uint32_t data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
916
data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING);
sys/dev/drm/amd/amdgpu/vce_v4_0.c
92
return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3));
sys/dev/drm/amd/amdgpu/vi.c
103
(void)RREG32(mmPCIE_INDEX);
sys/dev/drm/amd/amdgpu/vi.c
105
(void)RREG32(mmPCIE_DATA);
sys/dev/drm/amd/amdgpu/vi.c
1297
temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/vi.c
1313
temp = data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/drm/amd/amdgpu/vi.c
1329
temp = data = RREG32(0x157a);
sys/dev/drm/amd/amdgpu/vi.c
142
r = RREG32(mmMP0PUB_IND_DATA);
sys/dev/drm/amd/amdgpu/vi.c
1545
data = RREG32(mmHDP_MEM_POWER_LS);
sys/dev/drm/amd/amdgpu/vi.c
1550
data = RREG32(mmHDP_HOST_PATH_CNTL);
sys/dev/drm/amd/amdgpu/vi.c
164
r = RREG32(mmUVD_CTX_DATA);
sys/dev/drm/amd/amdgpu/vi.c
186
r = RREG32(mmDIDT_IND_DATA);
sys/dev/drm/amd/amdgpu/vi.c
208
r = RREG32(mmGC_CAC_IND_DATA);
sys/dev/drm/amd/amdgpu/vi.c
383
bus_cntl = RREG32(mmBUS_CNTL);
sys/dev/drm/amd/amdgpu/vi.c
385
d1vga_control = RREG32(mmD1VGA_CONTROL);
sys/dev/drm/amd/amdgpu/vi.c
386
d2vga_control = RREG32(mmD2VGA_CONTROL);
sys/dev/drm/amd/amdgpu/vi.c
387
vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
sys/dev/drm/amd/amdgpu/vi.c
444
dw_ptr[i] = RREG32(mmSMC_IND_DATA_11);
sys/dev/drm/amd/amdgpu/vi.c
456
reg = RREG32(mmBIF_IOV_FUNC_IDENTIFIER);
sys/dev/drm/amd/amdgpu/vi.c
574
val = RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/vi.c
641
return RREG32(reg_offset);
sys/dev/drm/amd/amdgpu/vi.c
680
if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
sys/dev/drm/amd/amdgpu/vi.c
715
return RREG32(mmCONFIG_MEMSIZE);
sys/dev/drm/amd/amdgpu/vi.c
881
tmp = RREG32(mmBIF_DOORBELL_APER_EN);
sys/dev/drm/amd/amdgpu/vi.c
900
return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
sys/dev/drm/amd/amdgpu/vi.c
908
RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
sys/dev/drm/amd/amdgpu/vi.c
91
(void)RREG32(mmPCIE_INDEX);
sys/dev/drm/amd/amdgpu/vi.c
919
RREG32(mmHDP_DEBUG0);
sys/dev/drm/amd/amdgpu/vi.c
92
r = RREG32(mmPCIE_DATA);
sys/dev/drm/radeon/atombios_crtc.c
1686
disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
sys/dev/drm/radeon/atombios_crtc.c
1691
disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
sys/dev/drm/radeon/atombios_crtc.c
1694
WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
sys/dev/drm/radeon/atombios_crtc.c
1695
WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
sys/dev/drm/radeon/atombios_crtc.c
235
vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
sys/dev/drm/radeon/atombios_crtc.c
400
ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
sys/dev/drm/radeon/atombios_crtc.c
405
ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
sys/dev/drm/radeon/atombios_crtc.c
416
ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
sys/dev/drm/radeon/atombios_crtc.c
421
ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
sys/dev/drm/radeon/atombios_encoders.c
1612
temp = RREG32(reg);
sys/dev/drm/radeon/atombios_encoders.c
1687
u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
2126
uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
sys/dev/drm/radeon/atombios_encoders.c
2455
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
2457
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
2504
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
43
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
45
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
60
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/drm/radeon/atombios_encoders.c
62
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/drm/radeon/btc_dpm.c
1341
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/drm/radeon/btc_dpm.c
1360
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/drm/radeon/btc_dpm.c
1444
tmp = RREG32(sequence[i]);
sys/dev/drm/radeon/btc_dpm.c
1741
if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1)
sys/dev/drm/radeon/btc_dpm.c
1756
arb_registers->mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/btc_dpm.c
1757
arb_registers->mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/btc_dpm.c
1758
arb_registers->mc_arb_rfsh_rate = RREG32(MC_ARB_RFSH_RATE);
sys/dev/drm/radeon/btc_dpm.c
1759
arb_registers->mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
sys/dev/drm/radeon/btc_dpm.c
1923
tmp = RREG32(MC_PMG_CMD_EMRS);
sys/dev/drm/radeon/btc_dpm.c
1936
tmp = RREG32(MC_PMG_CMD_MRS);
sys/dev/drm/radeon/btc_dpm.c
1952
tmp = RREG32(MC_PMG_CMD_MRS1);
sys/dev/drm/radeon/btc_dpm.c
2027
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/drm/radeon/btc_dpm.c
2028
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/drm/radeon/btc_dpm.c
2029
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/drm/radeon/btc_dpm.c
2030
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/drm/radeon/btc_dpm.c
2031
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/drm/radeon/btc_dpm.c
2032
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/drm/radeon/btc_dpm.c
2033
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/drm/radeon/btc_dpm.c
2034
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/drm/radeon/btc_dpm.c
2035
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/drm/radeon/btc_dpm.c
2036
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/drm/radeon/btc_dpm.c
2037
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/drm/radeon/btc_dpm.c
2070
tmp = RREG32(MC_PMG_AUTO_CFG);
sys/dev/drm/radeon/btc_dpm.c
2738
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/btc_dpm.c
2763
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/btc_dpm.c
2786
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/ci_dpm.c
1702
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/ci_dpm.c
1707
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/ci_dpm.c
1727
*parameter = RREG32(SMC_MSG_ARG_0);
sys/dev/drm/radeon/ci_dpm.c
1920
pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1921
pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1922
pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1923
pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1924
pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
sys/dev/drm/radeon/ci_dpm.c
1925
pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
sys/dev/drm/radeon/ci_dpm.c
1926
pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/ci_dpm.c
1927
pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/drm/radeon/ci_dpm.c
1928
pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/drm/radeon/ci_dpm.c
1979
if (RREG32(SMC_RESP_0) == 1)
sys/dev/drm/radeon/ci_dpm.c
2537
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/ci_dpm.c
2567
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/ci_dpm.c
2568
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/ci_dpm.c
2569
burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
sys/dev/drm/radeon/ci_dpm.c
2966
(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
sys/dev/drm/radeon/ci_dpm.c
2987
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/drm/radeon/ci_dpm.c
2988
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/ci_dpm.c
2990
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/ci_dpm.c
2996
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/ci_dpm.c
4382
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/drm/radeon/ci_dpm.c
4393
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/drm/radeon/ci_dpm.c
4419
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/drm/radeon/ci_dpm.c
4575
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/ci_dpm.c
4649
tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
sys/dev/drm/radeon/ci_dpm.c
4670
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/drm/radeon/ci_dpm.c
4671
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/drm/radeon/ci_dpm.c
4672
WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
sys/dev/drm/radeon/ci_dpm.c
4673
WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
sys/dev/drm/radeon/ci_dpm.c
4674
WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
sys/dev/drm/radeon/ci_dpm.c
4675
WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
sys/dev/drm/radeon/ci_dpm.c
4676
WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
sys/dev/drm/radeon/ci_dpm.c
4677
WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
sys/dev/drm/radeon/ci_dpm.c
4678
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/drm/radeon/ci_dpm.c
4679
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/drm/radeon/ci_dpm.c
4680
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/drm/radeon/ci_dpm.c
4681
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/drm/radeon/ci_dpm.c
4682
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/drm/radeon/ci_dpm.c
4683
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/drm/radeon/ci_dpm.c
4684
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/drm/radeon/ci_dpm.c
4685
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/drm/radeon/ci_dpm.c
4686
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/drm/radeon/ci_dpm.c
4687
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/drm/radeon/ci_dpm.c
4688
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/drm/radeon/ci_dpm.c
4689
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/drm/radeon/ci_dpm.c
5130
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/ci_dpm.c
582
data = RREG32(config_regs->offset << 2);
sys/dev/drm/radeon/ci_smc.c
255
*value = RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/ci_smc.c
88
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/cik.c
160
*val = RREG32(reg);
sys/dev/drm/radeon/cik.c
177
r = RREG32(CIK_DIDT_IND_DATA);
sys/dev/drm/radeon/cik.c
1897
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
sys/dev/drm/radeon/cik.c
1915
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/cik.c
1938
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
sys/dev/drm/radeon/cik.c
1943
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
sys/dev/drm/radeon/cik.c
239
(void)RREG32(PCIE_INDEX);
sys/dev/drm/radeon/cik.c
240
r = RREG32(PCIE_DATA);
sys/dev/drm/radeon/cik.c
251
(void)RREG32(PCIE_INDEX);
sys/dev/drm/radeon/cik.c
253
(void)RREG32(PCIE_DATA);
sys/dev/drm/radeon/cik.c
3103
data = RREG32(CC_RB_BACKEND_DISABLE);
sys/dev/drm/radeon/cik.c
3108
data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
sys/dev/drm/radeon/cik.c
3196
u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/cik.c
3290
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/cik.c
3291
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/cik.c
3380
tmp = RREG32(SPI_CONFIG_CNTL);
sys/dev/drm/radeon/cik.c
3388
tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
sys/dev/drm/radeon/cik.c
3392
tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
sys/dev/drm/radeon/cik.c
3396
tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
sys/dev/drm/radeon/cik.c
3422
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/cik.c
3426
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/cik.c
3496
tmp = RREG32(scratch);
sys/dev/drm/radeon/cik.c
3841
tmp = RREG32(scratch);
sys/dev/drm/radeon/cik.c
4147
rptr = RREG32(CP_RB0_RPTR);
sys/dev/drm/radeon/cik.c
4155
return RREG32(CP_RB0_WPTR);
sys/dev/drm/radeon/cik.c
4162
(void)RREG32(CP_RB0_WPTR);
sys/dev/drm/radeon/cik.c
4175
rptr = RREG32(CP_HQD_PQ_RPTR);
sys/dev/drm/radeon/cik.c
4194
wptr = RREG32(CP_HQD_PQ_WPTR);
sys/dev/drm/radeon/cik.c
4217
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/drm/radeon/cik.c
4221
if (RREG32(CP_HQD_ACTIVE) & 1) {
sys/dev/drm/radeon/cik.c
4224
if (!(RREG32(CP_HQD_ACTIVE) & 1))
sys/dev/drm/radeon/cik.c
4551
tmp = RREG32(CP_CPF_DEBUG);
sys/dev/drm/radeon/cik.c
4573
tmp = RREG32(CP_HPD_EOP_CONTROL);
sys/dev/drm/radeon/cik.c
4636
tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
sys/dev/drm/radeon/cik.c
4642
RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/radeon/cik.c
4654
if (RREG32(CP_HQD_ACTIVE) & 1) {
sys/dev/drm/radeon/cik.c
4657
if (!(RREG32(CP_HQD_ACTIVE) & 1))
sys/dev/drm/radeon/cik.c
4672
mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
sys/dev/drm/radeon/cik.c
4684
mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
sys/dev/drm/radeon/cik.c
4728
RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
sys/dev/drm/radeon/cik.c
4746
mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
sys/dev/drm/radeon/cik.c
4822
RREG32(GRBM_STATUS));
sys/dev/drm/radeon/cik.c
4824
RREG32(GRBM_STATUS2));
sys/dev/drm/radeon/cik.c
4826
RREG32(GRBM_STATUS_SE0));
sys/dev/drm/radeon/cik.c
4828
RREG32(GRBM_STATUS_SE1));
sys/dev/drm/radeon/cik.c
4830
RREG32(GRBM_STATUS_SE2));
sys/dev/drm/radeon/cik.c
4832
RREG32(GRBM_STATUS_SE3));
sys/dev/drm/radeon/cik.c
4834
RREG32(SRBM_STATUS));
sys/dev/drm/radeon/cik.c
4836
RREG32(SRBM_STATUS2));
sys/dev/drm/radeon/cik.c
4838
RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
sys/dev/drm/radeon/cik.c
4840
RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
sys/dev/drm/radeon/cik.c
4841
dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
sys/dev/drm/radeon/cik.c
4843
RREG32(CP_STALLED_STAT1));
sys/dev/drm/radeon/cik.c
4845
RREG32(CP_STALLED_STAT2));
sys/dev/drm/radeon/cik.c
4847
RREG32(CP_STALLED_STAT3));
sys/dev/drm/radeon/cik.c
4849
RREG32(CP_CPF_BUSY_STAT));
sys/dev/drm/radeon/cik.c
4851
RREG32(CP_CPF_STALLED_STAT1));
sys/dev/drm/radeon/cik.c
4852
dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
sys/dev/drm/radeon/cik.c
4853
dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
sys/dev/drm/radeon/cik.c
4855
RREG32(CP_CPC_STALLED_STAT1));
sys/dev/drm/radeon/cik.c
4856
dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
sys/dev/drm/radeon/cik.c
4874
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/cik.c
4887
tmp = RREG32(GRBM_STATUS2);
sys/dev/drm/radeon/cik.c
4892
tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4897
tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4902
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/cik.c
4910
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/cik.c
4961
RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
sys/dev/drm/radeon/cik.c
4963
RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
sys/dev/drm/radeon/cik.c
4980
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
4986
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
5035
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5039
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5045
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5049
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5053
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5059
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik.c
5080
save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
sys/dev/drm/radeon/cik.c
5081
save->gmcon_misc = RREG32(GMCON_MISC);
sys/dev/drm/radeon/cik.c
5082
save->gmcon_misc3 = RREG32(GMCON_MISC3);
sys/dev/drm/radeon/cik.c
5183
tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
5187
tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
5215
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/drm/radeon/cik.c
5361
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/cik.c
5367
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/cik.c
5403
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/radeon/cik.c
5404
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/radeon/cik.c
5522
u32 tmp = RREG32(CHUB_CONTROL);
sys/dev/drm/radeon/cik.c
5572
rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
sys/dev/drm/radeon/cik.c
5647
u64 tmp = RREG32(MC_VM_FB_OFFSET);
sys/dev/drm/radeon/cik.c
5787
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/drm/radeon/cik.c
5800
tmp = RREG32(RLC_LB_CNTL);
sys/dev/drm/radeon/cik.c
5817
if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
sys/dev/drm/radeon/cik.c
5827
if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
sys/dev/drm/radeon/cik.c
5837
tmp = RREG32(RLC_CNTL);
sys/dev/drm/radeon/cik.c
5846
orig = data = RREG32(RLC_CNTL);
sys/dev/drm/radeon/cik.c
5855
if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
sys/dev/drm/radeon/cik.c
5875
if ((RREG32(RLC_GPM_STAT) & mask) == mask)
sys/dev/drm/radeon/cik.c
5881
if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
sys/dev/drm/radeon/cik.c
5946
tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
sys/dev/drm/radeon/cik.c
6021
orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
sys/dev/drm/radeon/cik.c
6040
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/cik.c
6041
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/cik.c
6042
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/cik.c
6043
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/cik.c
6060
orig = data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/drm/radeon/cik.c
6067
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/radeon/cik.c
6084
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/drm/radeon/cik.c
6099
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/radeon/cik.c
6104
data = RREG32(RLC_MEM_SLP_CNTL);
sys/dev/drm/radeon/cik.c
6110
data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/drm/radeon/cik.c
6116
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/drm/radeon/cik.c
6153
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/drm/radeon/cik.c
6170
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/drm/radeon/cik.c
6189
orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
6194
orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
6207
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
6212
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
6217
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
6222
orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/cik.c
6239
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/cik.c
6248
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/cik.c
6278
orig = data = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/cik.c
6294
orig = data = RREG32(HDP_MEM_POWER_LS);
sys/dev/drm/radeon/cik.c
6384
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6398
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6411
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6424
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6527
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6532
orig = data = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/cik.c
6537
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6542
orig = data = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/cik.c
6547
data = RREG32(DB_RENDER_CONTROL);
sys/dev/drm/radeon/cik.c
6557
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/cik.c
6558
tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/cik.c
6601
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/drm/radeon/cik.c
6612
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6626
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6659
orig = data = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/cik.c
6667
data = RREG32(CP_RB_WPTR_POLL_CNTL);
sys/dev/drm/radeon/cik.c
6675
data = RREG32(RLC_PG_DELAY_2);
sys/dev/drm/radeon/cik.c
6680
data = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/cik.c
6841
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/drm/radeon/cik.c
6842
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/cik.c
6860
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/cik.c
6861
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/drm/radeon/cik.c
6886
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/drm/radeon/cik.c
6890
tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/cik.c
6892
tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/cik.c
6936
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6938
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6940
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6942
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6944
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6946
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/cik.c
6986
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/drm/radeon/cik.c
7064
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
sys/dev/drm/radeon/cik.c
7068
hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/drm/radeon/cik.c
7069
hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/drm/radeon/cik.c
7070
hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/drm/radeon/cik.c
7071
hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/drm/radeon/cik.c
7072
hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/drm/radeon/cik.c
7073
hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
sys/dev/drm/radeon/cik.c
7075
dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/cik.c
7076
dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/cik.c
7078
cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7079
cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7080
cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7081
cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7082
cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7083
cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7084
cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7085
cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
sys/dev/drm/radeon/cik.c
7298
RREG32(SRBM_STATUS);
sys/dev/drm/radeon/cik.c
7316
rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
sys/dev/drm/radeon/cik.c
7317
rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
sys/dev/drm/radeon/cik.c
7318
rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
sys/dev/drm/radeon/cik.c
7319
rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
sys/dev/drm/radeon/cik.c
7320
rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
sys/dev/drm/radeon/cik.c
7321
rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
sys/dev/drm/radeon/cik.c
7322
rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
sys/dev/drm/radeon/cik.c
7324
rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/drm/radeon/cik.c
7326
rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/drm/radeon/cik.c
7329
rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/drm/radeon/cik.c
7331
rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/drm/radeon/cik.c
7335
rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/drm/radeon/cik.c
7337
rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
sys/dev/drm/radeon/cik.c
7391
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7396
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7401
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7406
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7411
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7416
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7421
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7426
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7431
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7436
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7441
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7446
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/cik.c
7515
wptr = RREG32(IH_RB_WPTR);
sys/dev/drm/radeon/cik.c
7526
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/cik.c
7914
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
sys/dev/drm/radeon/cik.c
7923
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/drm/radeon/cik.c
7924
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/drm/radeon/cik.c
7925
mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
sys/dev/drm/radeon/cik.c
8874
if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/drm/radeon/cik.c
8907
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/cik.c
9366
wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/cik.c
9375
tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/cik.c
9435
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/drm/radeon/cik.c
9436
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/drm/radeon/cik_sdma.c
120
(void)RREG32(reg);
sys/dev/drm/radeon/cik_sdma.c
262
rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
sys/dev/drm/radeon/cik_sdma.c
276
(void)RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik_sdma.c
279
(void)RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/cik_sdma.c
312
value = RREG32(SDMA0_CNTL + reg_offset);
sys/dev/drm/radeon/cik_sdma.c
344
me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
sys/dev/drm/radeon/cik_sdma.c
74
rptr = RREG32(reg);
sys/dev/drm/radeon/cik_sdma.c
98
return (RREG32(reg) & 0x3fffc) >> 2;
sys/dev/drm/radeon/cypress_dpm.c
1042
RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
sys/dev/drm/radeon/cypress_dpm.c
107
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/cypress_dpm.c
1113
if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
sys/dev/drm/radeon/cypress_dpm.c
1128
if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
sys/dev/drm/radeon/cypress_dpm.c
1157
if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
sys/dev/drm/radeon/cypress_dpm.c
1176
value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
sys/dev/drm/radeon/cypress_dpm.c
1215
if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
sys/dev/drm/radeon/cypress_dpm.c
148
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/cypress_dpm.c
1580
u32 tmp = RREG32(GENERAL_PWRMGT);
sys/dev/drm/radeon/cypress_dpm.c
1734
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/cypress_dpm.c
1751
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/radeon/cypress_dpm.c
1764
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/drm/radeon/cypress_dpm.c
506
mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
sys/dev/drm/radeon/cypress_dpm.c
60
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/drm/radeon/cypress_dpm.c
721
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/drm/radeon/cypress_dpm.c
722
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/cypress_dpm.c
724
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/cypress_dpm.c
932
u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
sys/dev/drm/radeon/dce3_1_afmt.c
162
dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/drm/radeon/dce3_1_afmt.c
169
dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/drm/radeon/dce6_afmt.c
321
unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
sys/dev/drm/radeon/dce6_afmt.c
51
r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
sys/dev/drm/radeon/evergreen.c
1089
*val = RREG32(reg);
sys/dev/drm/radeon/evergreen.c
1141
if (RREG32(status_reg) & DCLK_STATUS)
sys/dev/drm/radeon/evergreen.c
1154
u32 cg_scratch = RREG32(CG_SCRATCH1);
sys/dev/drm/radeon/evergreen.c
1335
if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
sys/dev/drm/radeon/evergreen.c
1345
pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/radeon/evergreen.c
1346
pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/radeon/evergreen.c
1369
if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
sys/dev/drm/radeon/evergreen.c
1413
RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/evergreen.c
1429
return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/drm/radeon/evergreen.c
1440
toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
sys/dev/drm/radeon/evergreen.c
1442
temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
sys/dev/drm/radeon/evergreen.c
1453
temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
sys/dev/drm/radeon/evergreen.c
1474
u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
sys/dev/drm/radeon/evergreen.c
1664
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/evergreen.c
1689
tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/evergreen.c
1710
return !!(RREG32(DC_HPDx_INT_STATUS_REG(hpd)) & DC_HPDx_SENSE);
sys/dev/drm/radeon/evergreen.c
1855
if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/drm/radeon/evergreen.c
1898
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/evergreen.c
2266
arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
sys/dev/drm/radeon/evergreen.c
2275
tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
sys/dev/drm/radeon/evergreen.c
2345
tmp = RREG32(SRBM_STATUS) & 0x1F00;
sys/dev/drm/radeon/evergreen.c
2366
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/drm/radeon/evergreen.c
2562
dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2576
dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2583
dig_en_be = RREG32(NI_DIG_BE_EN_CNTL +
sys/dev/drm/radeon/evergreen.c
2585
uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 +
sys/dev/drm/radeon/evergreen.c
2618
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/drm/radeon/evergreen.c
2629
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/drm/radeon/evergreen.c
2634
stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL +
sys/dev/drm/radeon/evergreen.c
2640
fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]);
sys/dev/drm/radeon/evergreen.c
2653
save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
sys/dev/drm/radeon/evergreen.c
2654
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
sys/dev/drm/radeon/evergreen.c
2661
crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
sys/dev/drm/radeon/evergreen.c
2665
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2674
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2703
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2716
blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/radeon/evergreen.c
2730
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2735
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2769
tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2774
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2779
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2785
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2794
tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/radeon/evergreen.c
2803
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2809
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
2880
tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
sys/dev/drm/radeon/evergreen.c
3059
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3062
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3382
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/evergreen.c
3386
mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
sys/dev/drm/radeon/evergreen.c
3388
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/evergreen.c
3449
rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
sys/dev/drm/radeon/evergreen.c
3470
simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/drm/radeon/evergreen.c
3521
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/drm/radeon/evergreen.c
3526
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
sys/dev/drm/radeon/evergreen.c
3552
sq_config = RREG32(SQ_CONFIG);
sys/dev/drm/radeon/evergreen.c
3577
sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
sys/dev/drm/radeon/evergreen.c
3679
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/evergreen.c
3683
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/evergreen.c
3702
tmp = RREG32(FUS_MC_ARB_RAMCFG);
sys/dev/drm/radeon/evergreen.c
3704
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/evergreen.c
3712
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/evergreen.c
3737
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/evergreen.c
3738
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/evergreen.c
3741
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/radeon/evergreen.c
3742
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
sys/dev/drm/radeon/evergreen.c
3754
RREG32(GRBM_STATUS));
sys/dev/drm/radeon/evergreen.c
3756
RREG32(GRBM_STATUS_SE0));
sys/dev/drm/radeon/evergreen.c
3758
RREG32(GRBM_STATUS_SE1));
sys/dev/drm/radeon/evergreen.c
3760
RREG32(SRBM_STATUS));
sys/dev/drm/radeon/evergreen.c
3762
RREG32(SRBM_STATUS2));
sys/dev/drm/radeon/evergreen.c
3764
RREG32(CP_STALLED_STAT1));
sys/dev/drm/radeon/evergreen.c
3766
RREG32(CP_STALLED_STAT2));
sys/dev/drm/radeon/evergreen.c
3768
RREG32(CP_BUSY_STAT));
sys/dev/drm/radeon/evergreen.c
3770
RREG32(CP_STAT));
sys/dev/drm/radeon/evergreen.c
3772
RREG32(DMA_STATUS_REG));
sys/dev/drm/radeon/evergreen.c
3775
RREG32(DMA_STATUS_REG + 0x800));
sys/dev/drm/radeon/evergreen.c
3786
if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
sys/dev/drm/radeon/evergreen.c
3787
crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
3795
tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
3814
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/evergreen.c
3830
tmp = RREG32(DMA_STATUS_REG);
sys/dev/drm/radeon/evergreen.c
3835
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/evergreen.c
3840
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/evergreen.c
3864
tmp = RREG32(VM_L2_STATUS);
sys/dev/drm/radeon/evergreen.c
3895
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/evergreen.c
3955
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3959
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3965
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3969
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3973
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
3979
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/evergreen.c
4004
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/evergreen.c
4027
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/drm/radeon/evergreen.c
4380
u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/drm/radeon/evergreen.c
4437
return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
sys/dev/drm/radeon/evergreen.c
4450
tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/evergreen.c
4454
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/evergreen.c
4495
thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) &
sys/dev/drm/radeon/evergreen.c
4498
thermal_int = RREG32(CG_THERMAL_INT) &
sys/dev/drm/radeon/evergreen.c
4501
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/evergreen.c
4531
dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/evergreen.c
4588
RREG32(SRBM_STATUS);
sys/dev/drm/radeon/evergreen.c
4602
disp_int[i] = RREG32(evergreen_disp_int_status[i]);
sys/dev/drm/radeon/evergreen.c
4603
afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
4605
grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
sys/dev/drm/radeon/evergreen.c
4665
wptr = RREG32(IH_RB_WPTR);
sys/dev/drm/radeon/evergreen.c
4676
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/evergreen.c
4817
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
sys/dev/drm/radeon/evergreen.c
4826
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/drm/radeon/evergreen.c
4827
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/drm/radeon/evergreen.c
52
r = RREG32(EVERGREEN_CG_IND_DATA);
sys/dev/drm/radeon/evergreen.c
74
r = RREG32(EVERGREEN_PIF_PHY0_DATA);
sys/dev/drm/radeon/evergreen.c
96
r = RREG32(EVERGREEN_PIF_PHY1_DATA);
sys/dev/drm/radeon/evergreen_hdmi.c
266
value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/drm/radeon/evergreen_hdmi.c
294
value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
sys/dev/drm/radeon/evergreen_hdmi.c
312
unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &
sys/dev/drm/radeon/evergreen_hdmi.c
345
val = RREG32(HDMI_CONTROL + offset);
sys/dev/drm/radeon/evergreen_hdmi.c
44
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/drm/radeon/evergreen_hdmi.c
491
val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);
sys/dev/drm/radeon/kv_dpm.c
301
data = RREG32(config_regs->offset << 2);
sys/dev/drm/radeon/kv_smc.c
139
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/kv_smc.c
193
original_data= RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/kv_smc.c
38
if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0)
sys/dev/drm/radeon/kv_smc.c
42
tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;
sys/dev/drm/radeon/kv_smc.c
98
*value = RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/ni.c
1029
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/ni.c
1030
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/ni.c
1107
rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
sys/dev/drm/radeon/ni.c
1127
simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
sys/dev/drm/radeon/ni.c
1176
cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
sys/dev/drm/radeon/ni.c
1184
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/drm/radeon/ni.c
1188
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
sys/dev/drm/radeon/ni.c
1250
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/ni.c
1254
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/ni.c
1373
rdev->vm_manager.saved_table_addr[i] = RREG32(
sys/dev/drm/radeon/ni.c
1493
rptr = RREG32(CP_RB0_RPTR);
sys/dev/drm/radeon/ni.c
1495
rptr = RREG32(CP_RB1_RPTR);
sys/dev/drm/radeon/ni.c
1497
rptr = RREG32(CP_RB2_RPTR);
sys/dev/drm/radeon/ni.c
1509
wptr = RREG32(CP_RB0_WPTR);
sys/dev/drm/radeon/ni.c
1511
wptr = RREG32(CP_RB1_WPTR);
sys/dev/drm/radeon/ni.c
1513
wptr = RREG32(CP_RB2_WPTR);
sys/dev/drm/radeon/ni.c
1523
(void)RREG32(CP_RB0_WPTR);
sys/dev/drm/radeon/ni.c
1526
(void)RREG32(CP_RB1_WPTR);
sys/dev/drm/radeon/ni.c
1529
(void)RREG32(CP_RB2_WPTR);
sys/dev/drm/radeon/ni.c
1681
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1684
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1762
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/ni.c
1779
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1784
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1789
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/ni.c
1797
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/ni.c
1821
tmp = RREG32(VM_L2_STATUS);
sys/dev/drm/radeon/ni.c
1847
RREG32(0x14F8));
sys/dev/drm/radeon/ni.c
1849
RREG32(0x14D8));
sys/dev/drm/radeon/ni.c
1851
RREG32(0x14FC));
sys/dev/drm/radeon/ni.c
1853
RREG32(0x14DC));
sys/dev/drm/radeon/ni.c
1860
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1867
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/ni.c
1930
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1934
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1940
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1944
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1948
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
1954
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/ni.c
2523
u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
sys/dev/drm/radeon/ni.c
2744
if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
sys/dev/drm/radeon/ni.c
2754
if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
sys/dev/drm/radeon/ni.c
47
r = RREG32(TN_SMC_IND_DATA_0);
sys/dev/drm/radeon/ni.c
649
mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
sys/dev/drm/radeon/ni.c
650
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
sys/dev/drm/radeon/ni.c
654
blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
sys/dev/drm/radeon/ni.c
679
if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
sys/dev/drm/radeon/ni.c
883
*val = RREG32(reg);
sys/dev/drm/radeon/ni_dma.c
164
rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/ni_dma.c
169
rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/ni_dma.c
237
dma_cntl = RREG32(DMA_CNTL + reg_offset);
sys/dev/drm/radeon/ni_dma.c
64
rptr = RREG32(reg);
sys/dev/drm/radeon/ni_dma.c
88
return (RREG32(reg) & 0x3fffc) >> 2;
sys/dev/drm/radeon/ni_dpm.c
1086
tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
sys/dev/drm/radeon/ni_dpm.c
1183
ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/ni_dpm.c
1184
ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/ni_dpm.c
1185
ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/drm/radeon/ni_dpm.c
1186
ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
sys/dev/drm/radeon/ni_dpm.c
1187
ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/ni_dpm.c
1188
ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/radeon/ni_dpm.c
1189
ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/drm/radeon/ni_dpm.c
1190
ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);
sys/dev/drm/radeon/ni_dpm.c
1191
ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/drm/radeon/ni_dpm.c
1192
ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);
sys/dev/drm/radeon/ni_dpm.c
1193
ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/ni_dpm.c
1194
ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/drm/radeon/ni_dpm.c
1195
ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/drm/radeon/ni_dpm.c
1196
ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/drm/radeon/ni_dpm.c
1208
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/ni_dpm.c
1367
u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
sys/dev/drm/radeon/ni_dpm.c
1514
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/ni_dpm.c
1515
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/ni_dpm.c
1516
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
sys/dev/drm/radeon/ni_dpm.c
1519
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
sys/dev/drm/radeon/ni_dpm.c
1520
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
sys/dev/drm/radeon/ni_dpm.c
1521
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
sys/dev/drm/radeon/ni_dpm.c
1524
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
sys/dev/drm/radeon/ni_dpm.c
1525
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
sys/dev/drm/radeon/ni_dpm.c
1526
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
sys/dev/drm/radeon/ni_dpm.c
1529
mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
sys/dev/drm/radeon/ni_dpm.c
1530
mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
sys/dev/drm/radeon/ni_dpm.c
1531
burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
sys/dev/drm/radeon/ni_dpm.c
1562
mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
sys/dev/drm/radeon/ni_dpm.c
1626
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/ni_dpm.c
1627
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/ni_dpm.c
2187
mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
sys/dev/drm/radeon/ni_dpm.c
2321
u32 tmp = RREG32(DC_STUTTER_CNTL);
sys/dev/drm/radeon/ni_dpm.c
2348
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/drm/radeon/ni_dpm.c
2349
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/ni_dpm.c
2351
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/ni_dpm.c
2723
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/drm/radeon/ni_dpm.c
2734
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/drm/radeon/ni_dpm.c
2749
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/drm/radeon/ni_dpm.c
2883
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/drm/radeon/ni_dpm.c
2884
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/drm/radeon/ni_dpm.c
2885
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/drm/radeon/ni_dpm.c
2886
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/drm/radeon/ni_dpm.c
2887
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/drm/radeon/ni_dpm.c
2888
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/drm/radeon/ni_dpm.c
2889
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/drm/radeon/ni_dpm.c
2890
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/drm/radeon/ni_dpm.c
2891
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/drm/radeon/ni_dpm.c
2892
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/drm/radeon/ni_dpm.c
2893
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/drm/radeon/ni_dpm.c
2894
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/drm/radeon/ni_dpm.c
2895
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/drm/radeon/ni_dpm.c
3154
reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);
sys/dev/drm/radeon/ni_dpm.c
3354
reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |
sys/dev/drm/radeon/ni_dpm.c
3470
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/drm/radeon/ni_dpm.c
3485
bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
sys/dev/drm/radeon/ni_dpm.c
4309
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/radeon/ni_dpm.c
4329
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/radeon/ni_dpm.c
4347
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/radeon/r100.c
1066
rptr = RREG32(RADEON_CP_RB_RPTR);
sys/dev/drm/radeon/r100.c
1074
return RREG32(RADEON_CP_RB_WPTR);
sys/dev/drm/radeon/r100.c
1081
(void)RREG32(RADEON_CP_RB_WPTR);
sys/dev/drm/radeon/r100.c
119
if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
sys/dev/drm/radeon/r100.c
122
if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
sys/dev/drm/radeon/r100.c
168
if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
sys/dev/drm/radeon/r100.c
194
return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
sys/dev/drm/radeon/r100.c
2485
tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
sys/dev/drm/radeon/r100.c
2503
tmp = RREG32(RADEON_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2519
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/drm/radeon/r100.c
2532
rbbm_status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2545
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/drm/radeon/r100.c
2554
tmp = RREG32(R_000030_BUS_CNTL);
sys/dev/drm/radeon/r100.c
2560
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/r100.c
2572
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2577
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2581
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/r100.c
2594
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/r100.c
2598
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2602
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/r100.c
2606
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r100.c
2668
u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
sys/dev/drm/radeon/r100.c
2669
u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/r100.c
2670
u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
sys/dev/drm/radeon/r100.c
2716
else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
sys/dev/drm/radeon/r100.c
2721
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r100.c
2732
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r100.c
2749
aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
sys/dev/drm/radeon/r100.c
2777
if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
sys/dev/drm/radeon/r100.c
2793
config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
sys/dev/drm/radeon/r100.c
2797
tom = RREG32(RADEON_NB_TOM);
sys/dev/drm/radeon/r100.c
2802
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/drm/radeon/r100.c
2827
temp = RREG32(RADEON_CONFIG_CNTL);
sys/dev/drm/radeon/r100.c
2845
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
sys/dev/drm/radeon/r100.c
2860
(void)RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/drm/radeon/r100.c
2861
(void)RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/drm/radeon/r100.c
2882
save = RREG32(RADEON_CLOCK_CNTL_INDEX);
sys/dev/drm/radeon/r100.c
2885
tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/drm/radeon/r100.c
2898
data = RREG32(RADEON_CLOCK_CNTL_DATA);
sys/dev/drm/radeon/r100.c
2941
seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
sys/dev/drm/radeon/r100.c
2942
seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
sys/dev/drm/radeon/r100.c
2943
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
sys/dev/drm/radeon/r100.c
2946
reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
sys/dev/drm/radeon/r100.c
2948
value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
sys/dev/drm/radeon/r100.c
2964
rdp = RREG32(RADEON_CP_RB_RPTR);
sys/dev/drm/radeon/r100.c
2965
wdp = RREG32(RADEON_CP_RB_WPTR);
sys/dev/drm/radeon/r100.c
2967
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
sys/dev/drm/radeon/r100.c
2991
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
sys/dev/drm/radeon/r100.c
2992
seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
sys/dev/drm/radeon/r100.c
2993
csq_stat = RREG32(RADEON_CP_CSQ_STAT);
sys/dev/drm/radeon/r100.c
2994
csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
sys/dev/drm/radeon/r100.c
3014
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/drm/radeon/r100.c
3020
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/drm/radeon/r100.c
3026
tmp = RREG32(RADEON_CP_CSQ_DATA);
sys/dev/drm/radeon/r100.c
3039
tmp = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/drm/radeon/r100.c
3041
tmp = RREG32(RADEON_MC_FB_LOCATION);
sys/dev/drm/radeon/r100.c
3043
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/r100.c
3045
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/drm/radeon/r100.c
3047
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/drm/radeon/r100.c
3049
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/r100.c
3051
tmp = RREG32(0x01D0);
sys/dev/drm/radeon/r100.c
3053
tmp = RREG32(RADEON_AIC_LO_ADDR);
sys/dev/drm/radeon/r100.c
3055
tmp = RREG32(RADEON_AIC_HI_ADDR);
sys/dev/drm/radeon/r100.c
3057
tmp = RREG32(0x01E4);
sys/dev/drm/radeon/r100.c
3257
uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
sys/dev/drm/radeon/r100.c
3303
temp = RREG32(RADEON_MEM_TIMING_CNTL);
sys/dev/drm/radeon/r100.c
3343
temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/drm/radeon/r100.c
3364
temp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r100.c
3368
temp = RREG32(R300_MC_IND_INDEX);
sys/dev/drm/radeon/r100.c
3372
temp = RREG32(R300_MC_IND_DATA);
sys/dev/drm/radeon/r100.c
3375
temp = RREG32(R300_MC_READ_CNTL_AB);
sys/dev/drm/radeon/r100.c
3379
temp = RREG32(R300_MC_READ_CNTL_AB);
sys/dev/drm/radeon/r100.c
3515
temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
sys/dev/drm/radeon/r100.c
3538
temp = RREG32(RS400_DISP1_REG_CNTL);
sys/dev/drm/radeon/r100.c
354
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/r100.c
3544
temp = RREG32(RS400_DMIF_MEM_CNTL1);
sys/dev/drm/radeon/r100.c
3555
(unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
sys/dev/drm/radeon/r100.c
3571
grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
sys/dev/drm/radeon/r100.c
363
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/r100.c
3630
temp = RREG32(RS400_DISP2_REQ_CNTL1);
sys/dev/drm/radeon/r100.c
3636
temp = RREG32(RS400_DISP2_REQ_CNTL2);
sys/dev/drm/radeon/r100.c
3650
(unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
sys/dev/drm/radeon/r100.c
3684
tmp = RREG32(scratch);
sys/dev/drm/radeon/r100.c
3761
tmp = RREG32(scratch);
sys/dev/drm/radeon/r100.c
3791
save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
sys/dev/drm/radeon/r100.c
3792
save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
sys/dev/drm/radeon/r100.c
3793
save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
sys/dev/drm/radeon/r100.c
3795
save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
3796
save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
sys/dev/drm/radeon/r100.c
3809
C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
sys/dev/drm/radeon/r100.c
3938
rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/r100.c
3967
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r100.c
3968
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r100.c
4026
tmp = RREG32(RADEON_CP_CSQ_CNTL);
sys/dev/drm/radeon/r100.c
4030
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/r100.c
4034
tmp = RREG32(RADEON_SCRATCH_UMSK);
sys/dev/drm/radeon/r100.c
4072
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r100.c
4073
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r100.c
455
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
459
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/drm/radeon/r100.c
486
tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
490
tmp = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/drm/radeon/r100.c
508
if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
sys/dev/drm/radeon/r100.c
530
if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
sys/dev/drm/radeon/r100.c
534
if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
sys/dev/drm/radeon/r100.c
559
tmp = RREG32(RADEON_FP_GEN_CNTL);
sys/dev/drm/radeon/r100.c
567
tmp = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/r100.c
659
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/drm/radeon/r100.c
666
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
sys/dev/drm/radeon/r100.c
681
tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
sys/dev/drm/radeon/r100.c
735
RREG32(RADEON_GEN_INT_CNTL);
sys/dev/drm/radeon/r100.c
74
if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
sys/dev/drm/radeon/r100.c
747
tmp = RREG32(R_000044_GEN_INT_STATUS);
sys/dev/drm/radeon/r100.c
753
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
sys/dev/drm/radeon/r100.c
79
if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
sys/dev/drm/radeon/r100.c
816
msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
sys/dev/drm/radeon/r100.c
831
return RREG32(RADEON_CRTC_CRNT_FRAME);
sys/dev/drm/radeon/r100.c
833
return RREG32(RADEON_CRTC2_CRNT_FRAME);
sys/dev/drm/radeon/r100.c
91
vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/drm/radeon/r100.c
92
vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/drm/radeon/r100.c
94
vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/drm/radeon/r100.c
95
vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/drm/radeon/r100.c
967
tmp = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r300.c
1418
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/r300.c
1449
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r300.c
1450
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r300.c
1530
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r300.c
1531
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r300.c
333
(RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
sys/dev/drm/radeon/r300.c
345
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/drm/radeon/r300.c
389
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r300.c
412
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r300.c
417
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r300.c
421
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/r300.c
432
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/r300.c
436
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r300.c
444
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/r300.c
448
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/r300.c
473
tmp = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/r300.c
484
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
sys/dev/drm/radeon/r300.c
60
r = RREG32(RADEON_PCIE_DATA);
sys/dev/drm/radeon/r420.c
133
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r420.c
137
RREG32(R300_RB2D_DSTCACHE_MODE) |
sys/dev/drm/radeon/r420.c
146
tmp = RREG32(RV530_GB_PIPE_SELECT2);
sys/dev/drm/radeon/r420.c
165
r = RREG32(R_0001FC_MC_IND_DATA);
sys/dev/drm/radeon/r420.c
283
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/r420.c
315
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r420.c
316
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r420.c
406
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r420.c
407
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r420.c
483
tmp = RREG32(R400_GB_PIPE_SELECT);
sys/dev/drm/radeon/r420.c
485
tmp = RREG32(R300_GB_TILE_CONFIG);
sys/dev/drm/radeon/r420.c
487
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r420.c
98
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
sys/dev/drm/radeon/r520.c
203
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/r520.c
232
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r520.c
233
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r520.c
278
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/r520.c
279
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/r520.c
82
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
sys/dev/drm/radeon/r520.c
83
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/r600.c
1090
tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
sys/dev/drm/radeon/r600.c
117
r = RREG32(R600_RCU_DATA);
sys/dev/drm/radeon/r600.c
1260
tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
sys/dev/drm/radeon/r600.c
1275
r = RREG32(R_0028FC_MC_DATA);
sys/dev/drm/radeon/r600.c
139
r = RREG32(R600_UVD_CTX_DATA);
sys/dev/drm/radeon/r600.c
1415
base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
sys/dev/drm/radeon/r600.c
1433
tmp = RREG32(RAMCFG);
sys/dev/drm/radeon/r600.c
1441
tmp = RREG32(CHMAP);
sys/dev/drm/radeon/r600.c
1462
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/r600.c
1463
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/r600.c
1547
u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/drm/radeon/r600.c
1560
RREG32(R_008010_GRBM_STATUS));
sys/dev/drm/radeon/r600.c
1562
RREG32(R_008014_GRBM_STATUS2));
sys/dev/drm/radeon/r600.c
1564
RREG32(R_000E50_SRBM_STATUS));
sys/dev/drm/radeon/r600.c
1566
RREG32(CP_STALLED_STAT1));
sys/dev/drm/radeon/r600.c
1568
RREG32(CP_STALLED_STAT2));
sys/dev/drm/radeon/r600.c
1570
RREG32(CP_BUSY_STAT));
sys/dev/drm/radeon/r600.c
1572
RREG32(CP_STAT));
sys/dev/drm/radeon/r600.c
1574
RREG32(DMA_STATUS_REG));
sys/dev/drm/radeon/r600.c
1584
if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
sys/dev/drm/radeon/r600.c
1585
crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/radeon/r600.c
1593
tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
sys/dev/drm/radeon/r600.c
1612
tmp = RREG32(R_008010_GRBM_STATUS);
sys/dev/drm/radeon/r600.c
1637
tmp = RREG32(DMA_STATUS_REG);
sys/dev/drm/radeon/r600.c
1642
tmp = RREG32(R_000E50_SRBM_STATUS);
sys/dev/drm/radeon/r600.c
1699
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/r600.c
173
*val = RREG32(reg);
sys/dev/drm/radeon/r600.c
1775
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1779
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1785
tmp = RREG32(R_008020_GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1789
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1793
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1799
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
1830
tmp = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/r600.c
1848
tmp = RREG32(BUS_CNTL);
sys/dev/drm/radeon/r600.c
1852
tmp = RREG32(BIF_SCRATCH0);
sys/dev/drm/radeon/r600.c
1866
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/drm/radeon/r600.c
2078
ramcfg = RREG32(RAMCFG);
sys/dev/drm/radeon/r600.c
2110
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
sys/dev/drm/radeon/r600.c
2115
disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
sys/dev/drm/radeon/r600.c
2150
tmp = RREG32(SX_DEBUG_1);
sys/dev/drm/radeon/r600.c
2175
tmp = RREG32(SQ_MS_FIFO_SIZES);
sys/dev/drm/radeon/r600.c
2194
sq_config = RREG32(SQ_CONFIG);
sys/dev/drm/radeon/r600.c
2368
tmp = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/r600.c
2371
tmp = RREG32(ARB_POP);
sys/dev/drm/radeon/r600.c
2393
(void)RREG32(PCIE_PORT_INDEX);
sys/dev/drm/radeon/r600.c
2394
r = RREG32(PCIE_PORT_DATA);
sys/dev/drm/radeon/r600.c
2405
(void)RREG32(PCIE_PORT_INDEX);
sys/dev/drm/radeon/r600.c
2407
(void)RREG32(PCIE_PORT_DATA);
sys/dev/drm/radeon/r600.c
2615
rptr = RREG32(R600_CP_RB_RPTR);
sys/dev/drm/radeon/r600.c
2623
return RREG32(R600_CP_RB_WPTR);
sys/dev/drm/radeon/r600.c
2630
(void)RREG32(R600_CP_RB_WPTR);
sys/dev/drm/radeon/r600.c
2671
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
2734
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
2856
tmp = RREG32(scratch);
sys/dev/drm/radeon/r600.c
3203
temp = RREG32(CONFIG_CNTL);
sys/dev/drm/radeon/r600.c
342
u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
sys/dev/drm/radeon/r600.c
3450
tmp = RREG32(scratch);
sys/dev/drm/radeon/r600.c
3551
RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
3554
RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/r600.c
3606
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/drm/radeon/r600.c
3607
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/r600.c
3618
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/r600.c
3619
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/drm/radeon/r600.c
3637
tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/r600.c
3646
tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3648
tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3650
tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3652
tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3655
tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3657
tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3659
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3661
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3664
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3666
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3672
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3674
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3676
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
sys/dev/drm/radeon/r600.c
3678
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3680
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3712
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/drm/radeon/r600.c
3798
hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3799
hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3800
hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3801
hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3803
hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3804
hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3805
hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3806
hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3808
hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3809
hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3812
hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3813
hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3814
hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
sys/dev/drm/radeon/r600.c
3815
hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3816
hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
sys/dev/drm/radeon/r600.c
3819
dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
sys/dev/drm/radeon/r600.c
3822
thermal_int = RREG32(CG_THERMAL_INT) &
sys/dev/drm/radeon/r600.c
3825
thermal_int = RREG32(RV770_CG_THERMAL_INT) &
sys/dev/drm/radeon/r600.c
3921
RREG32(R_000E50_SRBM_STATUS);
sys/dev/drm/radeon/r600.c
3931
rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
sys/dev/drm/radeon/r600.c
3932
rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
sys/dev/drm/radeon/r600.c
3933
rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
sys/dev/drm/radeon/r600.c
3935
rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
sys/dev/drm/radeon/r600.c
3936
rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
sys/dev/drm/radeon/r600.c
3938
rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
sys/dev/drm/radeon/r600.c
3939
rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
sys/dev/drm/radeon/r600.c
3942
rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
sys/dev/drm/radeon/r600.c
3943
rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
sys/dev/drm/radeon/r600.c
3945
rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
sys/dev/drm/radeon/r600.c
3946
rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
sys/dev/drm/radeon/r600.c
3948
rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
sys/dev/drm/radeon/r600.c
3949
rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
sys/dev/drm/radeon/r600.c
3965
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3969
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3976
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3980
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3987
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3991
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
3997
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/r600.c
4003
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/r600.c
4008
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/r600.c
4013
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
sys/dev/drm/radeon/r600.c
4018
tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
sys/dev/drm/radeon/r600.c
4024
tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/r600.c
4030
tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/r600.c
4034
tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/r600.c
4058
wptr = RREG32(IH_RB_WPTR);
sys/dev/drm/radeon/r600.c
4069
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/r600.c
4121
RREG32(IH_RB_WPTR);
sys/dev/drm/radeon/r600.c
4566
link_cntl2 = RREG32(0x4088);
sys/dev/drm/radeon/r600.c
4580
tmp = RREG32(0x541c);
sys/dev/drm/radeon/r600.c
4630
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/drm/radeon/r600.c
4631
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/drm/radeon/r600.c
787
if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
sys/dev/drm/radeon/r600.c
801
if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/drm/radeon/r600.c
805
if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/drm/radeon/r600.c
809
if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/drm/radeon/r600.c
813
if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/drm/radeon/r600.c
818
if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/drm/radeon/r600.c
822
if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
sys/dev/drm/radeon/r600.c
831
if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
sys/dev/drm/radeon/r600.c
835
if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
sys/dev/drm/radeon/r600.c
839
if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
sys/dev/drm/radeon/r600.c
858
tmp = RREG32(DC_HPD1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
866
tmp = RREG32(DC_HPD2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
874
tmp = RREG32(DC_HPD3_INT_CONTROL);
sys/dev/drm/radeon/r600.c
882
tmp = RREG32(DC_HPD4_INT_CONTROL);
sys/dev/drm/radeon/r600.c
890
tmp = RREG32(DC_HPD5_INT_CONTROL);
sys/dev/drm/radeon/r600.c
899
tmp = RREG32(DC_HPD6_INT_CONTROL);
sys/dev/drm/radeon/r600.c
912
tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/r600.c
920
tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/r600.c
928
tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
sys/dev/drm/radeon/r600_dma.c
158
dma_cntl = RREG32(DMA_CNTL);
sys/dev/drm/radeon/r600_dma.c
57
rptr = RREG32(DMA_RB_RPTR);
sys/dev/drm/radeon/r600_dma.c
73
return (RREG32(DMA_RB_WPTR) & 0x3fffc) >> 2;
sys/dev/drm/radeon/r600_dma.c
99
u32 rb_cntl = RREG32(DMA_RB_CNTL);
sys/dev/drm/radeon/r600_dpm.c
255
if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
sys/dev/drm/radeon/r600_dpm.c
263
RREG32(GRBM_PWR_CNTL);
sys/dev/drm/radeon/r600_dpm.c
298
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
sys/dev/drm/radeon/r600_dpm.c
333
if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
sys/dev/drm/radeon/r600_dpm.c
539
tmp = RREG32(VID_UPPER_GPIO_CNTL);
sys/dev/drm/radeon/r600_dpm.c
549
gpio = RREG32(GPIOPAD_MASK);
sys/dev/drm/radeon/r600_dpm.c
553
gpio = RREG32(GPIOPAD_EN);
sys/dev/drm/radeon/r600_dpm.c
557
gpio = RREG32(GPIOPAD_A);
sys/dev/drm/radeon/r600_dpm.c
629
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK;
sys/dev/drm/radeon/r600_dpm.c
638
tmp = RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_PROFILE_INDEX_MASK;
sys/dev/drm/radeon/r600_hdmi.c
100
value = RREG32(R600_AUDIO_STATUS_BITS);
sys/dev/drm/radeon/r600_hdmi.c
145
u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
sys/dev/drm/radeon/r600_hdmi.c
274
return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0;
sys/dev/drm/radeon/r600_hdmi.c
457
value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset);
sys/dev/drm/radeon/r600_hdmi.c
64
value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL);
sys/dev/drm/radeon/radeon.h
2567
uint32_t tmp_ = RREG32(reg); \
sys/dev/drm/radeon/radeon_agp.c
165
agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
sys/dev/drm/radeon/radeon_agp.c
253
WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
sys/dev/drm/radeon/radeon_atombios.c
4072
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4073
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4075
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4076
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4110
rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
sys/dev/drm/radeon/radeon_atombios.c
4134
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4136
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4166
bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4167
bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4168
bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4170
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4171
bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4172
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4351
bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4353
bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4406
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
sys/dev/drm/radeon/radeon_atombios.c
4408
bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
sys/dev/drm/radeon/radeon_audio.c
125
return RREG32(reg);
sys/dev/drm/radeon/radeon_bios.c
315
bus_cntl = RREG32(R600_BUS_CNTL);
sys/dev/drm/radeon/radeon_bios.c
316
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
317
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
318
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
319
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/drm/radeon/radeon_bios.c
363
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
364
bus_cntl = RREG32(R600_BUS_CNTL);
sys/dev/drm/radeon/radeon_bios.c
365
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
366
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
367
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
368
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/drm/radeon/radeon_bios.c
385
cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/radeon_bios.c
394
cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
sys/dev/drm/radeon/radeon_bios.c
409
cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
sys/dev/drm/radeon/radeon_bios.c
438
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
439
bus_cntl = RREG32(R600_BUS_CNTL);
sys/dev/drm/radeon/radeon_bios.c
440
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
441
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
442
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
443
rom_cntl = RREG32(R600_ROM_CNTL);
sys/dev/drm/radeon/radeon_bios.c
444
general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
sys/dev/drm/radeon/radeon_bios.c
445
low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
sys/dev/drm/radeon/radeon_bios.c
446
medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
sys/dev/drm/radeon/radeon_bios.c
447
high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
sys/dev/drm/radeon/radeon_bios.c
448
ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
sys/dev/drm/radeon/radeon_bios.c
449
lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
sys/dev/drm/radeon/radeon_bios.c
514
seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
sys/dev/drm/radeon/radeon_bios.c
515
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
516
bus_cntl = RREG32(RV370_BUS_CNTL);
sys/dev/drm/radeon/radeon_bios.c
517
d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
518
d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
519
vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
520
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
sys/dev/drm/radeon/radeon_bios.c
521
gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
sys/dev/drm/radeon/radeon_bios.c
522
gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
sys/dev/drm/radeon/radeon_bios.c
575
seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
sys/dev/drm/radeon/radeon_bios.c
576
viph_control = RREG32(RADEON_VIPH_CONTROL);
sys/dev/drm/radeon/radeon_bios.c
578
bus_cntl = RREG32(RV370_BUS_CNTL);
sys/dev/drm/radeon/radeon_bios.c
580
bus_cntl = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/radeon_bios.c
581
crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
sys/dev/drm/radeon/radeon_bios.c
583
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/drm/radeon/radeon_bios.c
589
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_bios.c
593
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/radeon_clocks.c
479
if ((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/drm/radeon/radeon_clocks.c
618
if (RREG32(RADEON_MEM_CNTL) &
sys/dev/drm/radeon/radeon_clocks.c
671
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/drm/radeon/radeon_clocks.c
676
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/drm/radeon/radeon_clocks.c
694
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/drm/radeon/radeon_clocks.c
706
((RREG32(RADEON_CONFIG_CNTL) &
sys/dev/drm/radeon/radeon_combios.c
1102
uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
sys/dev/drm/radeon/radeon_combios.c
1109
fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
sys/dev/drm/radeon/radeon_combios.c
1110
fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
sys/dev/drm/radeon/radeon_combios.c
1116
lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/drm/radeon/radeon_combios.c
1126
(RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
sys/dev/drm/radeon/radeon_combios.c
1134
((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
sys/dev/drm/radeon/radeon_combios.c
2912
val = RREG32(reg);
sys/dev/drm/radeon/radeon_combios.c
2966
val = RREG32(reg);
sys/dev/drm/radeon/radeon_combios.c
3033
tmp = RREG32(addr);
sys/dev/drm/radeon/radeon_combios.c
3043
tmp = RREG32(addr);
sys/dev/drm/radeon/radeon_combios.c
3068
if ((RREG32(RADEON_MC_STATUS) &
sys/dev/drm/radeon/radeon_combios.c
3196
if ((RREG32(RADEON_MEM_STR_CNTL) &
sys/dev/drm/radeon/radeon_combios.c
3205
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/drm/radeon/radeon_combios.c
3211
tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
sys/dev/drm/radeon/radeon_combios.c
3229
mem_cntl = RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/radeon_combios.c
3236
RREG32(RADEON_MEM_CNTL);
sys/dev/drm/radeon/radeon_combios.c
3419
bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3420
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3421
bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3444
bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3464
uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3465
uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3563
uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
sys/dev/drm/radeon/radeon_combios.c
3598
uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_cursor.c
37
cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/radeon_cursor.c
44
cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/radeon_cursor.c
51
cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/radeon_device.c
212
tmp = RREG32(reg);
sys/dev/drm/radeon/radeon_device.c
673
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
sys/dev/drm/radeon/radeon_device.c
674
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
sys/dev/drm/radeon/radeon_device.c
676
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
sys/dev/drm/radeon/radeon_device.c
677
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
sys/dev/drm/radeon/radeon_device.c
680
reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
sys/dev/drm/radeon/radeon_device.c
681
RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
sys/dev/drm/radeon/radeon_device.c
686
reg = RREG32(AVIVO_D1CRTC_CONTROL) |
sys/dev/drm/radeon/radeon_device.c
687
RREG32(AVIVO_D2CRTC_CONTROL);
sys/dev/drm/radeon/radeon_device.c
692
reg = RREG32(RADEON_CRTC_GEN_CNTL) |
sys/dev/drm/radeon/radeon_device.c
693
RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/radeon_device.c
702
reg = RREG32(R600_CONFIG_MEMSIZE);
sys/dev/drm/radeon/radeon_device.c
704
reg = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/drm/radeon/radeon_device.c
913
r = RREG32(reg*4);
sys/dev/drm/radeon/radeon_display.c
1828
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/drm/radeon/radeon_display.c
1830
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/drm/radeon/radeon_display.c
1835
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/drm/radeon/radeon_display.c
1837
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/drm/radeon/radeon_display.c
1842
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/drm/radeon/radeon_display.c
1844
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/drm/radeon/radeon_display.c
1849
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/drm/radeon/radeon_display.c
1851
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/drm/radeon/radeon_display.c
1856
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/drm/radeon/radeon_display.c
1858
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/drm/radeon/radeon_display.c
1863
vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
sys/dev/drm/radeon/radeon_display.c
1865
position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
sys/dev/drm/radeon/radeon_display.c
1871
vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
sys/dev/drm/radeon/radeon_display.c
1872
position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
sys/dev/drm/radeon/radeon_display.c
1876
vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
sys/dev/drm/radeon/radeon_display.c
1877
position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
sys/dev/drm/radeon/radeon_display.c
1886
vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
sys/dev/drm/radeon/radeon_display.c
1889
position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/drm/radeon/radeon_display.c
1890
stat_crtc = RREG32(RADEON_CRTC_STATUS);
sys/dev/drm/radeon/radeon_display.c
1897
vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
sys/dev/drm/radeon/radeon_display.c
1899
position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
sys/dev/drm/radeon/radeon_display.c
1900
stat_crtc = RREG32(RADEON_CRTC2_STATUS);
sys/dev/drm/radeon/radeon_display.c
195
dac2_cntl = RREG32(RADEON_DAC_CNTL2);
sys/dev/drm/radeon/radeon_dp_auxch.c
104
tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
153
tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
182
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
186
tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
sys/dev/drm/radeon/radeon_dp_auxch.c
99
tmp = RREG32(chan->rec.mask_clk_reg);
sys/dev/drm/radeon/radeon_dp_mst.c
177
temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
sys/dev/drm/radeon/radeon_dp_mst.c
35
reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
sys/dev/drm/radeon/radeon_dp_mst.c
54
temp = RREG32(NI_DIG_FE_CNTL + offset);
sys/dev/drm/radeon/radeon_dp_mst.c
76
temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
sys/dev/drm/radeon/radeon_dp_mst.c
94
temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
sys/dev/drm/radeon/radeon_fence.c
94
seq = RREG32(drv->scratch_reg);
sys/dev/drm/radeon/radeon_i2c.c
129
temp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
135
temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
138
temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
142
temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
145
temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
149
temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
151
temp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
153
temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
155
temp = RREG32(rec->mask_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
168
temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
170
temp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
172
temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
174
temp = RREG32(rec->mask_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
187
val = RREG32(rec->y_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
202
val = RREG32(rec->y_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
216
val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
sys/dev/drm/radeon/radeon_i2c.c
229
val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
sys/dev/drm/radeon/radeon_i2c.c
351
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
479
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
482
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
511
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
514
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
524
p->buf[j] = RREG32(i2c_data) & 0xff;
sys/dev/drm/radeon/radeon_i2c.c
539
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
542
tmp = RREG32(i2c_cntl_0);
sys/dev/drm/radeon/radeon_i2c.c
565
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
598
tmp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
601
tmp = RREG32(rec->mask_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
603
tmp = RREG32(rec->mask_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
606
tmp = RREG32(rec->mask_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
609
tmp = RREG32(rec->a_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
612
tmp = RREG32(rec->a_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
614
tmp = RREG32(rec->a_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
617
tmp = RREG32(rec->a_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
620
tmp = RREG32(rec->en_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
623
tmp = RREG32(rec->en_clk_reg);
sys/dev/drm/radeon/radeon_i2c.c
625
tmp = RREG32(rec->en_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
628
tmp = RREG32(rec->en_data_reg);
sys/dev/drm/radeon/radeon_i2c.c
631
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_i2c.c
633
saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
sys/dev/drm/radeon/radeon_i2c.c
634
saved2 = RREG32(0x494);
sys/dev/drm/radeon/radeon_i2c.c
640
if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
sys/dev/drm/radeon/radeon_i2c.c
687
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
690
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
729
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
732
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
743
p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
sys/dev/drm/radeon/radeon_i2c.c
772
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
775
tmp = RREG32(AVIVO_DC_I2C_STATUS1);
sys/dev/drm/radeon/radeon_i2c.c
802
tmp = RREG32(RADEON_BIOS_6_SCRATCH);
sys/dev/drm/radeon/radeon_irq_kms.c
574
u32 tmp = RREG32(reg);
sys/dev/drm/radeon/radeon_legacy_crtc.c
535
gen_cntl_val = RREG32(gen_cntl_reg);
sys/dev/drm/radeon/radeon_legacy_crtc.c
65
fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
sys/dev/drm/radeon/radeon_legacy_crtc.c
652
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
sys/dev/drm/radeon/radeon_legacy_crtc.c
672
disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
sys/dev/drm/radeon/radeon_legacy_crtc.c
68
fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
sys/dev/drm/radeon/radeon_legacy_crtc.c
685
crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
sys/dev/drm/radeon/radeon_legacy_crtc.c
703
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_crtc.c
709
disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1050
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1053
tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1055
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1056
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1169
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1213
gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1214
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1216
disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1218
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1221
disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1226
dac_cntl = RREG32(RADEON_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1231
gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1233
dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1259
dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
sys/dev/drm/radeon/radeon_legacy_encoders.c
1315
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1316
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1317
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1318
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1319
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1320
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1344
RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1355
RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1358
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1388
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1389
tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1390
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1391
config_cntl = RREG32(RADEON_CONFIG_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1392
tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1424
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1454
gpio_monid = RREG32(RADEON_GPIO_MONID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1455
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1456
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1457
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1458
disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1459
disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1460
disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1461
disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1462
disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1463
disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1464
crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1465
crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1466
crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1467
crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1469
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1498
tmp = RREG32(RADEON_GPIO_MONID);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1586
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1589
gpiopad_a = RREG32(RADEON_GPIOPAD_A);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1590
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1592
disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1594
crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1596
tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1597
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1598
dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
sys/dev/drm/radeon/radeon_legacy_encoders.c
1652
if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
sys/dev/drm/radeon/radeon_legacy_encoders.c
1655
if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
sys/dev/drm/radeon/radeon_legacy_encoders.c
186
lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
189
lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
196
lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
207
lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
277
backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
sys/dev/drm/radeon/radeon_legacy_encoders.c
352
backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
sys/dev/drm/radeon/radeon_legacy_encoders.c
406
backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
sys/dev/drm/radeon/radeon_legacy_encoders.c
522
uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
523
uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
524
uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
55
lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
597
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
sys/dev/drm/radeon/radeon_legacy_encoders.c
601
dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
606
disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
sys/dev/drm/radeon/radeon_legacy_encoders.c
611
dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
sys/dev/drm/radeon/radeon_legacy_encoders.c
630
dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
660
crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
661
dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
662
dac_cntl = RREG32(RADEON_DAC_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
663
dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
702
if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
sys/dev/drm/radeon/radeon_legacy_encoders.c
734
uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
793
tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
824
tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
sys/dev/drm/radeon/radeon_legacy_encoders.c
83
disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
sys/dev/drm/radeon/radeon_legacy_encoders.c
834
fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
sys/dev/drm/radeon/radeon_legacy_encoders.c
86
lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
898
uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
91
lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
960
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_encoders.c
962
fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
sys/dev/drm/radeon/radeon_legacy_tv.c
282
WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);
sys/dev/drm/radeon/radeon_legacy_tv.c
294
WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);
sys/dev/drm/radeon/radeon_legacy_tv.c
312
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/drm/radeon/radeon_legacy_tv.c
332
tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL);
sys/dev/drm/radeon/radeon_legacy_tv.c
338
return RREG32(RADEON_TV_HOST_READ_DATA);
sys/dev/drm/radeon/radeon_legacy_tv.c
620
tmp = RREG32(RADEON_TV_VSCALER_CNTL1);
sys/dev/drm/radeon/radeon_legacy_tv.c
662
tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0;
sys/dev/drm/radeon/radeon_legacy_tv.c
761
tmp = RREG32(RADEON_TV_DAC_CNTL);
sys/dev/drm/radeon/radeon_ring.c
299
ptr = RREG32(ring->rptr_save_reg);
sys/dev/drm/radeon/radeon_ring.c
483
rptr_next = RREG32(ring->rptr_save_reg);
sys/dev/drm/radeon/radeon_ttm.c
1102
value = RREG32(RADEON_MM_DATA);
sys/dev/drm/radeon/radeon_uvd.c
1038
if ((RREG32(cg_upll_func_cntl) & mask) == mask)
sys/dev/drm/radeon/rs400.c
151
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/drm/radeon/rs400.c
155
tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
sys/dev/drm/radeon/rs400.c
242
tmp = RREG32(RADEON_MC_STATUS);
sys/dev/drm/radeon/rs400.c
257
RREG32(RADEON_MC_STATUS));
sys/dev/drm/radeon/rs400.c
271
base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
sys/dev/drm/radeon/rs400.c
284
r = RREG32(RS480_NB_MC_DATA);
sys/dev/drm/radeon/rs400.c
307
tmp = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/rs400.c
309
tmp = RREG32(RADEON_BUS_CNTL);
sys/dev/drm/radeon/rs400.c
322
tmp = RREG32(RS690_HDP_FB_LOCATION);
sys/dev/drm/radeon/rs400.c
325
tmp = RREG32(RADEON_AGP_BASE);
sys/dev/drm/radeon/rs400.c
327
tmp = RREG32(RS480_AGP_BASE_2);
sys/dev/drm/radeon/rs400.c
329
tmp = RREG32(RADEON_MC_AGP_LOCATION);
sys/dev/drm/radeon/rs400.c
437
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/rs400.c
467
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rs400.c
468
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rs400.c
541
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rs400.c
542
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rs600.c
1010
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/rs600.c
1044
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rs600.c
1045
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rs600.c
1119
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rs600.c
1120
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rs600.c
115
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rs600.c
132
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
sys/dev/drm/radeon/rs600.c
148
return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/drm/radeon/rs600.c
226
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/rs600.c
235
tmp = RREG32(voltage->gpio.reg);
sys/dev/drm/radeon/rs600.c
321
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rs600.c
339
tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rs600.c
354
tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
sys/dev/drm/radeon/rs600.c
359
tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
sys/dev/drm/radeon/rs600.c
377
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
385
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
456
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/rs600.c
462
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/rs600.c
466
tmp = RREG32(RADEON_CP_RB_CNTL);
sys/dev/drm/radeon/rs600.c
478
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/rs600.c
482
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/rs600.c
486
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/rs600.c
490
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/rs600.c
494
RREG32(R_0000F0_RBBM_SOFT_RESET);
sys/dev/drm/radeon/rs600.c
498
status = RREG32(R_000E40_RBBM_STATUS);
sys/dev/drm/radeon/rs600.c
563
tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
sys/dev/drm/radeon/rs600.c
57
if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
sys/dev/drm/radeon/rs600.c
658
u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
sys/dev/drm/radeon/rs600.c
660
u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
sys/dev/drm/radeon/rs600.c
664
hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
sys/dev/drm/radeon/rs600.c
67
pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/radeon/rs600.c
68
pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
sys/dev/drm/radeon/rs600.c
702
RREG32(R_000040_GEN_INT_CNTL);
sys/dev/drm/radeon/rs600.c
709
uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
sys/dev/drm/radeon/rs600.c
714
rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
sys/dev/drm/radeon/rs600.c
724
tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
729
tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
sys/dev/drm/radeon/rs600.c
738
rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
sys/dev/drm/radeon/rs600.c
741
tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
sys/dev/drm/radeon/rs600.c
756
u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
sys/dev/drm/radeon/rs600.c
827
msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
sys/dev/drm/radeon/rs600.c
842
return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
sys/dev/drm/radeon/rs600.c
844
return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
sys/dev/drm/radeon/rs600.c
875
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/drm/radeon/rs600.c
907
d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
sys/dev/drm/radeon/rs600.c
908
d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
sys/dev/drm/radeon/rs600.c
91
if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
sys/dev/drm/radeon/rs600.c
925
r = RREG32(R_000074_MC_IND_DATA);
sys/dev/drm/radeon/rs690.c
157
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
sys/dev/drm/radeon/rs690.c
226
tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
sys/dev/drm/radeon/rs690.c
656
r = RREG32(R_00007C_MC_DATA);
sys/dev/drm/radeon/rs690.c
726
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/rs690.c
760
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rs690.c
761
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rs690.c
836
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rs690.c
837
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rs780_dpm.c
1007
u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
sys/dev/drm/radeon/rs780_dpm.c
1008
u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/rs780_dpm.c
211
u32 fbdiv = (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
sys/dev/drm/radeon/rs780_dpm.c
985
u32 current_fb_div = RREG32(FVTHROT_STATUS_REG0) & CURRENT_FEEDBACK_DIV_MASK;
sys/dev/drm/radeon/rs780_dpm.c
986
u32 func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/rv515.c
148
RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
sys/dev/drm/radeon/rv515.c
160
gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
sys/dev/drm/radeon/rv515.c
161
tmp = RREG32(R300_DST_PIPE_CONFIG);
sys/dev/drm/radeon/rv515.c
213
r = RREG32(MC_IND_DATA);
sys/dev/drm/radeon/rv515.c
239
tmp = RREG32(GB_PIPE_SELECT);
sys/dev/drm/radeon/rv515.c
241
tmp = RREG32(SU_REG_DEST);
sys/dev/drm/radeon/rv515.c
243
tmp = RREG32(GB_TILE_CONFIG);
sys/dev/drm/radeon/rv515.c
245
tmp = RREG32(DST_PIPE_CONFIG);
sys/dev/drm/radeon/rv515.c
257
tmp = RREG32(0x2140);
sys/dev/drm/radeon/rv515.c
260
tmp = RREG32(0x425C);
sys/dev/drm/radeon/rv515.c
297
save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
sys/dev/drm/radeon/rv515.c
298
save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
sys/dev/drm/radeon/rv515.c
304
crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
sys/dev/drm/radeon/rv515.c
307
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
325
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
340
blackout = RREG32(R700_MC_CITF_CNTL);
sys/dev/drm/radeon/rv515.c
342
blackout = RREG32(R600_CITF_CNTL);
sys/dev/drm/radeon/rv515.c
360
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
365
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
404
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
410
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
415
tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
421
tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
432
tmp = RREG32(R700_MC_CITF_CNTL);
sys/dev/drm/radeon/rv515.c
434
tmp = RREG32(R600_CITF_CNTL);
sys/dev/drm/radeon/rv515.c
446
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
sys/dev/drm/radeon/rv515.c
547
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
sys/dev/drm/radeon/rv515.c
576
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rv515.c
577
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rv515.c
656
RREG32(R_000E40_RBBM_STATUS),
sys/dev/drm/radeon/rv515.c
657
RREG32(R_0007C0_CP_STAT));
sys/dev/drm/radeon/rv6xx_dpm.c
1183
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/rv6xx_dpm.c
2035
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/rv6xx_dpm.c
2060
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/rv6xx_dpm.c
2083
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/rv6xx_dpm.c
788
tmp = (RREG32(RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/rv6xx_dpm.c
790
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_RESERVE_M) & 0x3) + 3);
sys/dev/drm/radeon/rv730_dpm.c
203
RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/rv730_dpm.c
205
RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/rv730_dpm.c
207
RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/drm/radeon/rv730_dpm.c
209
RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/rv730_dpm.c
211
RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/radeon/rv730_dpm.c
214
RREG32(TCI_MCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/rv730_dpm.c
216
RREG32(TCI_DLL_CNTL);
sys/dev/drm/radeon/rv730_dpm.c
218
RREG32(CG_MPLL_FUNC_CNTL);
sys/dev/drm/radeon/rv730_dpm.c
220
RREG32(CG_MPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/rv730_dpm.c
222
RREG32(CG_MPLL_FUNC_CNTL_3);
sys/dev/drm/radeon/rv730_dpm.c
224
RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/rv730_dpm.c
226
RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/radeon/rv730_dpm.c
403
arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) &
sys/dev/drm/radeon/rv730_dpm.c
412
old_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/rv730_dpm.c
413
old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/rv730_dpm.c
419
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/rv730_dpm.c
420
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/rv730_dpm.c
429
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/rv730_dpm.c
430
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/rv730_dpm.c
439
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/rv730_dpm.c
440
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/rv730_dpm.c
482
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
sys/dev/drm/radeon/rv730_dpm.c
488
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
sys/dev/drm/radeon/rv730_dpm.c
503
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0);
sys/dev/drm/radeon/rv730_dpm.c
506
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0);
sys/dev/drm/radeon/rv740_dpm.c
294
RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/rv740_dpm.c
296
RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/rv740_dpm.c
298
RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/drm/radeon/rv740_dpm.c
300
RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/rv740_dpm.c
302
RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/radeon/rv740_dpm.c
305
RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/drm/radeon/rv740_dpm.c
307
RREG32(MPLL_AD_FUNC_CNTL_2);
sys/dev/drm/radeon/rv740_dpm.c
309
RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/drm/radeon/rv740_dpm.c
311
RREG32(MPLL_DQ_FUNC_CNTL_2);
sys/dev/drm/radeon/rv740_dpm.c
313
RREG32(MCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/rv740_dpm.c
314
pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
sys/dev/drm/radeon/rv740_dpm.c
315
pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/drm/radeon/rv740_dpm.c
316
pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/drm/radeon/rv770.c
1018
tmp = RREG32(HDP_DEBUG1);
sys/dev/drm/radeon/rv770.c
1102
RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/rv770.c
1138
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/rv770.c
1144
if (RREG32(CG_SPLL_STATUS) & SPLL_CHG_STATUS)
sys/dev/drm/radeon/rv770.c
1152
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/drm/radeon/rv770.c
1296
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/rv770.c
1298
shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
sys/dev/drm/radeon/rv770.c
1312
cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
sys/dev/drm/radeon/rv770.c
1334
disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
sys/dev/drm/radeon/rv770.c
1399
ta_aux_cntl = RREG32(TA_CNTL_AUX);
sys/dev/drm/radeon/rv770.c
1402
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/drm/radeon/rv770.c
1406
smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
sys/dev/drm/radeon/rv770.c
1420
db_debug3 = RREG32(DB_DEBUG3);
sys/dev/drm/radeon/rv770.c
1436
db_debug4 = RREG32(DB_DEBUG4);
sys/dev/drm/radeon/rv770.c
1476
sq_config = RREG32(SQ_CONFIG);
sys/dev/drm/radeon/rv770.c
1589
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/rv770.c
1645
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/rv770.c
1653
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/rv770.c
1674
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/rv770.c
1675
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/rv770.c
2064
tmp = RREG32(0x541c);
sys/dev/drm/radeon/rv770.c
790
u32 tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/drm/radeon/rv770.c
804
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/rv770.c
828
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
sys/dev/drm/radeon/rv770.c
844
return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
sys/dev/drm/radeon/rv770.c
851
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
sys/dev/drm/radeon/rv770_dpm.c
1310
return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
sys/dev/drm/radeon/rv770_dpm.c
1348
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
143
RREG32(GB_TILING_CONFIG);
sys/dev/drm/radeon/rv770_dpm.c
1526
RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1528
RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/rv770_dpm.c
1530
RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/drm/radeon/rv770_dpm.c
1532
RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/rv770_dpm.c
1534
RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/radeon/rv770_dpm.c
1536
RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1538
RREG32(MPLL_AD_FUNC_CNTL_2);
sys/dev/drm/radeon/rv770_dpm.c
1540
RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1542
RREG32(MPLL_DQ_FUNC_CNTL_2);
sys/dev/drm/radeon/rv770_dpm.c
1544
RREG32(MCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1545
pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1563
RREG32(S0_VID_LOWER_SMIO_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1572
(RREG32(GENERAL_PWRMGT) & SW_SMIO_INDEX_MASK) >> SW_SMIO_INDEX_SHIFT;
sys/dev/drm/radeon/rv770_dpm.c
1575
vid_smio_cntl = RREG32(S3_VID_LOWER_SMIO_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1578
vid_smio_cntl = RREG32(S2_VID_LOWER_SMIO_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1581
vid_smio_cntl = RREG32(S1_VID_LOWER_SMIO_CNTL);
sys/dev/drm/radeon/rv770_dpm.c
1599
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/rv770_dpm.c
1640
RREG32(GB_TILING_CONFIG);
sys/dev/drm/radeon/rv770_dpm.c
1662
if (((RREG32(SMC_MSG) & HOST_SMC_RESP_MASK) >> HOST_SMC_RESP_SHIFT) == 1)
sys/dev/drm/radeon/rv770_dpm.c
175
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
sys/dev/drm/radeon/rv770_dpm.c
177
if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)
sys/dev/drm/radeon/rv770_dpm.c
211
if (RREG32(GENERAL_PWRMGT) & GLOBAL_PWRMGT_EN)
sys/dev/drm/radeon/rv770_dpm.c
2476
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/rv770_dpm.c
2505
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/rv770_dpm.c
2527
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_PROFILE_INDEX_MASK) >>
sys/dev/drm/radeon/rv770_dpm.c
734
tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/rv770_dpm.c
736
tmp = RREG32(MC_SEQ_MISC0) & 3;
sys/dev/drm/radeon/rv770_dpm.c
884
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/rv770_smc.c
335
original_data = RREG32(SMC_SRAM_DATA);
sys/dev/drm/radeon/rv770_smc.c
416
tmp = RREG32(SMC_IO);
sys/dev/drm/radeon/rv770_smc.c
436
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/drm/radeon/rv770_smc.c
443
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK;
sys/dev/drm/radeon/rv770_smc.c
459
if (RREG32(SMC_IO) & SMC_STOP_MODE)
sys/dev/drm/radeon/rv770_smc.c
612
*value = RREG32(SMC_SRAM_DATA);
sys/dev/drm/radeon/si.c
1311
*val = RREG32(reg);
sys/dev/drm/radeon/si.c
1334
tmp = RREG32(CG_CLKPIN_CNTL_2);
sys/dev/drm/radeon/si.c
1338
tmp = RREG32(CG_CLKPIN_CNTL);
sys/dev/drm/radeon/si.c
1351
temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
sys/dev/drm/radeon/si.c
1614
running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
sys/dev/drm/radeon/si.c
1646
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
sys/dev/drm/radeon/si.c
1651
if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
sys/dev/drm/radeon/si.c
1766
if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
sys/dev/drm/radeon/si.c
1996
if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
sys/dev/drm/radeon/si.c
2018
u32 tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/si.c
2421
arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/si.c
2430
tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);
sys/dev/drm/radeon/si.c
2968
data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/si.c
2973
data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/si.c
2992
data = RREG32(SPI_STATIC_THREAD_MGMT_3);
sys/dev/drm/radeon/si.c
3015
data = RREG32(CC_RB_BACKEND_DISABLE);
sys/dev/drm/radeon/si.c
3020
data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
sys/dev/drm/radeon/si.c
3194
mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/si.c
3195
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/si.c
3299
sx_debug_1 = RREG32(SX_DEBUG_1);
sys/dev/drm/radeon/si.c
3333
tmp = RREG32(HDP_MISC_CNTL);
sys/dev/drm/radeon/si.c
3337
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/si.c
3766
tmp = RREG32(GRBM_STATUS);
sys/dev/drm/radeon/si.c
3783
tmp = RREG32(GRBM_STATUS2);
sys/dev/drm/radeon/si.c
3788
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3793
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3798
tmp = RREG32(SRBM_STATUS2);
sys/dev/drm/radeon/si.c
3806
tmp = RREG32(SRBM_STATUS);
sys/dev/drm/radeon/si.c
3828
tmp = RREG32(VM_L2_STATUS);
sys/dev/drm/radeon/si.c
3854
RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
sys/dev/drm/radeon/si.c
3856
RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
sys/dev/drm/radeon/si.c
3870
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3876
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
3937
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3941
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3947
tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3951
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3955
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3961
tmp = RREG32(SRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
3977
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si.c
3981
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/si.c
3986
if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)
sys/dev/drm/radeon/si.c
3991
tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/si.c
3995
tmp = RREG32(MPLL_CNTL_MODE);
sys/dev/drm/radeon/si.c
4004
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/drm/radeon/si.c
4008
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si.c
4012
tmp = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si.c
4016
tmp = RREG32(SPLL_CNTL_MODE);
sys/dev/drm/radeon/si.c
4037
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
4041
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
sys/dev/drm/radeon/si.c
4067
if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
sys/dev/drm/radeon/si.c
4199
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/si.c
4207
tmp = RREG32(MC_SHARED_CHMAP);
sys/dev/drm/radeon/si.c
4243
tmp = RREG32(CONFIG_MEMSIZE);
sys/dev/drm/radeon/si.c
4369
rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
sys/dev/drm/radeon/si.c
5119
if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)
sys/dev/drm/radeon/si.c
5125
if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)
sys/dev/drm/radeon/si.c
5134
u32 tmp = RREG32(CP_INT_CNTL_RING0);
sys/dev/drm/radeon/si.c
5146
tmp = RREG32(DB_DEPTH_INFO);
sys/dev/drm/radeon/si.c
5150
if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
sys/dev/drm/radeon/si.c
5162
tmp = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/si.c
5185
u32 tmp = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/si.c
5195
orig = data = RREG32(RLC_CNTL);
sys/dev/drm/radeon/si.c
5211
tmp = RREG32(RLC_CNTL);
sys/dev/drm/radeon/si.c
5220
orig = data = RREG32(DMA_PG);
sys/dev/drm/radeon/si.c
5249
tmp = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/si.c
5253
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/si.c
5257
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/si.c
5261
tmp = RREG32(DB_RENDER_CONTROL);
sys/dev/drm/radeon/si.c
5271
tmp = RREG32(RLC_PG_CNTL);
sys/dev/drm/radeon/si.c
5277
tmp = RREG32(RLC_AUTO_PG_CTRL);
sys/dev/drm/radeon/si.c
5291
tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/si.c
5292
tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
sys/dev/drm/radeon/si.c
5335
tmp = RREG32(RLC_MAX_PG_CU);
sys/dev/drm/radeon/si.c
5346
orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
sys/dev/drm/radeon/si.c
5369
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si.c
5370
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si.c
5371
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si.c
5372
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si.c
5387
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/drm/radeon/si.c
5393
orig = data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/drm/radeon/si.c
5399
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/radeon/si.c
5412
orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
sys/dev/drm/radeon/si.c
5417
data = RREG32(CP_MEM_SLP_CNTL);
sys/dev/drm/radeon/si.c
5422
orig = data = RREG32(CGTS_SM_CTRL_REG);
sys/dev/drm/radeon/si.c
5447
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/si.c
5459
orig = data = RREG32(UVD_CGC_CTRL);
sys/dev/drm/radeon/si.c
5489
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/drm/radeon/si.c
5506
orig = data = RREG32(mc_cg_registers[i]);
sys/dev/drm/radeon/si.c
5528
orig = data = RREG32(DMA_POWER_CNTL + offset);
sys/dev/drm/radeon/si.c
5540
orig = data = RREG32(DMA_POWER_CNTL + offset);
sys/dev/drm/radeon/si.c
5545
orig = data = RREG32(DMA_CLK_CTRL + offset);
sys/dev/drm/radeon/si.c
5576
orig = data = RREG32(HDP_HOST_PATH_CNTL);
sys/dev/drm/radeon/si.c
5592
orig = data = RREG32(HDP_MEM_POWER_LS);
sys/dev/drm/radeon/si.c
5795
u32 tmp = RREG32(GRBM_SOFT_RESET);
sys/dev/drm/radeon/si.c
5828
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/si.c
5838
tmp = RREG32(RLC_LB_CNTL);
sys/dev/drm/radeon/si.c
5908
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/drm/radeon/si.c
5909
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/si.c
5920
u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/si.c
5921
u32 ih_cntl = RREG32(IH_CNTL);
sys/dev/drm/radeon/si.c
5939
tmp = RREG32(CP_INT_CNTL_RING0) &
sys/dev/drm/radeon/si.c
5944
tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/si.c
5946
tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/si.c
5988
interrupt_cntl = RREG32(INTERRUPT_CNTL);
sys/dev/drm/radeon/si.c
6057
cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
sys/dev/drm/radeon/si.c
6060
dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/si.c
6061
dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
sys/dev/drm/radeon/si.c
6063
thermal_int = RREG32(CG_THERMAL_INT) &
sys/dev/drm/radeon/si.c
6125
RREG32(SRBM_STATUS);
sys/dev/drm/radeon/si.c
6141
disp_int[i] = RREG32(si_disp_int_status[i]);
sys/dev/drm/radeon/si.c
6143
grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]);
sys/dev/drm/radeon/si.c
6203
wptr = RREG32(IH_RB_WPTR);
sys/dev/drm/radeon/si.c
6214
tmp = RREG32(IH_RB_CNTL);
sys/dev/drm/radeon/si.c
6349
DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
sys/dev/drm/radeon/si.c
6358
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
sys/dev/drm/radeon/si.c
6359
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
sys/dev/drm/radeon/si.c
6986
clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
sys/dev/drm/radeon/si.c
6987
((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
sys/dev/drm/radeon/si.c
7398
orig = data = RREG32(THM_CLK_CNTL);
sys/dev/drm/radeon/si.c
7404
orig = data = RREG32(MISC_CLK_CNTL);
sys/dev/drm/radeon/si.c
7410
orig = data = RREG32(CG_CLKPIN_CNTL);
sys/dev/drm/radeon/si.c
7415
orig = data = RREG32(CG_CLKPIN_CNTL_2);
sys/dev/drm/radeon/si.c
7420
orig = data = RREG32(MPLL_BYPASSCLK_SEL);
sys/dev/drm/radeon/si.c
7426
orig = data = RREG32(SPLL_CNTL_MODE);
sys/dev/drm/radeon/si_dpm.c
2110
cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
sys/dev/drm/radeon/si_dpm.c
2671
reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
sys/dev/drm/radeon/si_dpm.c
2754
data = RREG32(config_regs->offset << 2);
sys/dev/drm/radeon/si_dpm.c
3213
tmp = RREG32(MC_SEQ_MISC0);
sys/dev/drm/radeon/si_dpm.c
3219
width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
sys/dev/drm/radeon/si_dpm.c
3221
tmp = RREG32(MC_ARB_RAMCFG);
sys/dev/drm/radeon/si_dpm.c
3574
si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
sys/dev/drm/radeon/si_dpm.c
3575
si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/si_dpm.c
3576
si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
sys/dev/drm/radeon/si_dpm.c
3577
si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
sys/dev/drm/radeon/si_dpm.c
3578
si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
sys/dev/drm/radeon/si_dpm.c
3579
si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
sys/dev/drm/radeon/si_dpm.c
3580
si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
sys/dev/drm/radeon/si_dpm.c
3581
si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
sys/dev/drm/radeon/si_dpm.c
3582
si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
sys/dev/drm/radeon/si_dpm.c
3583
si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
sys/dev/drm/radeon/si_dpm.c
3584
si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
sys/dev/drm/radeon/si_dpm.c
3585
si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
sys/dev/drm/radeon/si_dpm.c
3586
si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
sys/dev/drm/radeon/si_dpm.c
3587
si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
sys/dev/drm/radeon/si_dpm.c
3588
si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
sys/dev/drm/radeon/si_dpm.c
3624
if (RREG32(SMC_RESP_0) == 1)
sys/dev/drm/radeon/si_dpm.c
3689
tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
sys/dev/drm/radeon/si_dpm.c
3702
tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
sys/dev/drm/radeon/si_dpm.c
3803
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
sys/dev/drm/radeon/si_dpm.c
4282
u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
sys/dev/drm/radeon/si_dpm.c
4289
dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
sys/dev/drm/radeon/si_dpm.c
4310
dram_timing = RREG32(MC_ARB_DRAM_TIMING);
sys/dev/drm/radeon/si_dpm.c
4311
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
sys/dev/drm/radeon/si_dpm.c
4312
burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
sys/dev/drm/radeon/si_dpm.c
5006
(RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
sys/dev/drm/radeon/si_dpm.c
5025
((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
sys/dev/drm/radeon/si_dpm.c
5026
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/si_dpm.c
5028
dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/si_dpm.c
5036
dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
sys/dev/drm/radeon/si_dpm.c
5370
temp_reg = RREG32(MC_PMG_CMD_EMRS);
sys/dev/drm/radeon/si_dpm.c
5381
temp_reg = RREG32(MC_PMG_CMD_MRS);
sys/dev/drm/radeon/si_dpm.c
5407
temp_reg = RREG32(MC_PMG_CMD_MRS1);
sys/dev/drm/radeon/si_dpm.c
5547
WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
sys/dev/drm/radeon/si_dpm.c
5548
WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
sys/dev/drm/radeon/si_dpm.c
5549
WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
sys/dev/drm/radeon/si_dpm.c
5550
WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
sys/dev/drm/radeon/si_dpm.c
5551
WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
sys/dev/drm/radeon/si_dpm.c
5552
WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
sys/dev/drm/radeon/si_dpm.c
5553
WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
sys/dev/drm/radeon/si_dpm.c
5554
WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
sys/dev/drm/radeon/si_dpm.c
5555
WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
sys/dev/drm/radeon/si_dpm.c
5556
WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
sys/dev/drm/radeon/si_dpm.c
5557
WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
sys/dev/drm/radeon/si_dpm.c
5558
WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
sys/dev/drm/radeon/si_dpm.c
5559
WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
sys/dev/drm/radeon/si_dpm.c
5560
WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
sys/dev/drm/radeon/si_dpm.c
5961
u32 thermal_int = RREG32(CG_THERMAL_INT);
sys/dev/drm/radeon/si_dpm.c
6014
tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6016
tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6021
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/radeon/si_dpm.c
6025
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/si_dpm.c
6046
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6090
tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6145
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6146
duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6178
duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6187
tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
sys/dev/drm/radeon/si_dpm.c
6218
tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/si_dpm.c
6235
tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
sys/dev/drm/radeon/si_dpm.c
6264
tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
sys/dev/drm/radeon/si_dpm.c
6280
tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
sys/dev/drm/radeon/si_dpm.c
6284
tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
sys/dev/drm/radeon/si_dpm.c
6304
tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
sys/dev/drm/radeon/si_dpm.c
6309
tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
sys/dev/drm/radeon/si_dpm.c
7099
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/radeon/si_dpm.c
7119
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/radeon/si_dpm.c
7137
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
sys/dev/drm/radeon/si_smc.c
126
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si_smc.c
127
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si_smc.c
128
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si_smc.c
129
RREG32(CB_CGTT_SCLK_CTRL);
sys/dev/drm/radeon/si_smc.c
183
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/si_smc.c
188
tmp = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/si_smc.c
291
*value = RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/si_smc.c
86
original_data = RREG32(SMC_IND_DATA_0);
sys/dev/drm/radeon/sumo_dpm.c
111
local0 = RREG32(CG_CGTT_LOCAL_0);
sys/dev/drm/radeon/sumo_dpm.c
112
local1 = RREG32(CG_CGTT_LOCAL_1);
sys/dev/drm/radeon/sumo_dpm.c
1745
u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
sys/dev/drm/radeon/sumo_dpm.c
1822
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
sys/dev/drm/radeon/sumo_dpm.c
1849
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
sys/dev/drm/radeon/sumo_dpm.c
283
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/sumo_dpm.c
502
u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
sys/dev/drm/radeon/sumo_dpm.c
516
u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
sys/dev/drm/radeon/sumo_dpm.c
526
u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
sys/dev/drm/radeon/sumo_dpm.c
542
cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
sys/dev/drm/radeon/sumo_dpm.c
555
u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
sys/dev/drm/radeon/sumo_dpm.c
604
if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
sys/dev/drm/radeon/sumo_dpm.c
634
if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
sys/dev/drm/radeon/sumo_dpm.c
645
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
sys/dev/drm/radeon/sumo_dpm.c
650
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
sys/dev/drm/radeon/sumo_dpm.c
743
u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
sys/dev/drm/radeon/sumo_dpm.c
805
u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
sys/dev/drm/radeon/sumo_dpm.c
880
u32 v = RREG32(DOUT_SCRATCH3);
sys/dev/drm/radeon/sumo_dpm.c
894
u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
sys/dev/drm/radeon/sumo_dpm.c
895
u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
sys/dev/drm/radeon/sumo_dpm.c
932
u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
sys/dev/drm/radeon/sumo_dpm.c
945
u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
sys/dev/drm/radeon/sumo_dpm.c
974
u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
sys/dev/drm/radeon/sumo_dpm.c
99
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/sumo_smc.c
42
if (RREG32(GFX_INT_STATUS) & INT_DONE)
sys/dev/drm/radeon/sumo_smc.c
51
if (RREG32(GFX_INT_REQ) & INT_REQ)
sys/dev/drm/radeon/sumo_smc.c
57
if (RREG32(GFX_INT_STATUS) & INT_ACK)
sys/dev/drm/radeon/sumo_smc.c
63
if (RREG32(GFX_INT_STATUS) & INT_DONE)
sys/dev/drm/radeon/trinity_dpm.c
2041
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
sys/dev/drm/radeon/trinity_dpm.c
2062
(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) >>
sys/dev/drm/radeon/trinity_dpm.c
376
u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
sys/dev/drm/radeon/trinity_dpm.c
456
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/trinity_dpm.c
517
RREG32(GB_ADDR_CONFIG);
sys/dev/drm/radeon/trinity_dpm.c
778
if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
sys/dev/drm/radeon/trinity_dpm.c
783
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0)
sys/dev/drm/radeon/trinity_dpm.c
788
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
sys/dev/drm/radeon/trinity_dpm.c
823
if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0)
sys/dev/drm/radeon/trinity_dpm.c
944
u32 tmp = RREG32(CG_MISC_REG);
sys/dev/drm/radeon/trinity_smc.c
118
if ((RREG32(SMC_INT_REQ) & 0xffff) == 1)
sys/dev/drm/radeon/trinity_smc.c
37
if (RREG32(SMC_RESP_0) != 0)
sys/dev/drm/radeon/trinity_smc.c
41
v = RREG32(SMC_RESP_0);
sys/dev/drm/radeon/uvd_v1_0.c
332
status = RREG32(UVD_STATUS);
sys/dev/drm/radeon/uvd_v1_0.c
370
ring->wptr = RREG32(UVD_RBC_RB_RPTR);
sys/dev/drm/radeon/uvd_v1_0.c
42
return RREG32(UVD_RBC_RB_RPTR);
sys/dev/drm/radeon/uvd_v1_0.c
438
tmp = RREG32(UVD_CONTEXT_ID);
sys/dev/drm/radeon/uvd_v1_0.c
56
return RREG32(UVD_RBC_RB_WPTR);
sys/dev/drm/radeon/vce_v1_0.c
108
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v1_0.c
112
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
117
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
121
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v1_0.c
125
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
130
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
140
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v1_0.c
144
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v1_0.c
149
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
153
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v1_0.c
259
if (RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_DONE)
sys/dev/drm/radeon/vce_v1_0.c
266
if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_PASS))
sys/dev/drm/radeon/vce_v1_0.c
271
if (!(RREG32(VCE_FW_REG_STATUS) & VCE_FW_REG_STATUS_BUSY))
sys/dev/drm/radeon/vce_v1_0.c
329
status = RREG32(VCE_STATUS);
sys/dev/drm/radeon/vce_v1_0.c
63
return RREG32(VCE_RB_RPTR);
sys/dev/drm/radeon/vce_v1_0.c
65
return RREG32(VCE_RB_RPTR2);
sys/dev/drm/radeon/vce_v1_0.c
80
return RREG32(VCE_RB_WPTR);
sys/dev/drm/radeon/vce_v1_0.c
82
return RREG32(VCE_RB_WPTR2);
sys/dev/drm/radeon/vce_v2_0.c
134
tmp = RREG32(VCE_CLOCK_GATING_A);
sys/dev/drm/radeon/vce_v2_0.c
140
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
145
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
43
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
47
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
51
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
57
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
62
tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
67
tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
77
tmp = RREG32(VCE_CLOCK_GATING_B);
sys/dev/drm/radeon/vce_v2_0.c
87
orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
sys/dev/drm/radeon/vce_v2_0.c
93
orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
