sys/dev/drm/amd/display/dc/bios/bios_parser_helper.c

61

REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

339

REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

353

REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

381

REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

66

REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

67

REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

70

REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));

sys/dev/drm/amd/display/dc/dce/dce_abm.c

71

REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

258

*sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,

sys/dev/drm/amd/display/dc/dce/dce_aux.c

274

REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);

sys/dev/drm/amd/display/dc/dce/dce_aux.c

291

REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

481

REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

184

REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

189

REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

275

REG_GET(DMCU_STATUS, UC_IN_RESET, &dmcu_uc_reset);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

116

REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

146

REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

307

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

313

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

333

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

630

REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);

sys/dev/drm/amd/display/dc/dce/dce_i2c_hw.c

73

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1332

REG_GET(DP_MSE_SAT_UPDATE,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1335

REG_GET(DP_MSE_SAT_UPDATE,

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

1355

REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

550

REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

588

dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

625

dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

682

REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending);

sys/dev/drm/amd/display/dc/dce/dce_opp.c

438

REG_GET(CONTROL,

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

921

REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1156

REG_GET(DCFE_MEM_PWR_STATUS,

sys/dev/drm/amd/display/dc/dce/dce_transform.c

1164

REG_GET(DCFE_MEM_LIGHT_SLEEP_CNTL,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

401

REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

749

REG_GET(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, &value);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

759

REG_GET(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

412

REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

420

REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

433

REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

106

REG_GET(DPP_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

108

REG_GET(CM_IGAM_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

110

REG_GET(CM_IGAM_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

112

REG_GET(CM_DGAM_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

114

REG_GET(CM_RGAM_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp.c

116

REG_GET(CM_GAMUT_REMAP_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

235

REG_GET(CM_TEST_DEBUG_DATA,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

490

REG_GET(CM_TEST_DEBUG_DATA,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

667

REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

757

REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c

827

REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

100

REG_GET(DCHUBBUB_ARB_DRAM_STATE_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

599

REG_GET(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

699

REG_GET(DCSURF_FLIP_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

702

REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

705

REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

827

REG_GET(HUBPRET_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

858

REG_GET(BLANK_OFFSET_1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

861

REG_GET(DST_DIMENSIONS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

881

REG_GET(REF_FREQ_TO_PIX_FREQ,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

885

REG_GET(VBLANK_PARAMETERS_1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

888

REG_GET(VBLANK_PARAMETERS_3,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

892

REG_GET(NOM_PARAMETERS_0,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

896

REG_GET(NOM_PARAMETERS_1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

899

REG_GET(NOM_PARAMETERS_4,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

902

REG_GET(NOM_PARAMETERS_5,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

914

REG_GET(PREFETCH_SETTINS_C,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

917

REG_GET(PREFETCH_SETTINGS_C,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

920

REG_GET(VBLANK_PARAMETERS_2,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

923

REG_GET(VBLANK_PARAMETERS_4,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

927

REG_GET(NOM_PARAMETERS_2,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

931

REG_GET(NOM_PARAMETERS_3,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

934

REG_GET(NOM_PARAMETERS_6,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

937

REG_GET(NOM_PARAMETERS_7,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

95

REG_GET(DCHUBP_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

957

REG_GET(DCN_SURF0_TTU_CNTL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

966

REG_GET(DCN_SURF1_TTU_CNTL1,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

971

REG_GET(DCSURF_SURFACE_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

974

REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

977

REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

988

REG_GET(DCSURF_TILING_CONFIG,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

991

REG_GET(DCSURF_SURFACE_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

999

REG_GET(DCN_GLOBAL_TTU_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1548

REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1550

REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1553

REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1556

REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1574

REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1575

REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1577

REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1579

REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1582

REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1584

REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1587

REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1589

REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1592

REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1594

REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

393

REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

394

REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

395

REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

396

REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1251

REG_GET(DP_MSE_SAT_UPDATE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1254

REG_GET(DP_MSE_SAT_UPDATE,

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

1274

REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

494

REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

133

REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

134

REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

135

REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

147

REG_GET(MPCC_TOP_SEL[mpcc_id],

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

380

REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

384

REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

385

REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

386

REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

400

REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

401

REG_GET(MPCC_TOP_SEL[bot_mpcc_id], MPCC_TOP_SEL, &top_sel);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

420

REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

421

REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

422

REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1182

REG_GET(OTG_STEREO_STATUS,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1195

REG_GET(OTG_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1202

REG_GET(OTG_V_SYNC_A_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1205

REG_GET(OTG_V_TOTAL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1208

REG_GET(OTG_V_TOTAL_MAX,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1211

REG_GET(OTG_V_TOTAL_MIN,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1214

REG_GET(OTG_V_TOTAL_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1217

REG_GET(OTG_V_TOTAL_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1232

REG_GET(OTG_H_SYNC_A_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1235

REG_GET(OTG_H_TOTAL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1238

REG_GET(OPTC_INPUT_GLOBAL_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1254

REG_GET(OTG_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1291

REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1302

REG_GET(OPTC_INPUT_GLOBAL_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1359

REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1369

REG_GET(OTG_CRC0_DATA_B,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

367

REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

591

REG_GET(OTG_STATUS_FRAME_COUNT,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

630

REG_GET(OTG_NOM_VERT_POSITION,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

654

REG_GET(OTG_FORCE_COUNT_NOW_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

657

REG_GET(OTG_VERT_SYNC_CONTROL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

681

REG_GET(OTG_V_SYNC_A_CNTL,

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

780

REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, &reg1);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

45

REG_GET(MASK_reg, MASK, &gpio->store.mask);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

46

REG_GET(A_reg, A, &gpio->store.a);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

47

REG_GET(EN_reg, EN, &gpio->store.en);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

86

REG_GET(Y_reg, Y, value);

sys/dev/drm/amd/display/dc/gpio/hw_hpd.c

89

REG_GET(int_status,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

289

*sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT,

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

305

REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32);

sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c

322

REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

128

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

194

REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

239

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

245

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

407

REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

421

REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);

sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c

531

REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);

sys/dev/drm/amd/display/dc/inc/reg_helper.h

49

#ifdef REG_GET