sys/dev/crypto/tpm/tpm20.h

175

WR4(sc, off, RD4(sc, off) & val);

sys/dev/crypto/tpm/tpm20.h

187

WR4(sc, off, RD4(sc, off) | val);

sys/dev/crypto/tpm/tpm_crb.c

190

crb_sc->rsp_off = RD4(sc, TPM_CRB_CTRL_RSP_ADDR);

sys/dev/crypto/tpm/tpm_crb.c

191

crb_sc->rsp_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_RSP_HADDR) << 32);

sys/dev/crypto/tpm/tpm_crb.c

193

crb_sc->cmd_off = RD4(sc, TPM_CRB_CTRL_CMD_LADDR);

sys/dev/crypto/tpm/tpm_crb.c

194

crb_sc->cmd_off |= ((uint64_t) RD4(sc, TPM_CRB_CTRL_CMD_HADDR) << 32);

sys/dev/crypto/tpm/tpm_crb.c

195

crb_sc->cmd_buf_size = RD4(sc, TPM_CRB_CTRL_CMD_SIZE);

sys/dev/crypto/tpm/tpm_crb.c

196

crb_sc->rsp_buf_size = RD4(sc, TPM_CRB_CTRL_RSP_SIZE);

sys/dev/crypto/tpm/tpm_crb.c

251

if ((RD4(sc, off) & mask) == val)

sys/dev/crypto/tpm/tpm_crb.c

255

if ((RD4(sc, off) & mask) == val)

sys/dev/crypto/tpm/tpm_crb.c

323

if (RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_ERR_BIT) {

sys/dev/crypto/tpm/tpm_crb.c

337

if (!(RD4(sc, TPM_CRB_CTRL_STS) & TPM_CRB_CTRL_STS_IDLE_BIT)) {

sys/dev/crypto/tpm/tpm_tis.c

218

irq_mask = RD4(sc, TPM_INT_ENABLE);

sys/dev/crypto/tpm/tpm_tis.c

241

status = RD4(sc, TPM_INT_STS);

sys/dev/crypto/tpm/tpm_tis.c

254

if ((RD4(sc, off) & mask) == val)

sys/dev/crypto/tpm/tpm_tis.c

262

return ((RD4(sc, off) & mask) == val);

sys/dev/crypto/tpm/tpm_tis.c

267

if ((RD4(sc, off) & mask) == val)

sys/dev/crypto/tpm/tpm_tis.c

285

burst_count = (RD4(sc, TPM_STS) & TPM_STS_BURST_MASK) >>

sys/dev/crypto/tpm/tpm_tis.c

377

AND4(sc, TPM_INT_STS, RD4(sc, TPM_INT_STS));

sys/dev/crypto/tpm/tpm_tis.c

430

if (RD4(sc, TPM_STS) & TPM_STS_DATA_EXPECTED) {

sys/dev/disk/sdhci/sdhci.c

1151

while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {

sys/dev/disk/sdhci/sdhci.c

1236

uint32_t val = RD4(slot, SDHCI_RESPONSE + i * 4);

sys/dev/disk/sdhci/sdhci.c

1246

slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);

sys/dev/disk/sdhci/sdhci.c

144

RD4(slot, SDHCI_SDMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION));

sys/dev/disk/sdhci/sdhci.c

148

RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE));

sys/dev/disk/sdhci/sdhci.c

150

RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL));

sys/dev/disk/sdhci/sdhci.c

1523

val = RD4(slot, SDHCI_PRESENT_STATE);

sys/dev/disk/sdhci/sdhci.c

156

RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));

sys/dev/disk/sdhci/sdhci.c

158

RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE));

sys/dev/disk/sdhci/sdhci.c

162

RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2));

sys/dev/disk/sdhci/sdhci.c

164

RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR));

sys/dev/disk/sdhci/sdhci.c

166

RD4(slot, SDHCI_ADMA_ADDRESS_LOW), RD2(slot, SDHCI_SLOT_INT_STATUS));

sys/dev/disk/sdhci/sdhci.c

1688

err = RD4(slot, SDHCI_ACMD12_ERR);

sys/dev/disk/sdhci/sdhci.c

1719

addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);

sys/dev/disk/sdhci/sdhci.c

1725

addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);

sys/dev/disk/sdhci/sdhci.c

1727

addr = RD4(slot, SDHCI_ADMA_ADDRESS_LOW);

sys/dev/disk/sdhci/sdhci.c

1756

intmask = RD4(slot, SDHCI_INT_STATUS);

sys/dev/disk/sdhci/sdhci.c

401

data = RD4(slot, SDHCI_BUFFER);

sys/dev/disk/sdhci/sdhci.c

416

data = RD4(slot, SDHCI_BUFFER);

sys/dev/disk/sdhci/sdhci.c

471

while (RD4(slot, SDHCI_PRESENT_STATE) &

sys/dev/disk/sdhci/sdhci.c

478

while (RD4(slot, SDHCI_PRESENT_STATE) &

sys/dev/disk/sdhci/sdhci.c

656

caps = RD4(slot, SDHCI_CAPABILITIES);

sys/dev/disk/sdhci/sdhci.c

658

caps2 = RD4(slot, SDHCI_CAPABILITIES2);

sys/dev/disk/sdhci/sdhci.c

917

return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);