PORT_E
if (is_crt && port != PORT_E)
if (is_dvi && (port == PORT_A || port == PORT_E))
if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E))
info->supports_dvi = (port != PORT_A && port != PORT_E);
info->supports_dp = (port != PORT_E);
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
[PORT_E] = DVO_PORT_DPE,
[PORT_E] = { DVO_PORT_DPE, DVO_PORT_HDMIE, },
crt->base.port = PORT_E;
I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
I915_WRITE(DP_TP_CTL(PORT_E),
I915_WRITE(DDI_BUF_CTL(PORT_E),
POSTING_READ(DDI_BUF_CTL(PORT_E));
temp = I915_READ(DP_TP_STATUS(PORT_E));
temp = I915_READ(DDI_BUF_CTL(PORT_E));
I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
POSTING_READ(DDI_BUF_CTL(PORT_E));
temp = I915_READ(DP_TP_CTL(PORT_E));
I915_WRITE(DP_TP_CTL(PORT_E), temp);
POSTING_READ(DP_TP_CTL(PORT_E));
intel_wait_ddi_buf_idle(dev_priv, PORT_E);
I915_WRITE(DP_TP_CTL(PORT_E),
_skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
WARN_ON(is_mst && (port == PORT_A || port == PORT_E));
[PORT_E] = TRANSCODER_A,
if (port == PORT_E)
if (port == PORT_E)
!intel_bios_is_port_present(dev_priv, PORT_E))
if (port == PORT_A || port == PORT_E) {
case PORT_E:
if (port == PORT_A || port == PORT_E)
intel_ddi_init(dev_priv, PORT_E);
(dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
intel_ddi_init(dev_priv, PORT_E);
case PORT_E:
case PORT_E:
(port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
case PORT_E:
case PORT_E:
case PORT_E:
!IS_CHERRYVIEW(dev_priv) && port < PORT_E);
case PORT_E:
case PORT_E:
if (port == PORT_E) {