PCIR_COMMAND
cmd = pci_read_config(self, PCIR_COMMAND, 2);
pci_write_config(self, PCIR_COMMAND, cmd, 2);
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
old_cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, old_cmd, 2);
cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
cfg->cmdreg = REG(PCIR_COMMAND, 2);
sc->command = pci_read_config(dev, PCIR_COMMAND, 1);
value = pci_read_config(pcidev, PCIR_COMMAND, 2);
config = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, config | PCIM_CMD_INTxDIS, 2);
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
#ifndef PCIR_COMMAND
pci_read_config(pcs->pci_dev, PCIR_COMMAND, 1));
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
val = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, val, 2);
mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
MPT_CHECK(Command, PCIR_COMMAND, 2);
pci_write_config(mpt->dev, PCIR_COMMAND, mpt->pci_cfg.Command, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd | PCIM_CMD_BUSMASTEREN, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400,2);
u_short command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, command, 2);
if (pci_read_config(dev, PCIR_COMMAND, 2) & 0x0400) {
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, command, 2);
cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2);
pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2);
pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2);
(void) pci_read_config(dev, PCIR_COMMAND, 4);
adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
val = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND,
#define PCI_COMMAND_REGISTER PCIR_COMMAND
sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
#define PCI_COMMAND_REGISTER PCIR_COMMAND
u = pci_read_config(self, PCIR_COMMAND, 1);
pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN, 1);
pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
u = pci_read_config(self, PCIR_COMMAND, 1);
cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
command = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, command, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(brdev, PCIR_COMMAND, 0, 2);
PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
if (!(pci_read_config(dev, PCIR_COMMAND, 2) & PCIM_CMD_BUSMASTEREN)) {
command = pci_read_config(dev, PCIR_COMMAND, 1);
pci_write_config(dev, PCIR_COMMAND, command, 2);
pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
pci_write_config(dev, PCIR_COMMAND,
pci_read_config(dev, PCIR_COMMAND, sizeof(char)) |
pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
command = pci_read_config(dev, PCIR_COMMAND, 1);
command = pci_read_config(dev, PCIR_COMMAND, 1);
command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, command, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, command, 2);
command = pci_read_config(sc->mly_dev, PCIR_COMMAND, 2);
pci_write_config(sc->mly_dev, PCIR_COMMAND, command, 2);
command = pci_read_config(sc->mly_dev, PCIR_COMMAND, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, command, 2);
command = pci_read_config(dev, PCIR_COMMAND, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
cmd = pci_read_config(sc->tws_dev, PCIR_COMMAND, 2);
pci_write_config(sc->tws_dev, PCIR_COMMAND, cmd, 2);
val = pci_read_config(dev, PCIR_COMMAND, 4);
pci_write_config(dev, PCIR_COMMAND, val, 4);
command = pci_read_config(dev, PCIR_COMMAND, 4);