lib/libefivar/efivar-dp-format.c

1011

ASSERT (NewStr != NULL);

lib/libefivar/efivar-dp-format.c

113

ASSERT (Str->Str != NULL);

lib/libefivar/efivar-dp-format.c

1754

ASSERT (UriStr != NULL);

lib/libefivar/efivar-dp-format.c

2327

ASSERT (Str.Str != NULL);

lib/libefivar/efivar-dp-parse.c

1062

ASSERT (AcpiAdr != NULL);

lib/libefivar/efivar-dp-parse.c

1076

ASSERT (AcpiAdr != NULL);

lib/libefivar/efivar-dp-parse.c

3602

ASSERT (DeviceNodeStr != NULL);

lib/libefivar/efivar-dp-parse.c

3660

ASSERT (DevicePath != NULL);

lib/libefivar/efivar-dp-parse.c

3676

ASSERT (DeviceNode != NULL);

lib/libefivar/uefi-dputil.c

153

ASSERT (DevicePath != NULL);

lib/libefivar/uefi-dputil.c

216

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

239

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

264

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

289

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

319

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

346

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

372

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

401

ASSERT (Node != NULL);

lib/libefivar/uefi-dputil.c

402

ASSERT ((Length >= sizeof (EFI_DEVICE_PATH_PROTOCOL)) && (Length < SIZE_64KB));

libexec/rtld-elf/malloc.c

249

ASSERT(sz > 0);

libexec/rtld-elf/malloc.c

288

ASSERT(op->ov_magic == MAGIC); /* make sure it was in use */

libexec/rtld-elf/malloc.c

294

ASSERT(op->ov_rmagic == RMAGIC);

libexec/rtld-elf/malloc.c

295

ASSERT(*(u_short *)((caddr_t)(op + 1) + op->ov_size) == RMAGIC);

libexec/rtld-elf/malloc.c

298

ASSERT(size < NBUCKETS);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2008

ASSERT(0);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4758

ASSERT(dc_state_temp);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

154

ASSERT(mst_mgr->payloads[i].payload_state !=

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

233

ASSERT(bpp != 0);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

106

ASSERT(res_value <= LLONG_MAX - summand);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

139

ASSERT(res.value <= LONG_MAX);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

145

ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

151

ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

160

ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

184

ASSERT(res.value <= LONG_MAX);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

190

ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

194

ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

203

ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

217

ASSERT(arg.value);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

316

ASSERT(dc_fixpt_lt(arg, dc_fixpt_one));

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

358

ASSERT(m != 0);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

360

ASSERT(dc_fixpt_lt(

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

385

ASSERT(arg.value > 0);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

50

ASSERT(divisor);

sys/dev/drm/amd/display/dc/basics/fixpt31_32.c

84

ASSERT(res_value <= LONG_MAX);

sys/dev/drm/amd/display/dc/bios/bios_parser_common.c

165

ASSERT(0);

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

100

ASSERT(res_value <= MAX_I64 - summand);

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

121

ASSERT(abs_i64(result.value) <= abs_i64(arg.value));

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

163

ASSERT(res.value <= BW_FIXED_MAX_I32);

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

169

ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

175

ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

184

ASSERT(tmp <= (uint64_t)(MAX_I64 - res.value));

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

52

ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32);

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

69

ASSERT(denominator != 0);

sys/dev/drm/amd/display/dc/calcs/bw_fixed.c

76

ASSERT(res_value <= BW_FIXED_MAX_I32);

sys/dev/drm/amd/display/dc/calcs/dce_calcs.c

2777

ASSERT(pipe[i].plane_state);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1152

ASSERT(hsplit_pipe);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1368

ASSERT(fclks.num_levels >= 3);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

334

ASSERT(0); /* Not supported */

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

348

ASSERT(0); /* Not supported */

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

523

ASSERT(primary_pipe->bottom_pipe != secondary_pipe);

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

909

ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

911

ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

914

ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

916

ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value

sys/dev/drm/amd/display/dc/core/dc.c

1708

ASSERT(dc->current_state->stream_count == 0);

sys/dev/drm/amd/display/dc/core/dc_link.c

111

ASSERT(bp_result == BP_RESULT_NORECORD);

sys/dev/drm/amd/display/dc/core/dc_link.c

1333

ASSERT(result == DDC_RESULT_SUCESSFULL);

sys/dev/drm/amd/display/dc/core/dc_link.c

1627

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1646

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1659

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1680

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1699

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1712

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1731

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1743

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1755

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1783

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1795

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1807

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1819

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1831

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1843

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1859

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1871

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1883

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

1914

ASSERT(i2c_success);

sys/dev/drm/amd/display/dc/core/dc_link.c

2335

ASSERT(proposed_table->stream_count -

sys/dev/drm/amd/display/dc/core/dc_link.c

2424

ASSERT(proposed_table.stream_count > 0);

sys/dev/drm/amd/display/dc/core/dc_link.c

377

ASSERT(gpio_result == GPIO_RESULT_OK);

sys/dev/drm/amd/display/dc/core/dc_link.c

915

ASSERT(false);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1135

ASSERT(dp_cs);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1420

ASSERT(bits_per_channel != 0);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

153

ASSERT(0);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1569

ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

669

ASSERT(0);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

676

ASSERT(0);

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

879

ASSERT(0);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1289

ASSERT(0);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1404

ASSERT(tail_pipe);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1859

ASSERT(del_pipe->stream_res.stream_enc);

sys/dev/drm/amd/display/dc/core/dc_resource.c

1962

ASSERT(0);

sys/dev/drm/amd/display/dc/core/dc_surface.c

108

ASSERT(0);

sys/dev/drm/amd/display/dc/dc_helper.c

264

ASSERT(delay_between_poll_us * time_out_num_tries <= 200000);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

185

ASSERT(dprefclk_src_sel == 0);

sys/dev/drm/amd/display/dc/dce/dce_dmcu.c

565

ASSERT(0);

sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c

369

ASSERT(speed);

sys/dev/drm/amd/display/dc/dce/dce_ipp.c

224

ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

266

ASSERT(REG(DP_DPHY_INTERNAL_CTRL));

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

412

ASSERT(cp2520_pattern == 2);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c

855

ASSERT(result == BP_RESULT_OK);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

547

ASSERT(pixels_per_frame);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

548

ASSERT(pixels_per_second);

sys/dev/drm/amd/display/dc/dce/dce_mem_input.c

556

ASSERT(refresh_rate);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

1326

ASSERT(audio_info);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

672

ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

673

ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

696

ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

80

ASSERT(0);

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.c

946

ASSERT(retries <= max_retries);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

627

ASSERT(depth < COLOR_DEPTH_121212); /* Invalid clamp bit depth */

sys/dev/drm/amd/display/dc/dce/dce_transform.c

675

ASSERT(pixel_width);

sys/dev/drm/amd/display/dc/dce/dce_transform.c

704

ASSERT(pixels_per_entries);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1809

ASSERT(dc->fbc_compressor);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1828

ASSERT(pipe_ctx);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2145

ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2430

ASSERT(pipe_ctx != NULL);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2508

ASSERT(0);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

261

ASSERT(false);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

674

ASSERT(pipe_ctx->stream);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1119

ASSERT(timing != NULL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

146

ASSERT(0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

504

ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubbub.c

539

ASSERT(false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

1121

ASSERT(param->h_scale_ratio.value);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hubp.c

168

ASSERT(plane_size->video.chroma_pitch != 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2023

ASSERT(new_mpcc != NULL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2564

ASSERT(false);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

231

ASSERT(REG(DP_DPHY_INTERNAL_CTRL));

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

379

ASSERT(cp2520_pattern == 2);

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c

800

ASSERT(result == BP_RESULT_OK);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

100

ASSERT(!(mpc10->mpcc_in_use_mask & 1 << id));

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

110

ASSERT(mpcc_id < mpc10->num_mpcc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

155

ASSERT(mpc_busy == 0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

156

ASSERT(mpc_idle == 1);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

189

ASSERT(mpcc_id < mpc10->num_mpcc);

sys/dev/drm/amd/display/dc/dcn10/dcn10_mpc.c

190

ASSERT(!(mpc10->mpcc_in_use_mask & 1 << mpcc_id));

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

124

ASSERT(0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

278

ASSERT(0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

525

ASSERT(timing != NULL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1092

ASSERT(0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1336

ASSERT(dc->dcn_soc->number_of_channels < 3);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

1165

ASSERT(audio_info);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

604

ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

605

ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

70

ASSERT(0);

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

806

ASSERT(retries <= max_retries);

sys/dev/drm/amd/display/dc/dm_services.h

132

ASSERT(mask != 0);

sys/dev/drm/amd/display/dc/dml/display_mode_lib.c

39

ASSERT(0);

sys/dev/drm/amd/display/dc/dml/display_mode_lib.c

51

ASSERT(0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1134

ASSERT(ref_freq_to_pix_freq < 4.0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1141

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1159

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1333

ASSERT(dst_y_prefetch >= 2.0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1427

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1476

ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1477

ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1479

ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1504

ASSERT(vratio_pre_l <= 4.0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1510

ASSERT(vratio_pre_c <= 4.0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1519

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1524

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1529

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1547

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1551

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1555

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1681

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1682

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1720

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1721

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1767

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1768

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1804

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1805

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1818

ASSERT(cur0_src_width <= 256);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

183

ASSERT(prefill > 0.0 && prefill <= 8.0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1853

ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1888

ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1896

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1899

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1910

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

489

ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

508

ASSERT(log2_dpte_row_height_linear >= 3);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

814

ASSERT((log2_dpte_req_width_ptes == 3 && log2_dpte_req_height_ptes == 0) || /* 8x1 */

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

835

ASSERT(log2_dpte_row_height_linear >= 3);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

930

ASSERT(0);

sys/dev/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

938

ASSERT(0);

sys/dev/drm/amd/display/dc/gpio/hw_gpio.c

202

ASSERT(!pin->base.opened);

sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c

452

ASSERT(speed);

sys/dev/drm/amd/display/dc/os_types.h

79

#define BREAK_TO_DEBUGGER() ASSERT(0)

sys/dev/drm/amd/display/include/fixed31_32.h

218

ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) ||

sys/dev/drm/amd/display/include/fixed31_32.h

255

ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) ||

sys/dev/drm/amd/display/include/fixed31_32.h

280

ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) ||

sys/dev/drm/amd/display/include/fixed31_32.h

469

ASSERT(LLONG_MAX - (long long)arg_value >= summand);

sys/dev/drm/amd/display/include/fixed31_32.h

490

ASSERT(LLONG_MAX - (long long)arg_value >= summand);

sys/dev/drm/amd/display/include/fixed31_32.h

523

ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART);

sys/dev/drm/amd/display/modules/color/color_gamma.c

1077

ASSERT(numberof_points > 0);

sys/dev/drm/amd/display/modules/freesync/freesync.c

132

ASSERT(v_total < stream->timing.v_total);

sys/dev/drm/amd/display/modules/freesync/freesync.c

158

ASSERT(v_total < stream->timing.v_total);

sys/dev/netif/ix/ixgbe_common.c

2672

ASSERT(0);

sys/dev/netif/ix/ixgbe_dcb_82599.c

539

ASSERT(0);