sys/dev/drm/amd/display/dc/core/dc.c

1001

for (k = 0; k < MAX_PIPES; k++) {

sys/dev/drm/amd/display/dc/core/dc.c

1114

for (j = 0; j < MAX_PIPES; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

201

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

227

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

261

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

267

if (i == MAX_PIPES)

sys/dev/drm/amd/display/dc/core/dc.c

310

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

316

if (i == MAX_PIPES)

sys/dev/drm/amd/display/dc/core/dc.c

335

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

372

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

389

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

411

struct pipe_ctx *pipes_affected[MAX_PIPES];

sys/dev/drm/amd/display/dc/core/dc.c

417

for (j = 0; j < MAX_PIPES; j++) {

sys/dev/drm/amd/display/dc/core/dc.c

469

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc.c

479

if (i == MAX_PIPES)

sys/dev/drm/amd/display/dc/core/dc.c

790

struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };

sys/dev/drm/amd/display/dc/core/dc.c

815

struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };

sys/dev/drm/amd/display/dc/core/dc.c

826

struct pipe_ctx *pipe_set[MAX_PIPES];

sys/dev/drm/amd/display/dc/core/dc.c

909

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_debug.c

314

int h_pos[MAX_PIPES], v_pos[MAX_PIPES];

sys/dev/drm/amd/display/dc/core/dc_link.c

2208

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

2605

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

278

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

71

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1201

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1240

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

1854

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

2581

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_resource.c

423

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_stream.c

203

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_stream.c

248

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_stream.c

279

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/core/dc_stream.c

303

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dc.h

287

struct dc_link *links[MAX_PIPES * 2];

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

110

uint32_t PHASE[MAX_PIPES];

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

111

uint32_t MODULO[MAX_PIPES];

sys/dev/drm/amd/display/dc/dce/dce_clock_source.h

112

uint32_t PIXEL_RATE_CNTL[MAX_PIPES];

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

138

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1636

for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1677

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1779

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1884

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2424

for (k = 0; k < MAX_PIPES; k++)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

998

for (i = 0; i < MAX_PIPES; i++) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2582

for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {

sys/dev/drm/amd/display/dc/inc/core_types.h

137

struct mem_input *mis[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

138

struct hubp *hubps[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

139

struct input_pixel_processor *ipps[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

140

struct transform *transforms[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

141

struct dpp *dpps[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

142

struct output_pixel_processor *opps[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

143

struct timing_generator *timing_generators[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

144

struct stream_encoder *stream_enc[MAX_PIPES * 2];

sys/dev/drm/amd/display/dc/inc/core_types.h

149

struct aux_engine *engines[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

150

struct dce_i2c_hw *hw_i2cs[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

151

struct dce_i2c_sw *sw_i2cs[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

168

struct audio *audios[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

240

struct pipe_ctx pipe_ctx[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

241

bool is_stream_enc_acquired[MAX_PIPES * 2];

sys/dev/drm/amd/display/dc/inc/core_types.h

242

bool is_audio_acquired[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

253

struct dce_watermarks urgent_wm_ns[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

254

struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

255

struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

256

struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

275

struct dc_stream_state *streams[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/core_types.h

276

struct dc_stream_status stream_status[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/hw/opp.h

200

int dpp[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/hw/opp.h

201

int mpcc[MAX_PIPES];

sys/dev/drm/amd/display/dc/inc/hw/opp.h

209

bool mpcc_disconnect_pending[MAX_PIPES];