sys/dev/drm/amd/display/dc/core/dc_link.c

2576

if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dc_helper.c

280

!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

sys/dev/drm/amd/display/dc/dc_helper.c

292

if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

sys/dev/drm/amd/display/dc/dc_types.h

62

(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

904

if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

336

if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

199

if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

123

if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

164

if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1101

if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2423

if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

746

if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

985

if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1464

(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?

sys/dev/drm/amd/display/dc/gpio/hw_factory.c

61

if (IS_FPGA_MAXIMUS_DC(dce_environment)) {

sys/dev/drm/amd/display/dc/gpio/hw_translate.c

61

if (IS_FPGA_MAXIMUS_DC(dce_environment)) {

sys/dev/drm/amd/display/dc/i2caux/i2caux.c

76

if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {