DP_DPCD_REV
ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV,
DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
st = core_link_read_dpcd(link, DP_DPCD_REV, &rev.raw,
core_link_read_dpcd(link, DP_DPCD_REV,
DP_DPCD_REV -
DP_DPCD_REV];
DP_DPCD_REV];
uint8_t dpcd_data[DP_ADAPTER_CAP - DP_DPCD_REV + 1];
DP_DPCD_REV,
dpcd_data[DP_DPCD_REV - DP_DPCD_REV];
DP_DPCD_REV];
DP_DPCD_REV];
DP_MAX_LANE_COUNT - DP_DPCD_REV];
DP_MAX_DOWNSPREAD - DP_DPCD_REV];
DP_MAX_LINK_RATE - DP_DPCD_REV];
DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV];
if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer,
err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
sret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE);
ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, buf, DP_RECEIVER_CAP_SIZE);
return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
return intel_dp->dpcd[DP_DPCD_REV] != 0;
WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,
return dpcd[DP_DPCD_REV] >= 0x11 &&
return dpcd[DP_DPCD_REV] >= 0x12 &&
return dpcd[DP_DPCD_REV] >= 0x14 &&
return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)