libexec/dma/conf.c

128

au->host = strsep(&data, DP);

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

103

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

104

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

105

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

53

SRI(DP_CONFIG, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

54

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

55

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

56

SRI(DP_DPHY_SCRAM_CNTL, DP, id),\

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

57

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

58

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

59

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

60

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

61

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

62

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

63

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

64

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

65

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

66

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

67

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

68

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

69

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

70

SRI(DP_SEC_CNTL1, DP, id)

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

74

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

75

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

79

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

84

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

85

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

90

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

91

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

92

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

97

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h

98

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

106

SRI(DP_DB_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

107

SRI(DP_MSA_MISC, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

108

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

109

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

110

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

111

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

112

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

84

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

85

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

86

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

87

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

88

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

89

SRI(DP_VID_M, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

90

SRI(DP_VID_N, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

91

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

92

SRI(DP_VID_TIMING, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

93

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/drm/amd/display/dc/dce/dce_stream_encoder.h

94

SRI(DP_SEC_TIMESTAMP, DP, id)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

244

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

46

SRI(DP_CONFIG, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

47

SRI(DP_DPHY_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

48

SRI(DP_DPHY_PRBS_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

49

SRI(DP_DPHY_SCRAM_CNTL, DP, id),\

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

50

SRI(DP_DPHY_SYM0, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

51

SRI(DP_DPHY_SYM1, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

52

SRI(DP_DPHY_SYM2, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

53

SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

54

SRI(DP_LINK_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

55

SRI(DP_LINK_FRAMING_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

56

SRI(DP_MSE_SAT0, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

57

SRI(DP_MSE_SAT1, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

58

SRI(DP_MSE_SAT2, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

59

SRI(DP_MSE_SAT_UPDATE, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

60

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

61

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

62

SRI(DP_DPHY_FAST_TRAINING, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

63

SRI(DP_SEC_CNTL1, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

64

SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

65

SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

66

SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

306

SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

73

SRI(DP_DB_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

74

SRI(DP_MSA_MISC, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

75

SRI(DP_MSA_COLORIMETRY, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

76

SRI(DP_MSA_TIMING_PARAM1, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

77

SRI(DP_MSA_TIMING_PARAM2, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

78

SRI(DP_MSA_TIMING_PARAM3, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

79

SRI(DP_MSA_TIMING_PARAM4, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

80

SRI(DP_MSE_RATE_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

81

SRI(DP_MSE_RATE_UPDATE, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

82

SRI(DP_PIXEL_FORMAT, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

83

SRI(DP_SEC_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

84

SRI(DP_STEER_FIFO, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

85

SRI(DP_VID_M, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

86

SRI(DP_VID_N, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

87

SRI(DP_VID_STREAM_CNTL, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

88

SRI(DP_VID_TIMING, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

89

SRI(DP_SEC_AUD_N, DP, id), \

sys/dev/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

90

SRI(DP_SEC_TIMESTAMP, DP, id)

sys/dev/drm/i915/intel_ddi.c

1245

intel_dp->DP = intel_dig_port->saved_port_bits |

sys/dev/drm/i915/intel_ddi.c

1247

intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);

sys/dev/drm/i915/intel_ddi.c

3333

intel_dp->DP |= DDI_BUF_CTL_ENABLE;

sys/dev/drm/i915/intel_ddi.c

3334

I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);

sys/dev/drm/i915/intel_display.c

11062

OUTPUT_TYPE(DP),

sys/dev/drm/i915/intel_dp.c

2166

intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;

sys/dev/drm/i915/intel_dp.c

2169

intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

sys/dev/drm/i915/intel_dp.c

2170

intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);

sys/dev/drm/i915/intel_dp.c

2176

intel_dp->DP |= DP_SYNC_HS_HIGH;

sys/dev/drm/i915/intel_dp.c

2178

intel_dp->DP |= DP_SYNC_VS_HIGH;

sys/dev/drm/i915/intel_dp.c

2179

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

sys/dev/drm/i915/intel_dp.c

2182

intel_dp->DP |= DP_ENHANCED_FRAMING;

sys/dev/drm/i915/intel_dp.c

2184

intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2188

intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

sys/dev/drm/i915/intel_dp.c

2198

intel_dp->DP |= DP_COLOR_RANGE_16_235;

sys/dev/drm/i915/intel_dp.c

2201

intel_dp->DP |= DP_SYNC_HS_HIGH;

sys/dev/drm/i915/intel_dp.c

2203

intel_dp->DP |= DP_SYNC_VS_HIGH;

sys/dev/drm/i915/intel_dp.c

2204

intel_dp->DP |= DP_LINK_TRAIN_OFF;

sys/dev/drm/i915/intel_dp.c

2207

intel_dp->DP |= DP_ENHANCED_FRAMING;

sys/dev/drm/i915/intel_dp.c

2210

intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2212

intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);

sys/dev/drm/i915/intel_dp.c

2734

intel_dp->DP &= ~DP_PLL_FREQ_MASK;

sys/dev/drm/i915/intel_dp.c

2737

intel_dp->DP |= DP_PLL_FREQ_162MHZ;

sys/dev/drm/i915/intel_dp.c

2739

intel_dp->DP |= DP_PLL_FREQ_270MHZ;

sys/dev/drm/i915/intel_dp.c

2741

I915_WRITE(DP_A, intel_dp->DP);

sys/dev/drm/i915/intel_dp.c

2754

intel_dp->DP |= DP_PLL_ENABLE;

sys/dev/drm/i915/intel_dp.c

2756

I915_WRITE(DP_A, intel_dp->DP);

sys/dev/drm/i915/intel_dp.c

2773

intel_dp->DP &= ~DP_PLL_ENABLE;

sys/dev/drm/i915/intel_dp.c

2775

I915_WRITE(DP_A, intel_dp->DP);

sys/dev/drm/i915/intel_dp.c

3062

uint32_t *DP,

sys/dev/drm/i915/intel_dp.c

3105

*DP &= ~DP_LINK_TRAIN_MASK_CPT;

sys/dev/drm/i915/intel_dp.c

3109

*DP |= DP_LINK_TRAIN_OFF_CPT;

sys/dev/drm/i915/intel_dp.c

3112

*DP |= DP_LINK_TRAIN_PAT_1_CPT;

sys/dev/drm/i915/intel_dp.c

3115

*DP |= DP_LINK_TRAIN_PAT_2_CPT;

sys/dev/drm/i915/intel_dp.c

3119

*DP |= DP_LINK_TRAIN_PAT_2_CPT;

sys/dev/drm/i915/intel_dp.c

3124

*DP &= ~DP_LINK_TRAIN_MASK;

sys/dev/drm/i915/intel_dp.c

3128

*DP |= DP_LINK_TRAIN_OFF;

sys/dev/drm/i915/intel_dp.c

3131

*DP |= DP_LINK_TRAIN_PAT_1;

sys/dev/drm/i915/intel_dp.c

3134

*DP |= DP_LINK_TRAIN_PAT_2;

sys/dev/drm/i915/intel_dp.c

3138

*DP |= DP_LINK_TRAIN_PAT_2;

sys/dev/drm/i915/intel_dp.c

3159

intel_dp->DP |= DP_PORT_EN;

sys/dev/drm/i915/intel_dp.c

3161

intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

sys/dev/drm/i915/intel_dp.c

3163

I915_WRITE(intel_dp->output_reg, intel_dp->DP);

sys/dev/drm/i915/intel_dp.c

3770

intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;

sys/dev/drm/i915/intel_dp.c

3772

I915_WRITE(intel_dp->output_reg, intel_dp->DP);

sys/dev/drm/i915/intel_dp.c

3784

_intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);

sys/dev/drm/i915/intel_dp.c

3786

I915_WRITE(intel_dp->output_reg, intel_dp->DP);

sys/dev/drm/i915/intel_dp.c

3830

uint32_t DP = intel_dp->DP;

sys/dev/drm/i915/intel_dp.c

3842

DP &= ~DP_LINK_TRAIN_MASK_CPT;

sys/dev/drm/i915/intel_dp.c

3843

DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;

sys/dev/drm/i915/intel_dp.c

3845

DP &= ~DP_LINK_TRAIN_MASK;

sys/dev/drm/i915/intel_dp.c

3846

DP |= DP_LINK_TRAIN_PAT_IDLE;

sys/dev/drm/i915/intel_dp.c

3848

I915_WRITE(intel_dp->output_reg, DP);

sys/dev/drm/i915/intel_dp.c

3851

DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);

sys/dev/drm/i915/intel_dp.c

3852

I915_WRITE(intel_dp->output_reg, DP);

sys/dev/drm/i915/intel_dp.c

3869

DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);

sys/dev/drm/i915/intel_dp.c

3870

DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |

sys/dev/drm/i915/intel_dp.c

3872

I915_WRITE(intel_dp->output_reg, DP);

sys/dev/drm/i915/intel_dp.c

3875

DP &= ~DP_PORT_EN;

sys/dev/drm/i915/intel_dp.c

3876

I915_WRITE(intel_dp->output_reg, DP);

sys/dev/drm/i915/intel_dp.c

3886

intel_dp->DP = DP;

sys/dev/drm/i915/intel_dp.c

5610

intel_dp->DP = I915_READ(intel_dp->output_reg);

sys/dev/drm/i915/intel_dp.c

6591

intel_dp->DP = I915_READ(intel_dp->output_reg);

sys/dev/drm/i915/intel_dp.c

717

uint32_t DP;

sys/dev/drm/i915/intel_dp.c

730

DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;

sys/dev/drm/i915/intel_dp.c

731

DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

sys/dev/drm/i915/intel_dp.c

732

DP |= DP_PORT_WIDTH(1);

sys/dev/drm/i915/intel_dp.c

733

DP |= DP_LINK_TRAIN_PAT_1;

sys/dev/drm/i915/intel_dp.c

736

DP |= DP_PIPE_SEL_CHV(pipe);

sys/dev/drm/i915/intel_dp.c

738

DP |= DP_PIPE_SEL(pipe);

sys/dev/drm/i915/intel_dp.c

764

I915_WRITE(intel_dp->output_reg, DP);

sys/dev/drm/i915/intel_dp.c

767

I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);

sys/dev/drm/i915/intel_dp.c

770

I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);

sys/dev/drm/i915/intel_dp_link_training.c

164

intel_dp->DP |= DP_PORT_EN;

sys/dev/drm/i915/intel_drv.h

1079

uint32_t DP;