crypto/libressl/crypto/aes/aes_core.c

1166

static const u8 Te4[256] = {

crypto/libressl/crypto/aes/aes_core.c

584

static const u8 Td4[256] = {

crypto/libressl/crypto/aes/aes_locl.h

68

#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }

crypto/libressl/crypto/asn1/a_int.c

133

uint8_t u8;

crypto/libressl/crypto/asn1/a_int.c

138

if (!CBS_get_u8(cbs, &u8))

crypto/libressl/crypto/asn1/a_int.c

144

val = val << 8 | u8;

crypto/libressl/crypto/asn1/a_int.c

158

uint8_t u8;

crypto/libressl/crypto/asn1/a_int.c

172

u8 = (val >> (i * 8)) & 0xff;

crypto/libressl/crypto/asn1/a_int.c

173

if (!started && i != 0 && u8 == 0)

crypto/libressl/crypto/asn1/a_int.c

175

if (!CBB_add_u8(&cbb, u8))

crypto/libressl/crypto/camellia/camellia.c

115

# define PUTU32(p,v) ((p)[0] = (u8)((v) >> 24), (p)[1] = (u8)((v) >> 16), (p)[2] = (u8)((v) >> 8), (p)[3] = (u8)(v))

crypto/libressl/crypto/camellia/camellia.c

347

Camellia_Ekeygen(int keyBitLength, const u8 *rawKey, KEY_TABLE_TYPE k)

crypto/libressl/crypto/camellia/camellia.c

465

Camellia_EncryptBlock_Rounds(int grandRounds, const u8 plaintext[],

crypto/libressl/crypto/camellia/camellia.c

466

const KEY_TABLE_TYPE keyTable, u8 ciphertext[])

crypto/libressl/crypto/camellia/camellia.c

509

Camellia_EncryptBlock(int keyBitLength, const u8 plaintext[],

crypto/libressl/crypto/camellia/camellia.c

510

const KEY_TABLE_TYPE keyTable, u8 ciphertext[])

crypto/libressl/crypto/camellia/camellia.c

517

Camellia_DecryptBlock_Rounds(int grandRounds, const u8 ciphertext[],

crypto/libressl/crypto/camellia/camellia.c

518

const KEY_TABLE_TYPE keyTable, u8 plaintext[])

crypto/libressl/crypto/camellia/camellia.c

561

Camellia_DecryptBlock(int keyBitLength, const u8 plaintext[],

crypto/libressl/crypto/camellia/camellia.c

562

const KEY_TABLE_TYPE keyTable, u8 ciphertext[])

crypto/libressl/crypto/camellia/cmll_locl.h

76

int Camellia_Ekeygen(int keyBitLength, const u8 *rawKey,

crypto/libressl/crypto/camellia/cmll_locl.h

78

void Camellia_EncryptBlock_Rounds(int grandRounds, const u8 plaintext[],

crypto/libressl/crypto/camellia/cmll_locl.h

79

const KEY_TABLE_TYPE keyTable, u8 ciphertext[]);

crypto/libressl/crypto/camellia/cmll_locl.h

80

void Camellia_DecryptBlock_Rounds(int grandRounds, const u8 ciphertext[],

crypto/libressl/crypto/camellia/cmll_locl.h

81

const KEY_TABLE_TYPE keyTable, u8 plaintext[]);

crypto/libressl/crypto/camellia/cmll_locl.h

82

void Camellia_EncryptBlock(int keyBitLength, const u8 plaintext[],

crypto/libressl/crypto/camellia/cmll_locl.h

83

const KEY_TABLE_TYPE keyTable, u8 ciphertext[]);

crypto/libressl/crypto/camellia/cmll_locl.h

84

void Camellia_DecryptBlock(int keyBitLength, const u8 ciphertext[],

crypto/libressl/crypto/camellia/cmll_locl.h

85

const KEY_TABLE_TYPE keyTable, u8 plaintext[]);

crypto/libressl/crypto/chacha/chacha-merged.c

114

chacha_ivsetup(chacha_ctx *x, const u8 *iv, const u8 *counter)

crypto/libressl/crypto/chacha/chacha-merged.c

123

chacha_encrypt_bytes(chacha_ctx *x, const u8 *m, u8 *c, u32 bytes)

crypto/libressl/crypto/chacha/chacha-merged.c

129

u8 *ctarget = NULL;

crypto/libressl/crypto/chacha/chacha-merged.c

130

u8 tmp[64];

crypto/libressl/crypto/chacha/chacha-merged.c

25

u8 ks[CHACHA_BLOCKLEN];

crypto/libressl/crypto/chacha/chacha-merged.c

26

u8 unused;

crypto/libressl/crypto/chacha/chacha-merged.c

29

static inline void chacha_keysetup(struct chacha_ctx *x, const u8 *k, u32 kbits)

crypto/libressl/crypto/chacha/chacha-merged.c

31

static inline void chacha_ivsetup(struct chacha_ctx *x, const u8 *iv,

crypto/libressl/crypto/chacha/chacha-merged.c

32

const u8 *ctr)

crypto/libressl/crypto/chacha/chacha-merged.c

35

static inline void chacha_encrypt_bytes(struct chacha_ctx *x, const u8 *m,

crypto/libressl/crypto/chacha/chacha-merged.c

36

u8 *c, u32 bytes)

crypto/libressl/crypto/chacha/chacha-merged.c

45

#define U8V(v) ((u8)(v) & U8C(0xFF))

crypto/libressl/crypto/chacha/chacha-merged.c

89

chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)

crypto/libressl/crypto/modes/ccm128.c

116

ctx->cmac.c[0] ^= (u8)(alen>>8);

crypto/libressl/crypto/modes/ccm128.c

117

ctx->cmac.c[1] ^= (u8)alen;

crypto/libressl/crypto/modes/ccm128.c

123

ctx->cmac.c[2] ^= (u8)(alen>>(56%(sizeof(alen)*8)));

crypto/libressl/crypto/modes/ccm128.c

124

ctx->cmac.c[3] ^= (u8)(alen>>(48%(sizeof(alen)*8)));

crypto/libressl/crypto/modes/ccm128.c

125

ctx->cmac.c[4] ^= (u8)(alen>>(40%(sizeof(alen)*8)));

crypto/libressl/crypto/modes/ccm128.c

126

ctx->cmac.c[5] ^= (u8)(alen>>(32%(sizeof(alen)*8)));

crypto/libressl/crypto/modes/ccm128.c

127

ctx->cmac.c[6] ^= (u8)(alen>>24);

crypto/libressl/crypto/modes/ccm128.c

128

ctx->cmac.c[7] ^= (u8)(alen>>16);

crypto/libressl/crypto/modes/ccm128.c

129

ctx->cmac.c[8] ^= (u8)(alen>>8);

crypto/libressl/crypto/modes/ccm128.c

130

ctx->cmac.c[9] ^= (u8)alen;

crypto/libressl/crypto/modes/ccm128.c

136

ctx->cmac.c[2] ^= (u8)(alen>>24);

crypto/libressl/crypto/modes/ccm128.c

137

ctx->cmac.c[3] ^= (u8)(alen>>16);

crypto/libressl/crypto/modes/ccm128.c

138

ctx->cmac.c[4] ^= (u8)(alen>>8);

crypto/libressl/crypto/modes/ccm128.c

139

ctx->cmac.c[5] ^= (u8)alen;

crypto/libressl/crypto/modes/ccm128.c

158

u8 c;

crypto/libressl/crypto/modes/ccm128.c

179

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

201

union { u64 u[2]; u8 c[16]; } temp;

crypto/libressl/crypto/modes/ccm128.c

254

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

272

union { u64 u[2]; u8 c[16]; } temp;

crypto/libressl/crypto/modes/ccm128.c

333

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

390

union { u64 u[2]; u8 c[16]; } scratch;

crypto/libressl/crypto/modes/ccm128.c

67

ctx->nonce.c[0] = ((u8)(L-1)&7) | (u8)(((M-2)/2)&7)<<3;

crypto/libressl/crypto/modes/ccm128.c

84

ctx->nonce.c[8] = (u8)(mlen>>(56%(sizeof(mlen)*8)));

crypto/libressl/crypto/modes/ccm128.c

85

ctx->nonce.c[9] = (u8)(mlen>>(48%(sizeof(mlen)*8)));

crypto/libressl/crypto/modes/ccm128.c

86

ctx->nonce.c[10] = (u8)(mlen>>(40%(sizeof(mlen)*8)));

crypto/libressl/crypto/modes/ccm128.c

87

ctx->nonce.c[11] = (u8)(mlen>>(32%(sizeof(mlen)*8)));

crypto/libressl/crypto/modes/ccm128.c

92

ctx->nonce.c[12] = (u8)(mlen>>24);

crypto/libressl/crypto/modes/ccm128.c

93

ctx->nonce.c[13] = (u8)(mlen>>16);

crypto/libressl/crypto/modes/ccm128.c

94

ctx->nonce.c[14] = (u8)(mlen>>8);

crypto/libressl/crypto/modes/ccm128.c

95

ctx->nonce.c[15] = (u8)mlen;

crypto/libressl/crypto/modes/ctr128.c

179

u8 c;

crypto/libressl/crypto/modes/ctr128.c

69

u8 c;

crypto/libressl/crypto/modes/gcm128.c

1082

const u8 *inp,size_t len) = ctx->ghash;

crypto/libressl/crypto/modes/gcm128.c

1112

u8 c = *(in++);

crypto/libressl/crypto/modes/gcm128.c

1220

u8 c = in[n];

crypto/libressl/crypto/modes/gcm128.c

1232

u8 c;

crypto/libressl/crypto/modes/gcm128.c

1270

const u8 *inp,size_t len) = ctx->ghash;

crypto/libressl/crypto/modes/gcm128.c

1388

const u8 *inp,size_t len) = ctx->ghash;

crypto/libressl/crypto/modes/gcm128.c

1416

u8 c = *(in++);

crypto/libressl/crypto/modes/gcm128.c

148

const u8 *xi = (const u8 *)Xi+15;

crypto/libressl/crypto/modes/gcm128.c

1490

u8 c = in[n];

crypto/libressl/crypto/modes/gcm128.c

1519

u8 *p = ctx->len.c;

crypto/libressl/crypto/modes/gcm128.c

220

if ((u8 *)Xi==xi) break;

crypto/libressl/crypto/modes/gcm128.c

239

u8 *p = (u8 *)Xi;

crypto/libressl/crypto/modes/gcm128.c

339

nlo = ((const u8 *)Xi)[15];

crypto/libressl/crypto/modes/gcm128.c

360

nlo = ((const u8 *)Xi)[cnt];

crypto/libressl/crypto/modes/gcm128.c

381

u8 *p = (u8 *)Xi;

crypto/libressl/crypto/modes/gcm128.c

403

const u8 *inp,size_t len)

crypto/libressl/crypto/modes/gcm128.c

412

nlo = ((const u8 *)Xi)[15];

crypto/libressl/crypto/modes/gcm128.c

434

nlo = ((const u8 *)Xi)[cnt];

crypto/libressl/crypto/modes/gcm128.c

458

u8 Hshl4[16]; /* Htable shifted left by 4 bits */

crypto/libressl/crypto/modes/gcm128.c

503

Hshl4[cnt] = (u8)(Z.lo<<4);

crypto/libressl/crypto/modes/gcm128.c

508

nlo = ((const u8 *)Xi)[cnt];

crypto/libressl/crypto/modes/gcm128.c

526

nlo = ((const u8 *)Xi)[0];

crypto/libressl/crypto/modes/gcm128.c

549

u8 *p = (u8 *)Xi;

crypto/libressl/crypto/modes/gcm128.c

565

void gcm_ghash_4bit(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

595

const u8 *p = (const u8 *)(xi+j);

crypto/libressl/crypto/modes/gcm128.c

599

const u8 *p = (const u8 *)(xi+j);

crypto/libressl/crypto/modes/gcm128.c

620

u8 *p = (u8 *)Xi;

crypto/libressl/crypto/modes/gcm128.c

652

void gcm_ghash_clmul(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

657

void gcm_ghash_4bit_mmx(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

660

void gcm_ghash_4bit_x86(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

668

void gcm_ghash_neon(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/gcm128.c

696

u8 *p = ctx->H.c;

crypto/libressl/crypto/modes/gcm128.c

791

ctx->Yi.c[8] ^= (u8)(len0>>56);

crypto/libressl/crypto/modes/gcm128.c

792

ctx->Yi.c[9] ^= (u8)(len0>>48);

crypto/libressl/crypto/modes/gcm128.c

793

ctx->Yi.c[10] ^= (u8)(len0>>40);

crypto/libressl/crypto/modes/gcm128.c

794

ctx->Yi.c[11] ^= (u8)(len0>>32);

crypto/libressl/crypto/modes/gcm128.c

795

ctx->Yi.c[12] ^= (u8)(len0>>24);

crypto/libressl/crypto/modes/gcm128.c

796

ctx->Yi.c[13] ^= (u8)(len0>>16);

crypto/libressl/crypto/modes/gcm128.c

797

ctx->Yi.c[14] ^= (u8)(len0>>8);

crypto/libressl/crypto/modes/gcm128.c

798

ctx->Yi.c[15] ^= (u8)(len0);

crypto/libressl/crypto/modes/gcm128.c

839

const u8 *inp,size_t len) = ctx->ghash;

crypto/libressl/crypto/modes/gcm128.c

900

const u8 *inp,size_t len) = ctx->ghash;

crypto/libressl/crypto/modes/modes_lcl.h

107

union { u64 u[2]; u8 c[16]; } nonce, cmac;

crypto/libressl/crypto/modes/modes_lcl.h

67

#define PUTU32(p,v) ((p)[0]=(u8)((v)>>24),(p)[1]=(u8)((v)>>16),(p)[2]=(u8)((v)>>8),(p)[3]=(u8)(v))

crypto/libressl/crypto/modes/modes_lcl.h

85

union { u64 u[2]; u32 d[4]; u8 c[16]; size_t t[16/sizeof(size_t)]; }

crypto/libressl/crypto/modes/modes_lcl.h

94

void (*ghash)(u64 Xi[2],const u128 Htable[16],const u8 *inp,size_t len);

crypto/libressl/crypto/modes/xts128.c

115

tweak.c[i] = (u8)c;

crypto/libressl/crypto/modes/xts128.c

118

tweak.c[0] ^= (u8)(0x87&(0-c));

crypto/libressl/crypto/modes/xts128.c

123

u8 c = inp[i];

crypto/libressl/crypto/modes/xts128.c

135

union { u64 u[2]; u8 c[16]; } tweak1;

crypto/libressl/crypto/modes/xts128.c

150

tweak1.c[i] = (u8)c;

crypto/libressl/crypto/modes/xts128.c

153

tweak1.c[0] ^= (u8)(0x87&(0-c));

crypto/libressl/crypto/modes/xts128.c

168

u8 c = inp[16+i];

crypto/libressl/crypto/modes/xts128.c

67

union { u64 u[2]; u32 d[4]; u8 c[16]; } tweak, scratch;

crypto/libressl/crypto/whrlpool/wp_block.c

167

u8 c[(256*N+ROUNDS)*sizeof(u64)];

crypto/libressl/crypto/whrlpool/wp_block.c

444

const u8 *p=inp;

crypto/libressl/crypto/whrlpool/wp_block.c

445

union { u64 q[8]; u8 c[64]; } S,K,*H=(void *)ctx->H.q;

crypto/libressl/ssl/ssl_both.c

406

uint8_t u8;

crypto/libressl/ssl/ssl_both.c

467

if (!CBS_get_u8(&cbs, &u8) ||

crypto/libressl/ssl/ssl_both.c

472

s->s3->hs.tls12.message_type = u8;

crypto/openssh/chacha.c

20

#define U8V(v) ((u8)(v) & U8C(0xFF))

crypto/openssh/chacha.c

55

chacha_keysetup(chacha_ctx *x,const u8 *k,u32 kbits)

crypto/openssh/chacha.c

80

chacha_ivsetup(chacha_ctx *x, const u8 *iv, const u8 *counter)

crypto/openssh/chacha.c

89

chacha_encrypt_bytes(chacha_ctx *x,const u8 *m,u8 *c,u32 bytes)

crypto/openssh/chacha.c

93

u8 *ctarget = NULL;

crypto/openssh/chacha.c

94

u8 tmp[64];

crypto/openssh/cipher-aesctr.c

33

aesctr_inc(u8 *ctr, u32 len)

crypto/openssh/cipher-aesctr.c

42

u8 x, add = 1;

crypto/openssh/cipher-aesctr.c

57

aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits)

crypto/openssh/cipher-aesctr.c

63

aesctr_ivsetup(aesctr_ctx *x,const u8 *iv)

crypto/openssh/cipher-aesctr.c

69

aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes)

crypto/openssh/cipher-aesctr.c

72

u8 buf[AES_BLOCK_SIZE];

crypto/openssh/cipher-aesctr.h

28

u8 ctr[AES_BLOCK_SIZE]; /* counter */

crypto/openssh/cipher-aesctr.h

31

void aesctr_keysetup(aesctr_ctx *x,const u8 *k,u32 kbits,u32 ivbits);

crypto/openssh/cipher-aesctr.h

32

void aesctr_ivsetup(aesctr_ctx *x,const u8 *iv);

crypto/openssh/cipher-aesctr.h

33

void aesctr_encrypt_bytes(aesctr_ctx *x,const u8 *m,u8 *c,u32 bytes);

crypto/openssh/rijndael.c

580

static const u8 Td4[256] = {

crypto/openssh/rijndael.c

622

#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }

crypto/openssh/rijndael.c

630

rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

crypto/openssh/rijndael.c

718

rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits)

crypto/openssh/rijndael.c

762

rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16],

crypto/openssh/rijndael.c

763

u8 ct[16])

crypto/openssh/rijndael.c

947

rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16],

crypto/openssh/rijndael.c

948

u8 pt[16])

crypto/openssh/rijndael.h

41

void rijndaelEncrypt(const unsigned int [], int, const u8 [16], u8 [16]);

crypto/openssh/umac.c

173

rijndaelEncrypt((u32 *)(int_key), AES_ROUNDS, (u8 *)(in), (u8 *)(out))

sys/crypto/chacha20/chacha.c

101

chacha_ctrsave(const chacha_ctx *x, u8 *counter)

sys/crypto/chacha20/chacha.c

111

chacha_encrypt_bytes(chacha_ctx *x, const u8 *m, u8 *c, u32 bytes)

sys/crypto/chacha20/chacha.c

115

u8 *ctarget = NULL;

sys/crypto/chacha20/chacha.c

116

u8 tmp[64];

sys/crypto/chacha20/chacha.c

21

#define U8V(v) ((u8)(v) & U8C(0xFF))

sys/crypto/chacha20/chacha.c

264

hchacha20(u8 derived_key[32], const u8 nonce[16], const u8 key[32])

sys/crypto/chacha20/chacha.c

56

chacha_keysetup(chacha_ctx *x, const u8 *k, u32 kbits)

sys/crypto/chacha20/chacha.c

81

chacha_ivsetup(chacha_ctx *x, const u8 *iv, const u8 *counter)

sys/crypto/rijndael/rijndael-alg-fst.c

1043

void rijndaelDecrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 ct[16], u8 pt[16]) {

sys/crypto/rijndael/rijndael-alg-fst.c

727

#define PUTU32(ct, st) { (ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); (ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); }

sys/crypto/rijndael/rijndael-alg-fst.c

734

int rijndaelKeySetupEnc(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits) {

sys/crypto/rijndael/rijndael-alg-fst.c

822

int rijndaelKeySetupDec(u32 rk[/*4*(Nr + 1)*/], const u8 cipherKey[], int keyBits) {

sys/crypto/rijndael/rijndael-alg-fst.c

862

void rijndaelEncrypt(const u32 rk[/*4*(Nr + 1)*/], int Nr, const u8 pt[16], u8 ct[16]) {

sys/dev/disk/sym/sym_defs.h

267

/*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */

sys/dev/disk/sym/sym_defs.h

269

/*01*/ u8 nc_scntl1; /* no reset */

sys/dev/disk/sym/sym_defs.h

274

/*02*/ u8 nc_scntl2; /* no disconnect expected */

sys/dev/disk/sym/sym_defs.h

280

/*03*/ u8 nc_scntl3; /* cnf system clock dependent */

sys/dev/disk/sym/sym_defs.h

285

/*04*/ u8 nc_scid; /* cnf host adapter scsi address */

sys/dev/disk/sym/sym_defs.h

289

/*05*/ u8 nc_sxfer; /* ### Sync speed and count */

sys/dev/disk/sym/sym_defs.h

292

/*06*/ u8 nc_sdid; /* ### Destination-ID */

sys/dev/disk/sym/sym_defs.h

294

/*07*/ u8 nc_gpreg; /* ??? IO-Pins */

sys/dev/disk/sym/sym_defs.h

296

/*08*/ u8 nc_sfbr; /* ### First byte received */

sys/dev/disk/sym/sym_defs.h

298

/*09*/ u8 nc_socl;

sys/dev/disk/sym/sym_defs.h

308

/*0a*/ u8 nc_ssid;

sys/dev/disk/sym/sym_defs.h

310

/*0b*/ u8 nc_sbcl;

sys/dev/disk/sym/sym_defs.h

312

/*0c*/ u8 nc_dstat;

sys/dev/disk/sym/sym_defs.h

321

/*0d*/ u8 nc_sstat0;

sys/dev/disk/sym/sym_defs.h

331

/*0e*/ u8 nc_sstat1;

sys/dev/disk/sym/sym_defs.h

334

/*0f*/ u8 nc_sstat2;

sys/dev/disk/sym/sym_defs.h

341

/*10*/ u8 nc_dsa; /* --> Base page */

sys/dev/disk/sym/sym_defs.h

342

/*11*/ u8 nc_dsa1;

sys/dev/disk/sym/sym_defs.h

343

/*12*/ u8 nc_dsa2;

sys/dev/disk/sym/sym_defs.h

344

/*13*/ u8 nc_dsa3;

sys/dev/disk/sym/sym_defs.h

346

/*14*/ u8 nc_istat; /* --> Main Command and status */

sys/dev/disk/sym/sym_defs.h

356

/*15*/ u8 nc_istat1; /* 896 only */

sys/dev/disk/sym/sym_defs.h

357

/*16*/ u8 nc_mbox0; /* 896 only */

sys/dev/disk/sym/sym_defs.h

358

/*17*/ u8 nc_mbox1; /* 896 only */

sys/dev/disk/sym/sym_defs.h

360

/*18*/ u8 nc_ctest0;

sys/dev/disk/sym/sym_defs.h

361

/*19*/ u8 nc_ctest1;

sys/dev/disk/sym/sym_defs.h

363

/*1a*/ u8 nc_ctest2;

sys/dev/disk/sym/sym_defs.h

367

/*1b*/ u8 nc_ctest3;

sys/dev/disk/sym/sym_defs.h

376

/*20*/ u8 nc_dfifo;

sys/dev/disk/sym/sym_defs.h

377

/*21*/ u8 nc_ctest4;

sys/dev/disk/sym/sym_defs.h

381

/*22*/ u8 nc_ctest5;

sys/dev/disk/sym/sym_defs.h

385

/*23*/ u8 nc_ctest6;

sys/dev/disk/sym/sym_defs.h

392

/*34*/ u8 nc_scratcha; /* Temporary register a */

sys/dev/disk/sym/sym_defs.h

393

/*35*/ u8 nc_scratcha1;

sys/dev/disk/sym/sym_defs.h

394

/*36*/ u8 nc_scratcha2;

sys/dev/disk/sym/sym_defs.h

395

/*37*/ u8 nc_scratcha3;

sys/dev/disk/sym/sym_defs.h

397

/*38*/ u8 nc_dmode;

sys/dev/disk/sym/sym_defs.h

404

/*39*/ u8 nc_dien;

sys/dev/disk/sym/sym_defs.h

405

/*3a*/ u8 nc_sbr;

sys/dev/disk/sym/sym_defs.h

407

/*3b*/ u8 nc_dcntl; /* --> Script execution control */

sys/dev/disk/sym/sym_defs.h

435

/*44*/ u8 nc_slpar;

sys/dev/disk/sym/sym_defs.h

436

/*45*/ u8 nc_swide;

sys/dev/disk/sym/sym_defs.h

437

/*46*/ u8 nc_macntl;

sys/dev/disk/sym/sym_defs.h

438

/*47*/ u8 nc_gpcntl;

sys/dev/disk/sym/sym_defs.h

439

/*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/

sys/dev/disk/sym/sym_defs.h

440

/*49*/ u8 nc_stime1; /* cmd: timeout user defined */

sys/dev/disk/sym/sym_defs.h

443

/*4c*/ u8 nc_stest0;

sys/dev/disk/sym/sym_defs.h

445

/*4d*/ u8 nc_stest1;

sys/dev/disk/sym/sym_defs.h

451

/*4e*/ u8 nc_stest2;

sys/dev/disk/sym/sym_defs.h

455

/*4f*/ u8 nc_stest3;

sys/dev/disk/sym/sym_defs.h

461

/*52*/ u8 nc_stest4;

sys/dev/disk/sym/sym_defs.h

469

/*53*/ u8 nc_53_;

sys/dev/disk/sym/sym_defs.h

471

/*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */

sys/dev/disk/sym/sym_defs.h

479

/*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */

sys/dev/disk/sym/sym_defs.h

489

/*5c*/ u8 nc_scr0; /* Working register B */

sys/dev/disk/sym/sym_defs.h

490

/*5d*/ u8 nc_scr1;

sys/dev/disk/sym/sym_defs.h

491

/*5e*/ u8 nc_scr2;

sys/dev/disk/sym/sym_defs.h

492

/*5f*/ u8 nc_scr3;

sys/dev/disk/sym/sym_defs.h

494

/*60*/ u8 nc_scrx[64]; /* Working register C-R */

sys/dev/disk/sym/sym_defs.h

510

/*be*/ u8 nc_aipcntl0; /* AIP Control 0 C1010 only */

sys/dev/disk/sym/sym_defs.h

511

/*bf*/ u8 nc_aipcntl1; /* AIP Control 1 C1010 only */

sys/dev/disk/sym/sym_defs.h

515

/*c8*/ u8 nc_rbc; /* Remaining Byte Count */

sys/dev/disk/sym/sym_defs.h

516

/*c9*/ u8 nc_rbc1;

sys/dev/disk/sym/sym_defs.h

517

/*ca*/ u8 nc_rbc2;

sys/dev/disk/sym/sym_defs.h

518

/*cb*/ u8 nc_rbc3;

sys/dev/disk/sym/sym_defs.h

520

/*cc*/ u8 nc_ua; /* Updated Address */

sys/dev/disk/sym/sym_defs.h

521

/*cd*/ u8 nc_ua1;

sys/dev/disk/sym/sym_defs.h

522

/*ce*/ u8 nc_ua2;

sys/dev/disk/sym/sym_defs.h

523

/*cf*/ u8 nc_ua3;

sys/dev/disk/sym/sym_defs.h

525

/*d4*/ u8 nc_ia; /* Instruction Address */

sys/dev/disk/sym/sym_defs.h

526

/*d5*/ u8 nc_ia1;

sys/dev/disk/sym/sym_defs.h

527

/*d6*/ u8 nc_ia2;

sys/dev/disk/sym/sym_defs.h

528

/*d7*/ u8 nc_ia3;

sys/dev/disk/sym/sym_defs.h

533

/*e2*/ u8 nc_crccntl0; /* CRC control register */

sys/dev/disk/sym/sym_defs.h

535

/*e3*/ u8 nc_crccntl1; /* CRC control register */

sys/dev/disk/sym/sym_hipd.c

1059

u8 scsi_version;

sys/dev/disk/sym/sym_hipd.c

1060

u8 spi_version;

sys/dev/disk/sym/sym_hipd.c

1061

u8 period;

sys/dev/disk/sym/sym_hipd.c

1062

u8 offset;

sys/dev/disk/sym/sym_hipd.c

1063

u8 width;

sys/dev/disk/sym/sym_hipd.c

1064

u8 options; /* PPR options */

sys/dev/disk/sym/sym_hipd.c

1345

u8 status[4];

sys/dev/disk/sym/sym_hipd.c

1399

u8 cdb_buf[16]; /* Copy of CDB */

sys/dev/disk/sym/sym_hipd.c

1400

u8 *sns_bbuf; /* Bounce buffer for sense data */

sys/dev/drm/amd/amdgpu/amdgpu.h

1036

u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];

sys/dev/drm/amd/amdgpu/amdgpu.h

1279

u8 perf_req, bool advertise);

sys/dev/drm/amd/amdgpu/amdgpu.h

639

u8 *bios, u32 length_bytes);

sys/dev/drm/amd/amdgpu/amdgpu_acpi.c

616

u8 perf_req, bool advertise)

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

91

u8 i;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1013

u8 clock_type,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1020

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1109

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1177

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

119

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1205

int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1210

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1256

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1286

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1416

u8 voltage_type, u8 voltage_mode)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1420

u8 *start = (u8*)v3;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1433

u8 voltage_type,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1434

u8 *svd_gpio_id, u8 *svc_gpio_id)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1437

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1478

u8 voltage_type, u8 voltage_mode)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1481

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1513

u8 voltage_type, u8 voltage_mode,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1517

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

154

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1548

((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1584

u8 module_index,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1588

u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1609

((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

161

u8 id)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1612

((u8 *)reg_block + (2 * sizeof(u16)) +

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1615

num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1625

(u8)(format->ucPreRegDataLength);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1628

((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1633

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1652

((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1677

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1758

void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1763

u8 align_num_bytes = ALIGN(num_bytes, 4);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

191

((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

270

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

297

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

41

u8 index)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

431

u8 *num_dst_objs = (u8 *)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

432

((u8 *)router_src_dst_table + 1 +

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

773

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

800

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

929

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

941

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

947

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

963

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

969

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

990

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

109

u8 pre_reg_data;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

113

u8 last;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

114

u8 num_entries;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

137

u8 id);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

158

u8 clock_type,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

185

u8 voltage_type, u8 voltage_mode);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

188

u8 voltage_type, u8 voltage_mode,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

192

u8 module_index,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

202

void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

203

int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

211

u8 voltage_type,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

212

u8 *svd_gpio_id, u8 *svc_gpio_id);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

86

u8 mem_vendor;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

87

u8 mem_type;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

94

u8 num_entries;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

95

u8 rsv[3];

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

135

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

203

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

204

u8 mem_type;

sys/dev/drm/amd/amdgpu/amdgpu_bios.c

154

u8 header[AMD_VBIOS_SIGNATURE_END+1] = {0};

sys/dev/drm/amd/amdgpu/amdgpu_display.c

443

u8 out = 0x0;

sys/dev/drm/amd/amdgpu/amdgpu_display.c

444

u8 buf[8];

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

300

((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

313

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

345

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

473

((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

523

((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

568

((u8 *)&array->entries[0] +

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

577

((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

584

((u8 *)&array->entries[0] +

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

595

((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

622

((u8 *)&array->entries[0] +

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

631

((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

658

((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

716

((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

721

u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

825

u8 frev, crev;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

975

u8 amdgpu_encode_pci_lane_width(u32 lanes)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

977

u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 };

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

154

u8 count;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

165

u8 count;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

170

u8 ppm_design;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

225

u8 t_hyst;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

228

u8 control_mode;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

428

u8 fan_pulses_per_revolution;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

429

u8 fan_min_rpm;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

430

u8 fan_max_rpm;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.h

503

u8 amdgpu_encode_pci_lane_width(u32 lanes);

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

85

u8 *save_restore_list_cntl;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

86

u8 *save_restore_list_gpm;

sys/dev/drm/amd/amdgpu/amdgpu_gfx.h

87

u8 *save_restore_list_srm;

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

285

u8 slave_addr,

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

286

u8 addr,

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

287

u8 *val)

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

289

u8 out_buf[2];

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

290

u8 in_buf[2];

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

319

u8 slave_addr,

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

320

u8 addr,

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

321

u8 val)

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

343

u8 val;

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

372

u8 val;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

252

u8 status_bits;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

253

u8 category_code;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

272

u8 level);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

274

u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

354

u8 bl_level; /* saved backlight level */

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

405

u8 h_border;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

406

u8 v_border;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

483

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

484

u8 dp_sink_type;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

492

u8 id;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

500

u8 plugged_state;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

507

u8 i2c_addr;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

510

u8 ddc_mux_type;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

511

u8 ddc_mux_control_pin;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

512

u8 ddc_mux_state;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

515

u8 cd_mux_type;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

516

u8 cd_mux_control_pin;

sys/dev/drm/amd/amdgpu/amdgpu_mode.h

517

u8 cd_mux_state;

sys/dev/drm/amd/amdgpu/amdgpu_trace.h

50

trace_amdgpu_ttm_bo_move(struct amdgpu_bo *bo, u8 new_memtype, u8 old_memtype)

sys/dev/drm/amd/amdgpu/amdgpu_ttm.c

776

mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

76

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \

sys/dev/drm/amd/amdgpu/amdgpu_virt.h

77

(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

sys/dev/drm/amd/amdgpu/atombios_crtc.c

321

u8 frev, crev;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

474

u8 frev, crev;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

527

u32 freq, u8 clk_type, u8 clk_src)

sys/dev/drm/amd/amdgpu/atombios_crtc.c

529

u8 frev, crev;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

592

u8 frev, crev;

sys/dev/drm/amd/amdgpu/atombios_crtc.h

41

u32 freq, u8 clk_type, u8 clk_src);

sys/dev/drm/amd/amdgpu/atombios_dp.c

132

u8 tx_buf[20];

sys/dev/drm/amd/amdgpu/atombios_dp.c

134

u8 ack, delay = 0;

sys/dev/drm/amd/amdgpu/atombios_dp.c

206

static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/amd/amdgpu/atombios_dp.c

208

u8 train_set[4])

sys/dev/drm/amd/amdgpu/atombios_dp.c

210

u8 v = 0;

sys/dev/drm/amd/amdgpu/atombios_dp.c

211

u8 p = 0;

sys/dev/drm/amd/amdgpu/atombios_dp.c

215

u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);

sys/dev/drm/amd/amdgpu/atombios_dp.c

216

u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

sys/dev/drm/amd/amdgpu/atombios_dp.c

256

const u8 dpcd[DP_DPCD_SIZE],

sys/dev/drm/amd/amdgpu/atombios_dp.c

293

static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/atombios_dp.c

295

u8 ucconfig, u8 lane_num)

sys/dev/drm/amd/amdgpu/atombios_dp.c

311

u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)

sys/dev/drm/amd/amdgpu/atombios_dp.c

323

u8 buf[3];

sys/dev/drm/amd/amdgpu/atombios_dp.c

340

u8 msg[DP_DPCD_SIZE];

sys/dev/drm/amd/amdgpu/atombios_dp.c

367

u8 tmp;

sys/dev/drm/amd/amdgpu/atombios_dp.c

448

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/drm/amd/amdgpu/atombios_dp.c

460

u8 power_state)

sys/dev/drm/amd/amdgpu/atombios_dp.c

485

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/drm/amd/amdgpu/atombios_dp.c

486

u8 train_set[4];

sys/dev/drm/amd/amdgpu/atombios_dp.c

487

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/drm/amd/amdgpu/atombios_dp.c

488

u8 tries;

sys/dev/drm/amd/amdgpu/atombios_dp.c

533

u8 tmp;

sys/dev/drm/amd/amdgpu/atombios_dp.c

58

u8 *send, int send_bytes,

sys/dev/drm/amd/amdgpu/atombios_dp.c

59

u8 *recv, int recv_size,

sys/dev/drm/amd/amdgpu/atombios_dp.c

592

u8 voltage;

sys/dev/drm/amd/amdgpu/atombios_dp.c

60

u8 delay, u8 *ack)

sys/dev/drm/amd/amdgpu/atombios_dp.c

720

u8 tmp;

sys/dev/drm/amd/amdgpu/atombios_dp.h

28

u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector);

sys/dev/drm/amd/amdgpu/atombios_dp.h

38

u8 power_state);

sys/dev/drm/amd/amdgpu/atombios_encoders.c

122

static u8 amdgpu_atombios_encoder_backlight_level(struct backlight_device *bd)

sys/dev/drm/amd/amdgpu/atombios_encoders.c

124

u8 level;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

1304

u8 frev, crev;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2145

u8 *record;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2149

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/drm/amd/amdgpu/atombios_encoders.c

215

u8 backlight_level;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2153

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2175

memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],

sys/dev/drm/amd/amdgpu/atombios_encoders.c

38

u8

sys/dev/drm/amd/amdgpu/atombios_encoders.c

41

u8 backlight_level;

sys/dev/drm/amd/amdgpu/atombios_encoders.c

418

static u8 amdgpu_atombios_encoder_get_bpc(struct drm_encoder *encoder)

sys/dev/drm/amd/amdgpu/atombios_encoders.c

54

u8 backlight_level)

sys/dev/drm/amd/amdgpu/atombios_encoders.c

67

u8

sys/dev/drm/amd/amdgpu/atombios_encoders.c

81

u8 level)

sys/dev/drm/amd/amdgpu/atombios_encoders.h

27

u8

sys/dev/drm/amd/amdgpu/atombios_encoders.h

31

u8 backlight_level);

sys/dev/drm/amd/amdgpu/atombios_encoders.h

32

u8

sys/dev/drm/amd/amdgpu/atombios_encoders.h

36

u8 level);

sys/dev/drm/amd/amdgpu/atombios_i2c.c

118

u8 flags;

sys/dev/drm/amd/amdgpu/atombios_i2c.c

167

void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device* adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)

sys/dev/drm/amd/amdgpu/atombios_i2c.c

39

u8 slave_addr, u8 flags,

sys/dev/drm/amd/amdgpu/atombios_i2c.c

40

u8 *buf, u8 num)

sys/dev/drm/amd/amdgpu/atombios_i2c.h

31

u8 slave_addr, u8 line_number, u8 offset, u8 data);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1161

(u8 *)(&fan_table),

sys/dev/drm/amd/amdgpu/ci_dpm.c

1482

(u8 *)&low_sclk_interrupt_t,

sys/dev/drm/amd/amdgpu/ci_dpm.c

193

static u8 ci_get_memory_module_index(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/ci_dpm.c

195

return (u8) ((RREG32(mmBIOS_SCRATCH_4) >> 16) & 0xff);

sys/dev/drm/amd/amdgpu/ci_dpm.c

253

static u8 ci_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/amd/amdgpu/ci_dpm.c

255

u8 mc_para_index;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2591

static u8 ci_get_sleep_divider_id_from_clock(u32 sclk, u32 min_sclk_in_sr)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2606

return (u8)i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

262

mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

266

static u8 ci_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2677

arb_regs->McArbBurstTime = (u8)burst_time;

sys/dev/drm/amd/amdgpu/ci_dpm.c

268

u8 mc_para_index;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2705

(u8 *)&arb_regs,

sys/dev/drm/amd/amdgpu/ci_dpm.c

276

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2771

(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2779

pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2809

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2817

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

283

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2850

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2867

table->AcpLevelCount = (u8)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2883

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2915

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3160

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3290

state->VddcOffsetVid = (u8)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3354

sclk->SclkDid = (u8)dividers.post_divider;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3447

pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3452

(u8 *)levels, level_array_size,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3499

pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3507

(u8 *)levels, level_array_size,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3839

(u8 *)&table->SystemFlags,

sys/dev/drm/amd/amdgpu/ci_dpm.c

393

static u8 ci_convert_to_vid(u16 vddc)

sys/dev/drm/amd/amdgpu/ci_dpm.c

401

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

402

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

403

u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4250

static u8 ci_get_vce_boot_level(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4252

u8 i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

430

u8 *vid = pi->smc_powertune_table.VddCVid;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4493

u8 i, j, k;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4631

u8 i, j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4659

u8 i, j;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4686

u8 i, k;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4778

u8 module_index = ci_get_memory_module_index(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4848

mc_reg_table->last = (u8)i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4913

(u8 *)&pi->smc_mc_reg_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4932

(u8 *)&pi->smc_mc_reg_table.data[0],

sys/dev/drm/amd/amdgpu/ci_dpm.c

5043

u8 request;

sys/dev/drm/amd/amdgpu/ci_dpm.c

508

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

509

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

531

pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/drm/amd/amdgpu/ci_dpm.c

532

pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5559

u8 table_rev)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5661

u8 frev, crev;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5662

u8 *power_state_offset;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5687

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5689

u8 *idx;

sys/dev/drm/amd/amdgpu/ci_dpm.c

569

dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5704

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/amd/amdgpu/ci_dpm.c

571

(u8)(pi->thermal_temp_setting.temperature_high / 1000);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5712

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/amd/amdgpu/ci_dpm.c

5746

u8 frev, crev;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5839

u8 frev, crev;

sys/dev/drm/amd/amdgpu/ci_dpm.c

640

(u8 *)&pi->smc_powertune_table,

sys/dev/drm/amd/amdgpu/ci_dpm.h

177

u8 svi_load_line_en;

sys/dev/drm/amd/amdgpu/ci_dpm.h

178

u8 svi_load_line_vddc;

sys/dev/drm/amd/amdgpu/ci_dpm.h

179

u8 tdc_vddc_throttle_release_limit_perc;

sys/dev/drm/amd/amdgpu/ci_dpm.h

180

u8 tdc_mawt;

sys/dev/drm/amd/amdgpu/ci_dpm.h

181

u8 tdc_waterfall_ctl;

sys/dev/drm/amd/amdgpu/ci_dpm.h

182

u8 dte_ambient_temp_base;

sys/dev/drm/amd/amdgpu/ci_dpm.h

334

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/amd/amdgpu/ci_dpm.h

83

u8 last;

sys/dev/drm/amd/amdgpu/ci_dpm.h

84

u8 num_entries;

sys/dev/drm/amd/amdgpu/ci_smc.c

135

static u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };

sys/dev/drm/amd/amdgpu/ci_smc.c

214

const u8 *src;

sys/dev/drm/amd/amdgpu/ci_smc.c

226

src = (const u8 *)

sys/dev/drm/amd/amdgpu/ci_smc.c

52

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/amd/amdgpu/cik.c

936

u8 *bios, u32 length_bytes)

sys/dev/drm/amd/amdgpu/cik_sdma.c

1176

u8 instance_id, queue_id;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1263

u8 *sadb = NULL;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1356

u8 stereo_freqs = 0;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1551

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2892

u8 bl_level = amdgpu_display_backlight_get_level(adev,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1289

u8 *sadb = NULL;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1382

u8 stereo_freqs = 0;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1593

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3025

u8 bl_level = amdgpu_display_backlight_get_level(adev,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1216

u8 *sadb = NULL;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1309

u8 stereo_freqs = 0;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1498

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2787

u8 bl_level = amdgpu_display_backlight_get_level(adev,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4940

u8 me_id, pipe_id;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6716

u8 me_id, pipe_id, queue_id;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4673

u8 me_id, pipe_id, queue_id;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

524

adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

528

adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

532

adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1001

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1009

(u8 *)&pi->vce_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1010

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1020

(u8 *)&pi->vce_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1021

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1029

(u8 *)&pi->vce_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1058

(u8)kv_get_clk_bypass(adev, table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1064

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1072

(u8 *)&pi->samu_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1073

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1083

(u8 *)&pi->samu_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1084

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1092

(u8 *)&pi->samu_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1123

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1131

(u8 *)&pi->acp_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1132

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1142

(u8 *)&pi->acp_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1143

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1151

(u8 *)&pi->acp_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1410

(u8 *)&value, sizeof(u16), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1443

(u8 *)&pi->fps_high_t,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1452

(u8 *)&pi->fps_low_t,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1518

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1530

static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1532

u8 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1562

(u8 *)&pi->vce_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1563

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1596

(u8 *)&pi->samu_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1597

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1611

static u8 kv_get_acp_boot_level(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1613

u8 i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1631

u8 acp_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1660

(u8 *)&pi->acp_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1661

sizeof(u8),

sys/dev/drm/amd/amdgpu/kv_dpm.c

1840

u8 clk_bypass_cntl;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1851

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2148

static u8 kv_get_sleep_divider_id_from_clock(struct amdgpu_device *adev,

sys/dev/drm/amd/amdgpu/kv_dpm.c

2168

return (u8)i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2565

u8 frev, crev;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2656

u8 table_rev)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2715

u8 frev, crev;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2716

u8 *power_state_offset;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2741

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2743

u8 *idx;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2755

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/amd/amdgpu/kv_dpm.c

2763

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/amd/amdgpu/kv_dpm.c

617

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

633

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

647

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

674

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

702

pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;

sys/dev/drm/amd/amdgpu/kv_dpm.c

793

(u8 *)&low_sclk_interrupt_t,

sys/dev/drm/amd/amdgpu/kv_dpm.c

812

pi->graphics_boot_level = (u8)i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

826

pi->graphics_boot_level = (u8)i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

843

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

856

(u8 *)&pi->graphics_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

867

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

925

(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

927

(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

933

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

939

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

947

(u8 *)&pi->uvd_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

948

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

958

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

965

(u8 *)&pi->uvd_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

995

(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);

sys/dev/drm/amd/amdgpu/kv_dpm.h

100

u8 ss_divider_index;

sys/dev/drm/amd/amdgpu/kv_dpm.h

101

u8 allow_gnb_slow;

sys/dev/drm/amd/amdgpu/kv_dpm.h

102

u8 force_nbp_state;

sys/dev/drm/amd/amdgpu/kv_dpm.h

103

u8 display_wm;

sys/dev/drm/amd/amdgpu/kv_dpm.h

104

u8 vce_wm;

sys/dev/drm/amd/amdgpu/kv_dpm.h

111

u8 dpm0_pg_nb_ps_lo;

sys/dev/drm/amd/amdgpu/kv_dpm.h

112

u8 dpm0_pg_nb_ps_hi;

sys/dev/drm/amd/amdgpu/kv_dpm.h

113

u8 dpmx_nb_ps_lo;

sys/dev/drm/amd/amdgpu/kv_dpm.h

114

u8 dpmx_nb_ps_hi;

sys/dev/drm/amd/amdgpu/kv_dpm.h

125

u8 htc_tmp_lmt;

sys/dev/drm/amd/amdgpu/kv_dpm.h

126

u8 htc_hyst_lmt;

sys/dev/drm/amd/amdgpu/kv_dpm.h

151

u8 graphics_dpm_level_count;

sys/dev/drm/amd/amdgpu/kv_dpm.h

152

u8 uvd_level_count;

sys/dev/drm/amd/amdgpu/kv_dpm.h

153

u8 vce_level_count;

sys/dev/drm/amd/amdgpu/kv_dpm.h

154

u8 acp_level_count;

sys/dev/drm/amd/amdgpu/kv_dpm.h

155

u8 samu_level_count;

sys/dev/drm/amd/amdgpu/kv_dpm.h

163

u8 uvd_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.h

164

u8 vce_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.h

165

u8 acp_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.h

166

u8 samu_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.h

167

u8 uvd_interval;

sys/dev/drm/amd/amdgpu/kv_dpm.h

168

u8 vce_interval;

sys/dev/drm/amd/amdgpu/kv_dpm.h

169

u8 acp_interval;

sys/dev/drm/amd/amdgpu/kv_dpm.h

170

u8 samu_interval;

sys/dev/drm/amd/amdgpu/kv_dpm.h

171

u8 graphics_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.h

172

u8 graphics_interval;

sys/dev/drm/amd/amdgpu/kv_dpm.h

173

u8 graphics_therm_throttle_enable;

sys/dev/drm/amd/amdgpu/kv_dpm.h

174

u8 graphics_voltage_change_enable;

sys/dev/drm/amd/amdgpu/kv_dpm.h

175

u8 graphics_clk_slow_enable;

sys/dev/drm/amd/amdgpu/kv_dpm.h

176

u8 graphics_clk_slow_divider;

sys/dev/drm/amd/amdgpu/kv_dpm.h

177

u8 fps_low_t;

sys/dev/drm/amd/amdgpu/kv_dpm.h

227

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/amd/amdgpu/kv_dpm.h

98

u8 vddc_index;

sys/dev/drm/amd/amdgpu/kv_dpm.h

99

u8 ds_divider_index;

sys/dev/drm/amd/amdgpu/kv_smc.c

124

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/amd/amdgpu/mxgpu_ai.c

82

u8 reg;

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1068

u8 instance_id, queue_id;

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1403

u8 instance_id, queue_id;

sys/dev/drm/amd/amdgpu/si_dpm.c

2283

(u8 *)(&(smc_table->dpm2Params.TDPLimit)),

sys/dev/drm/amd/amdgpu/si_dpm.c

2300

(u8 *)papm_parm,

sys/dev/drm/amd/amdgpu/si_dpm.c

2332

(u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),

sys/dev/drm/amd/amdgpu/si_dpm.c

2398

u8 max_ps_percent;

sys/dev/drm/amd/amdgpu/si_dpm.c

2466

smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

sys/dev/drm/amd/amdgpu/si_dpm.c

2570

u8 tdep_count;

sys/dev/drm/amd/amdgpu/si_dpm.c

2622

(u8 *)dte_tables,

sys/dev/drm/amd/amdgpu/si_dpm.c

2815

(u8 *)cac_tables,

sys/dev/drm/amd/amdgpu/si_dpm.c

3003

(u8 *)spll_table,

sys/dev/drm/amd/amdgpu/si_dpm.c

3392

static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)

sys/dev/drm/amd/amdgpu/si_dpm.c

3394

return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);

sys/dev/drm/amd/amdgpu/si_dpm.c

4289

static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/amd/amdgpu/si_dpm.c

4291

u8 mc_para_index;

sys/dev/drm/amd/amdgpu/si_dpm.c

4298

mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);

sys/dev/drm/amd/amdgpu/si_dpm.c

4302

static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/drm/amd/amdgpu/si_dpm.c

4304

u8 mc_para_index;

sys/dev/drm/amd/amdgpu/si_dpm.c

4312

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/drm/amd/amdgpu/si_dpm.c

4319

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/drm/amd/amdgpu/si_dpm.c

4324

static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)

sys/dev/drm/amd/amdgpu/si_dpm.c

4328

u8 result = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

4515

u8 i;

sys/dev/drm/amd/amdgpu/si_dpm.c

4580

voltage->index = (u8)i;

sys/dev/drm/amd/amdgpu/si_dpm.c

4602

voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;

sys/dev/drm/amd/amdgpu/si_dpm.c

4661

u16 value, u8 index,

sys/dev/drm/amd/amdgpu/si_dpm.c

4684

smc_voltage->phase_settings = (u8)i;

sys/dev/drm/amd/amdgpu/si_dpm.c

4765

(u8)si_calculate_memory_refresh_rate(adev, pl->sclk);

sys/dev/drm/amd/amdgpu/si_dpm.c

4777

arb_regs->mc_arb_burst_time = (u8)burst_time;

sys/dev/drm/amd/amdgpu/si_dpm.c

4799

(u8 *)&arb_regs,

sys/dev/drm/amd/amdgpu/si_dpm.c

4918

table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;

sys/dev/drm/amd/amdgpu/si_dpm.c

5012

(u8)amdgpu_get_pcie_gen_support(adev,

sys/dev/drm/amd/amdgpu/si_dpm.c

5112

state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);

sys/dev/drm/amd/amdgpu/si_dpm.c

5142

(u8 *)&arb_regs,

sys/dev/drm/amd/amdgpu/si_dpm.c

5239

(u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

sys/dev/drm/amd/amdgpu/si_dpm.c

5452

level->gen2PCIE = (u8)si_pi->force_pcie_gen;

sys/dev/drm/amd/amdgpu/si_dpm.c

5454

level->gen2PCIE = (u8)pl->pcie_gen;

sys/dev/drm/amd/amdgpu/si_dpm.c

5692

(u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);

sys/dev/drm/amd/amdgpu/si_dpm.c

5749

return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

sys/dev/drm/amd/amdgpu/si_dpm.c

5769

ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,

sys/dev/drm/amd/amdgpu/si_dpm.c

5818

u8 i, j, k;

sys/dev/drm/amd/amdgpu/si_dpm.c

5936

u8 i, j;

sys/dev/drm/amd/amdgpu/si_dpm.c

5962

u8 i, j;

sys/dev/drm/amd/amdgpu/si_dpm.c

5991

u8 module_index = rv770_get_memory_module_index(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

6053

mc_reg_table->last = (u8)i;

sys/dev/drm/amd/amdgpu/si_dpm.c

6138

(u8 *)smc_mc_reg_table,

sys/dev/drm/amd/amdgpu/si_dpm.c

6157

(u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

sys/dev/drm/amd/amdgpu/si_dpm.c

6239

u8 request;

sys/dev/drm/amd/amdgpu/si_dpm.c

6519

(u8 *)(&fan_table),

sys/dev/drm/amd/amdgpu/si_dpm.c

7106

u8 table_rev)

sys/dev/drm/amd/amdgpu/si_dpm.c

7223

u8 frev, crev;

sys/dev/drm/amd/amdgpu/si_dpm.c

7224

u8 *power_state_offset;

sys/dev/drm/amd/amdgpu/si_dpm.c

7249

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/amd/amdgpu/si_dpm.c

7251

u8 *idx;

sys/dev/drm/amd/amdgpu/si_dpm.c

7266

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/amd/amdgpu/si_dpm.c

7274

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/amd/amdgpu/si_dpm.h

1006

u8 svd_gpio_id;

sys/dev/drm/amd/amdgpu/si_dpm.h

1007

u8 svc_gpio_id;

sys/dev/drm/amd/amdgpu/si_dpm.h

275

u8 last;

sys/dev/drm/amd/amdgpu/si_dpm.h

276

u8 num_entries;

sys/dev/drm/amd/amdgpu/si_dpm.h

490

u8 vddc_index;

sys/dev/drm/amd/amdgpu/si_dpm.h

491

u8 high_smio;

sys/dev/drm/amd/amdgpu/si_dpm.h

563

u8 valid_vddc_entries;

sys/dev/drm/amd/amdgpu/si_dpm.h

566

u8 odt_value_0[2];

sys/dev/drm/amd/amdgpu/si_dpm.h

567

u8 odt_value_1[2];

sys/dev/drm/amd/amdgpu/si_dpm.h

621

u8 last;

sys/dev/drm/amd/amdgpu/si_dpm.h

622

u8 num_entries;

sys/dev/drm/amd/amdgpu/si_dpm.h

637

u8 mc_wr_weight;

sys/dev/drm/amd/amdgpu/si_dpm.h

638

u8 mc_rd_weight;

sys/dev/drm/amd/amdgpu/si_dpm.h

639

u8 allow_ovrflw;

sys/dev/drm/amd/amdgpu/si_dpm.h

640

u8 num_win_tdp;

sys/dev/drm/amd/amdgpu/si_dpm.h

641

u8 l2num_win_tdp;

sys/dev/drm/amd/amdgpu/si_dpm.h

642

u8 lts_truncate_n;

sys/dev/drm/amd/amdgpu/si_dpm.h

664

u8 mvdd_high_index;

sys/dev/drm/amd/amdgpu/si_dpm.h

665

u8 mvdd_low_index;

sys/dev/drm/amd/amdgpu/si_dpm.h

843

u8 lta_window_size;

sys/dev/drm/amd/amdgpu/si_dpm.h

844

u8 lts_truncate;

sys/dev/drm/amd/amdgpu/si_dpm.h

865

u8 lts_truncate_default;

sys/dev/drm/amd/amdgpu/si_dpm.h

866

u8 shift_n_default;

sys/dev/drm/amd/amdgpu/si_dpm.h

867

u8 operating_temp;

sys/dev/drm/amd/amdgpu/si_dpm.h

871

u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/drm/amd/amdgpu/si_dpm.h

881

u8 lts_truncate;

sys/dev/drm/amd/amdgpu/si_dpm.h

882

u8 shift_n;

sys/dev/drm/amd/amdgpu/si_dpm.h

883

u8 dc_pwr_value;

sys/dev/drm/amd/amdgpu/si_dpm.h

894

u8 window_size;

sys/dev/drm/amd/amdgpu/si_dpm.h

895

u8 temp_select;

sys/dev/drm/amd/amdgpu/si_dpm.h

896

u8 dte_mode;

sys/dev/drm/amd/amdgpu/si_dpm.h

897

u8 tdep_count;

sys/dev/drm/amd/amdgpu/si_dpm.h

898

u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/drm/amd/amdgpu/si_dpm.h

929

u8 last;

sys/dev/drm/amd/amdgpu/si_dpm.h

930

u8 num_entries;

sys/dev/drm/amd/amdgpu/sislands_smc.h

408

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/amd/amdgpu/soc15.c

243

u8 *bios, u32 length_bytes)

sys/dev/drm/amd/amdgpu/vi.c

420

u8 *bios, u32 length_bytes)

sys/dev/drm/amd/include/amd_acpi.h

40

u8 command_code; /* notify command code */

sys/dev/drm/amd/include/amd_acpi.h

46

u8 panel_exp_mode; /* panel expansion mode */

sys/dev/drm/amd/include/amd_acpi.h

47

u8 thermal_gfx; /* thermal state: target gfx controller */

sys/dev/drm/amd/include/amd_acpi.h

48

u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */

sys/dev/drm/amd/include/amd_acpi.h

49

u8 forced_power_gfx; /* forced power state: target gfx controller */

sys/dev/drm/amd/include/amd_acpi.h

50

u8 forced_power_state; /* forced power state: state id */

sys/dev/drm/amd/include/amd_acpi.h

51

u8 system_power_src; /* system power source */

sys/dev/drm/amd/include/amd_acpi.h

52

u8 backlight_level; /* panel backlight level (0-255) */

sys/dev/drm/amd/include/amd_acpi.h

73

u8 req_type; /* request type */

sys/dev/drm/amd/include/amd_acpi.h

74

u8 perf_req; /* performance request */

sys/dev/drm/amd/include/amd_acpi.h

79

u8 ret_val; /* return value */

sys/dev/drm/amd/include/kgd_pp_interface.h

36

u8 clk_idx;

sys/dev/drm/amd/include/kgd_pp_interface.h

37

u8 pstate;

sys/dev/drm/amd/include/linux/chash.h

137

prefix.values = (u8 *)&data \

sys/dev/drm/amd/include/linux/chash.h

169

int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,

sys/dev/drm/amd/include/linux/chash.h

41

u8 bits;

sys/dev/drm/amd/include/linux/chash.h

42

u8 key_size;

sys/dev/drm/amd/include/linux/chash.h

50

u8 *values;

sys/dev/drm/amd/lib/chash.c

40

int chash_table_alloc(struct chash_table *table, u8 bits, u8 key_size,

sys/dev/drm/amd/lib/chash.c

463

static int __init chash_self_test(u8 bits, u8 key_size,

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1169

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1201

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1365

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

141

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

205

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

485

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

605

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

107

u8 ucSclkPostDiv;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

108

u8 ucSclkVcoMode;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

109

u8 ucSclkPllRange;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.h

110

u8 ucSscEnable;

sys/dev/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

139

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/vega10_processpptables.c

51

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/vega12_processpptables.c

49

u8 frev, crev;

sys/dev/drm/amd/powerplay/hwmgr/vega20_processpptables.c

49

u8 frev, crev;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

499

smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

504

(u8 *)levels, array_size,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

624

u8 *hi_vid = smu_data->power_tune_table.BapmVddCVidHiSidd;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

625

u8 *lo_vid = smu_data->power_tune_table.BapmVddCVidLoSidd;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

647

smu_data->power_tune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

648

smu_data->power_tune_table.GnbLPMLMinVid = (u8)min;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

36

u8 svi_load_line_en;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

37

u8 svi_load_line_vddc;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

38

u8 tdc_vddc_throttle_release_limit_perc;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

39

u8 tdc_mawt;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

40

u8 tdc_waterfall_ctl;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.h

41

u8 dte_ambient_temp_base;

sys/dev/drm/drm_dp_dual_mode_helper.c

103

u8 offset, const void *buffer, size_t size)

sys/dev/drm/drm_dp_dual_mode_helper.c

436

u8 data;

sys/dev/drm/drm_dp_dual_mode_helper.c

482

u8 data = 0;

sys/dev/drm/drm_dp_dual_mode_helper.c

61

u8 offset, void *buffer, size_t size)

sys/dev/drm/drm_dp_helper.c

102

u8 l = dp_link_status(link_status, i);

sys/dev/drm/drm_dp_helper.c

1033

static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)

sys/dev/drm/drm_dp_helper.c

1035

u8 buf, count;

sys/dev/drm/drm_dp_helper.c

1070

u8 crc_bytes[6];

sys/dev/drm/drm_dp_helper.c

108

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/drm_dp_helper.c

115

u8 l = dp_link_status(link_status, i);

sys/dev/drm/drm_dp_helper.c

1187

int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])

sys/dev/drm/drm_dp_helper.c

121

void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

sys/dev/drm/drm_dp_helper.c

1219

u8 buf;

sys/dev/drm/drm_dp_helper.c

1246

u8 buf;

sys/dev/drm/drm_dp_helper.c

1265

u8 oui[3];

sys/dev/drm/drm_dp_helper.c

1266

u8 device_id[6];

sys/dev/drm/drm_dp_helper.c

1300

u8 any_device[] = DEVICE_ID_ANY;

sys/dev/drm/drm_dp_helper.c

136

void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {

sys/dev/drm/drm_dp_helper.c

151

u8 drm_dp_link_rate_to_bw_code(int link_rate)

sys/dev/drm/drm_dp_helper.c

169

int drm_dp_bw_code_to_link_rate(u8 link_bw)

sys/dev/drm/drm_dp_helper.c

192

u8 request, uint offset, void *buffer, int ret)

sys/dev/drm/drm_dp_helper.c

218

static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,

sys/dev/drm/drm_dp_helper.c

355

u8 status[DP_LINK_STATUS_SIZE])

sys/dev/drm/drm_dp_helper.c

375

u8 values[3];

sys/dev/drm/drm_dp_helper.c

404

u8 value;

sys/dev/drm/drm_dp_helper.c

442

u8 value;

sys/dev/drm/drm_dp_helper.c

46

static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)

sys/dev/drm/drm_dp_helper.c

473

u8 values[2];

sys/dev/drm/drm_dp_helper.c

500

int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/drm/drm_dp_helper.c

501

const u8 port_cap[4])

sys/dev/drm/drm_dp_helper.c

51

static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/drm_dp_helper.c

531

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/drm/drm_dp_helper.c

532

const u8 port_cap[4])

sys/dev/drm/drm_dp_helper.c

56

u8 l = dp_link_status(link_status, i);

sys/dev/drm/drm_dp_helper.c

587

const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/drm/drm_dp_helper.c

588

const u8 port_cap[4], struct drm_dp_aux *aux)

sys/dev/drm/drm_dp_helper.c

60

bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/drm_dp_helper.c

63

u8 lane_align;

sys/dev/drm/drm_dp_helper.c

64

u8 lane_status;

sys/dev/drm/drm_dp_helper.c

80

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/drm_dp_helper.c

84

u8 lane_status;

sys/dev/drm/drm_dp_helper.c

95

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/drm_dp_mst_topology.c

1033

static struct drm_dp_mst_port *drm_dp_get_port(struct drm_dp_mst_branch *mstb, u8 port_num)

sys/dev/drm/drm_dp_mst_topology.c

104

static u8 drm_dp_msg_data_crc4(const uint8_t *data, u8 number_of_bytes)

sys/dev/drm/drm_dp_mst_topology.c

1052

static u8 drm_dp_calculate_rad(struct drm_dp_mst_port *port,

sys/dev/drm/drm_dp_mst_topology.c

1053

u8 *rad)

sys/dev/drm/drm_dp_mst_topology.c

106

u8 bitmask = 0x80;

sys/dev/drm/drm_dp_mst_topology.c

107

u8 bitshift = 7;

sys/dev/drm/drm_dp_mst_topology.c

1074

u8 rad[6], lct;

sys/dev/drm/drm_dp_mst_topology.c

108

u8 array_index = 0;

sys/dev/drm/drm_dp_mst_topology.c

1097

static void drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)

sys/dev/drm/drm_dp_mst_topology.c

1268

u8 lct, u8 *rad)

sys/dev/drm/drm_dp_mst_topology.c

137

static inline u8 drm_dp_calc_sb_hdr_size(struct drm_dp_sideband_msg_hdr *hdr)

sys/dev/drm/drm_dp_mst_topology.c

139

u8 size = 3;

sys/dev/drm/drm_dp_mst_topology.c

1391

u8 *guid)

sys/dev/drm/drm_dp_mst_topology.c

1407

static int build_dpcd_read(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes)

sys/dev/drm/drm_dp_mst_topology.c

1422

bool up, u8 *msg, int len)

sys/dev/drm/drm_dp_mst_topology.c

145

u8 *buf, int *len)

sys/dev/drm/drm_dp_mst_topology.c

1457

u8 req_type;

sys/dev/drm/drm_dp_mst_topology.c

149

u8 crc4;

sys/dev/drm/drm_dp_mst_topology.c

1496

u8 chunk[48];

sys/dev/drm/drm_dp_mst_topology.c

164

u8 *buf, int buflen, u8 *hdrlen)

sys/dev/drm/drm_dp_mst_topology.c

166

u8 crc4;

sys/dev/drm/drm_dp_mst_topology.c

167

u8 len;

sys/dev/drm/drm_dp_mst_topology.c

169

u8 idx;

sys/dev/drm/drm_dp_mst_topology.c

1725

u8 sinks[DRM_DP_MAX_SDP_STREAMS];

sys/dev/drm/drm_dp_mst_topology.c

2008

int offset, int size, u8 *bytes)

sys/dev/drm/drm_dp_mst_topology.c

2043

static int drm_dp_encode_up_ack_reply(struct drm_dp_sideband_msg_tx *msg, u8 req_type)

sys/dev/drm/drm_dp_mst_topology.c

205

u8 *buf = raw->msg;

sys/dev/drm/drm_dp_mst_topology.c

2225

u8 guid[16];

sys/dev/drm/drm_dp_mst_topology.c

2264

u8 replyblock[32];

sys/dev/drm/drm_dp_mst_topology.c

2450

int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled)

sys/dev/drm/drm_dp_mst_topology.c

2783

u8 payload_alloc[3], status;

sys/dev/drm/drm_dp_mst_topology.c

2856

u8 status;

sys/dev/drm/drm_dp_mst_topology.c

3050

u8 buf[DP_PAYLOAD_TABLE_SIZE];

sys/dev/drm/drm_dp_mst_topology.c

307

static void drm_dp_crc_sideband_chunk_req(u8 *msg, u8 len)

sys/dev/drm/drm_dp_mst_topology.c

309

u8 crc4;

sys/dev/drm/drm_dp_mst_topology.c

318

u8 *buf = raw->msg;

sys/dev/drm/drm_dp_mst_topology.c

327

u8 *replybuf, u8 replybuflen, bool hdr)

sys/dev/drm/drm_dp_mst_topology.c

330

u8 crc4;

sys/dev/drm/drm_dp_mst_topology.c

333

u8 hdrlen;

sys/dev/drm/drm_dp_mst_topology.c

364

msg->curchunk_idx = min(msg->curchunk_len, (u8)(replybuflen - hdrlen));

sys/dev/drm/drm_dp_mst_topology.c

56

int offset, int size, u8 *bytes);

sys/dev/drm/drm_dp_mst_topology.c

64

u8 *guid);

sys/dev/drm/drm_dp_mst_topology.c

668

static int build_dpcd_write(struct drm_dp_sideband_msg_tx *msg, u8 port_num, u32 offset, u8 num_bytes, u8 *bytes)

sys/dev/drm/drm_dp_mst_topology.c

70

static u8 drm_dp_msg_header_crc4(const uint8_t *data, size_t num_nibbles)

sys/dev/drm/drm_dp_mst_topology.c

703

u8 vcpi, uint16_t pbn,

sys/dev/drm/drm_dp_mst_topology.c

704

u8 number_sdp_streams,

sys/dev/drm/drm_dp_mst_topology.c

705

u8 *sdp_stream_sink)

sys/dev/drm/drm_dp_mst_topology.c

72

u8 bitmask = 0x80;

sys/dev/drm/drm_dp_mst_topology.c

73

u8 bitshift = 7;

sys/dev/drm/drm_dp_mst_topology.c

74

u8 array_index = 0;

sys/dev/drm/drm_dp_mst_topology.c

76

u8 remainder = 0;

sys/dev/drm/drm_dp_mst_topology.c

840

static struct drm_dp_mst_branch *drm_dp_add_mst_branch_device(u8 lct, u8 *rad)

sys/dev/drm/drm_edid.c

1330

static const u8 edid_header[] = {

sys/dev/drm/drm_edid.c

1342

int drm_edid_header_is_valid(const u8 *raw_edid)

sys/dev/drm/drm_edid.c

1362

static int drm_edid_block_checksum(const u8 *raw_edid)

sys/dev/drm/drm_edid.c

1365

u8 csum = 0;

sys/dev/drm/drm_edid.c

1372

static bool drm_edid_is_zero(const u8 *in_edid, int length)

sys/dev/drm/drm_edid.c

1392

bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,

sys/dev/drm/drm_edid.c

1395

u8 csum;

sys/dev/drm/drm_edid.c

1487

u8 *raw = (u8 *)edid;

sys/dev/drm/drm_edid.c

1513

drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)

sys/dev/drm/drm_edid.c

1565

u8 *edid, int num_blocks)

sys/dev/drm/drm_edid.c

1576

u8 *block = edid + i * EDID_LENGTH;

sys/dev/drm/drm_edid.c

1613

int (*get_edid_block)(void *data, u8 *buf, unsigned int block,

sys/dev/drm/drm_edid.c

1618

u8 *edid, *new;

sys/dev/drm/drm_edid.c

1660

u8 *block = edid + j * EDID_LENGTH;

sys/dev/drm/drm_edid.c

1674

u8 *base;

sys/dev/drm/drm_edid.c

1688

u8 *block = edid + i * EDID_LENGTH;

sys/dev/drm/drm_edid.c

1935

cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)

sys/dev/drm/drm_edid.c

1938

u8 d = ext[0x02];

sys/dev/drm/drm_edid.c

1939

u8 *det_base = ext + d;

sys/dev/drm/drm_edid.c

1947

vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)

sys/dev/drm/drm_edid.c

1950

u8 *det_base = ext + 5;

sys/dev/drm/drm_edid.c

1960

drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)

sys/dev/drm/drm_edid.c

1972

u8 *ext = raw_edid + (i * EDID_LENGTH);

sys/dev/drm/drm_edid.c

1989

u8 *r = (u8 *)t;

sys/dev/drm/drm_edid.c

2001

drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);

sys/dev/drm/drm_edid.c

2011

u8 *r = (u8 *)t;

sys/dev/drm/drm_edid.c

2013

*(u8 **)data = r;

sys/dev/drm/drm_edid.c

2020

u8 *r = NULL;

sys/dev/drm/drm_edid.c

2021

drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);

sys/dev/drm/drm_edid.c

2028

u8 *r = NULL;

sys/dev/drm/drm_edid.c

2029

drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);

sys/dev/drm/drm_edid.c

2036

u8 *r = NULL;

sys/dev/drm/drm_edid.c

2037

drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);

sys/dev/drm/drm_edid.c

2044

u8 *r = NULL;

sys/dev/drm/drm_edid.c

2045

drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);

sys/dev/drm/drm_edid.c

2052

u8 *r = NULL;

sys/dev/drm/drm_edid.c

2053

drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);

sys/dev/drm/drm_edid.c

2078

bad_std_timing(u8 a, u8 b)

sys/dev/drm/drm_edid.c

2358

struct edid *edid, u8 *t)

sys/dev/drm/drm_edid.c

2375

struct edid *edid, u8 *t)

sys/dev/drm/drm_edid.c

2391

range_pixel_clock(struct edid *edid, u8 *t)

sys/dev/drm/drm_edid.c

2410

u8 *t = (u8 *)timing;

sys/dev/drm/drm_edid.c

2590

drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,

sys/dev/drm/drm_edid.c

2601

u8 *est = ((u8 *)timing) + 6;

sys/dev/drm/drm_edid.c

2668

drm_for_each_detailed_block((u8 *)edid,

sys/dev/drm/drm_edid.c

2727

drm_for_each_detailed_block((u8 *)edid, do_standard_modes,

sys/dev/drm/drm_edid.c

2743

const u8 empty[3] = { 0, 0, 0 };

sys/dev/drm/drm_edid.c

2803

drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);

sys/dev/drm/drm_edid.c

2862

drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);

sys/dev/drm/drm_edid.c

2883

static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)

sys/dev/drm/drm_edid.c

2885

u8 *edid_ext = NULL;

sys/dev/drm/drm_edid.c

2894

edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);

sys/dev/drm/drm_edid.c

2905

static u8 *drm_find_cea_extension(const struct edid *edid)

sys/dev/drm/drm_edid.c

2910

static u8 *drm_find_displayid_extension(const struct edid *edid)

sys/dev/drm/drm_edid.c

2941

cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)

sys/dev/drm/drm_edid.c

2975

static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,

sys/dev/drm/drm_edid.c

2979

u8 vic;

sys/dev/drm/drm_edid.c

3015

u8 drm_match_cea_mode(const struct drm_display_mode *to_match)

sys/dev/drm/drm_edid.c

3018

u8 vic;

sys/dev/drm/drm_edid.c

3048

static bool drm_valid_cea_vic(u8 vic)

sys/dev/drm/drm_edid.c

3060

enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)

sys/dev/drm/drm_edid.c

3083

static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,

sys/dev/drm/drm_edid.c

3087

u8 vic;

sys/dev/drm/drm_edid.c

3119

static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)

sys/dev/drm/drm_edid.c

3122

u8 vic;

sys/dev/drm/drm_edid.c

3143

static bool drm_valid_hdmi_vic(u8 vic)

sys/dev/drm/drm_edid.c

3167

u8 vic = drm_match_cea_mode(mode);

sys/dev/drm/drm_edid.c

3220

static u8 svd_to_vic(u8 svd)

sys/dev/drm/drm_edid.c

3231

const u8 *video_db, u8 video_len,

sys/dev/drm/drm_edid.c

3232

u8 video_index)

sys/dev/drm/drm_edid.c

3236

u8 vic;

sys/dev/drm/drm_edid.c

3266

const u8 *svds, u8 svds_len)

sys/dev/drm/drm_edid.c

3274

u8 vic = svd_to_vic(svds[i]);

sys/dev/drm/drm_edid.c

3301

drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)

sys/dev/drm/drm_edid.c

3303

u8 vic = svd_to_vic(svd);

sys/dev/drm/drm_edid.c

3313

do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)

sys/dev/drm/drm_edid.c

3406

static int add_hdmi_mode(struct drm_connector *connector, u8 vic)

sys/dev/drm/drm_edid.c

3426

const u8 *video_db, u8 video_len, u8 video_index)

sys/dev/drm/drm_edid.c

3475

do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,

sys/dev/drm/drm_edid.c

3476

const u8 *video_db, u8 video_len)

sys/dev/drm/drm_edid.c

3480

u8 vic_len, hdmi_3d_len = 0;

sys/dev/drm/drm_edid.c

3518

u8 vic;

sys/dev/drm/drm_edid.c

3612

cea_db_payload_len(const u8 *db)

sys/dev/drm/drm_edid.c

3618

cea_db_extended_tag(const u8 *db)

sys/dev/drm/drm_edid.c

3624

cea_db_tag(const u8 *db)

sys/dev/drm/drm_edid.c

3630

cea_revision(const u8 *cea)

sys/dev/drm/drm_edid.c

3636

cea_db_offsets(const u8 *cea, int *start, int *end)

sys/dev/drm/drm_edid.c

3648

static bool cea_db_is_hdmi_vsdb(const u8 *db)

sys/dev/drm/drm_edid.c

3663

static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)

sys/dev/drm/drm_edid.c

3678

static bool cea_db_is_y420cmdb(const u8 *db)

sys/dev/drm/drm_edid.c

3692

static bool cea_db_is_y420vdb(const u8 *db)

sys/dev/drm/drm_edid.c

3710

const u8 *db)

sys/dev/drm/drm_edid.c

3714

u8 map_len = cea_db_payload_len(db) - 1;

sys/dev/drm/drm_edid.c

3715

u8 count;

sys/dev/drm/drm_edid.c

3752

const u8 *cea = drm_find_cea_extension(edid);

sys/dev/drm/drm_edid.c

3753

const u8 *db, *hdmi = NULL, *video = NULL;

sys/dev/drm/drm_edid.c

3754

u8 dbl, hdmi_len, video_len = 0;

sys/dev/drm/drm_edid.c

3775

const u8 *vdb420 = &db[2];

sys/dev/drm/drm_edid.c

3800

u8 vic;

sys/dev/drm/drm_edid.c

3840

drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)

sys/dev/drm/drm_edid.c

3842

u8 len = cea_db_payload_len(db);

sys/dev/drm/drm_edid.c

3874

*(u8 **)data = t->data.other_data.data.str.str;

sys/dev/drm/drm_edid.c

3885

drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);

sys/dev/drm/drm_edid.c

3940

u8 *cea;

sys/dev/drm/drm_edid.c

3941

u8 *db;

sys/dev/drm/drm_edid.c

4038

u8 *cea;

sys/dev/drm/drm_edid.c

4057

u8 *db = &cea[i];

sys/dev/drm/drm_edid.c

4068

u8 *sad = &db[1 + j * 3];

sys/dev/drm/drm_edid.c

4095

int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)

sys/dev/drm/drm_edid.c

4099

const u8 *cea;

sys/dev/drm/drm_edid.c

4118

const u8 *db = &cea[i];

sys/dev/drm/drm_edid.c

4189

u8 *edid_ext;

sys/dev/drm/drm_edid.c

4227

u8 *edid_ext;

sys/dev/drm/drm_edid.c

4272

u8 *edid_ext;

sys/dev/drm/drm_edid.c

4316

const u8 *db)

sys/dev/drm/drm_edid.c

4318

u8 dc_mask;

sys/dev/drm/drm_edid.c

4326

const u8 *hf_vsdb)

sys/dev/drm/drm_edid.c

4372

const u8 *hdmi)

sys/dev/drm/drm_edid.c

4439

drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)

sys/dev/drm/drm_edid.c

4442

u8 len = cea_db_payload_len(db);

sys/dev/drm/drm_edid.c

4461

const u8 *edid_ext;

sys/dev/drm/drm_edid.c

4481

const u8 *db = &edid_ext[i];

sys/dev/drm/drm_edid.c

4591

static int validate_displayid(u8 *displayid, int length, int idx)

sys/dev/drm/drm_edid.c

4594

u8 csum = 0;

sys/dev/drm/drm_edid.c

4688

u8 *displayid;

sys/dev/drm/drm_edid.c

4911

u8 vendor_if_vic = drm_match_hdmi_mode(mode);

sys/dev/drm/drm_edid.c

5068

u8 vic;

sys/dev/drm/drm_edid.c

5108

u8 tile_v_loc, tile_h_loc;

sys/dev/drm/drm_edid.c

5109

u8 num_v_tile, num_h_tile;

sys/dev/drm/drm_edid.c

5158

u8 *displayid, int length,

sys/dev/drm/drm_edid_load.c

37

static u8 *do_edid_fw_load(struct drm_connector *connector, const char *fwname,

sys/dev/drm/drm_edid_load.c

67

static u8 *

sys/dev/drm/drm_edid_load.c

72

const u8 *fwdata;

sys/dev/drm/drm_edid_load.c

73

u8 *block = NULL, *new = NULL;

sys/dev/drm/drm_fb_helper.c

1658

u8 depth)

sys/dev/drm/drm_mipi_dsi.c

1018

int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format)

sys/dev/drm/drm_mipi_dsi.c

1041

u8 payload[3] = { MIPI_DCS_SET_TEAR_SCANLINE, scanline >> 8,

sys/dev/drm/drm_mipi_dsi.c

1064

u8 payload[2] = { brightness & 0xff, brightness >> 8 };

sys/dev/drm/drm_mipi_dsi.c

375

bool mipi_dsi_packet_format_is_short(u8 type)

sys/dev/drm/drm_mipi_dsi.c

412

bool mipi_dsi_packet_format_is_long(u8 type)

sys/dev/drm/drm_mipi_dsi.c

478

const u8 *tx = msg->tx_buf;

sys/dev/drm/drm_mipi_dsi.c

501

.tx_buf = (u8 [2]) { 0, 0 },

sys/dev/drm/drm_mipi_dsi.c

521

.tx_buf = (u8 [2]) { 0, 0 },

sys/dev/drm/drm_mipi_dsi.c

543

u8 tx[2] = { value & 0xff, value >> 8 };

sys/dev/drm/drm_mipi_dsi.c

701

ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,

sys/dev/drm/drm_mipi_dsi.c

706

u8 *tx;

sys/dev/drm/drm_mipi_dsi.c

741

ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,

sys/dev/drm/drm_mipi_dsi.c

802

int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode)

sys/dev/drm/drm_mipi_dsi.c

827

int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format)

sys/dev/drm/drm_mipi_dsi.c

932

u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff };

sys/dev/drm/drm_mipi_dsi.c

956

u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff };

sys/dev/drm/drm_mipi_dsi.c

998

u8 value = mode;

sys/dev/drm/drm_modes.c

1204

u8 vic = drm_match_cea_mode(mode);

sys/dev/drm/drm_modes.c

1768

u8 vic = drm_match_cea_mode(mode);

sys/dev/drm/drm_modes.c

1788

u8 vic = drm_match_cea_mode(mode);

sys/dev/drm/drm_scdc_helper.c

139

u8 status;

sys/dev/drm/drm_scdc_helper.c

166

u8 config;

sys/dev/drm/drm_scdc_helper.c

221

u8 config;

sys/dev/drm/drm_scdc_helper.c

53

ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,

sys/dev/drm/drm_scdc_helper.c

93

ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,

sys/dev/drm/i915/dvo_ch7017.c

162

u8 dummy;

sys/dev/drm/i915/dvo_ch7017.c

168

static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)

sys/dev/drm/i915/dvo_ch7017.c

187

static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)

sys/dev/drm/i915/dvo_ch7017.c

189

u8 buf[2] = { addr, val };

sys/dev/drm/i915/dvo_ch7017.c

205

u8 val;

sys/dev/drm/i915/dvo_ch7017.c

261

u8 lvds_pll_feedback_div, lvds_pll_vco_control;

sys/dev/drm/i915/dvo_ch7017.c

262

u8 outputs_enable, lvds_control_2, lvds_power_down;

sys/dev/drm/i915/dvo_ch7017.c

263

u8 horizontal_active_pixel_input;

sys/dev/drm/i915/dvo_ch7017.c

264

u8 horizontal_active_pixel_output, vertical_active_line_output;

sys/dev/drm/i915/dvo_ch7017.c

265

u8 active_input_line_output;

sys/dev/drm/i915/dvo_ch7017.c

336

u8 val;

sys/dev/drm/i915/dvo_ch7017.c

364

u8 val;

sys/dev/drm/i915/dvo_ch7017.c

376

u8 val;

sys/dev/drm/i915/dvo_ch7xxx.c

110

static char *ch7xxx_get_id(u8 vid)

sys/dev/drm/i915/dvo_ch7xxx.c

122

static char *ch7xxx_get_did(u8 did)

sys/dev/drm/i915/dvo_ch7xxx.c

135

static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/drm/i915/dvo_ch7xxx.c

139

u8 out_buf[2];

sys/dev/drm/i915/dvo_ch7xxx.c

140

u8 in_buf[2];

sys/dev/drm/i915/dvo_ch7xxx.c

173

static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/drm/i915/dvo_ch7xxx.c

177

u8 out_buf[2];

sys/dev/drm/i915/dvo_ch7xxx.c

204

u8 vendor, device;

sys/dev/drm/i915/dvo_ch7xxx.c

247

u8 cdet, orig_pm, pm;

sys/dev/drm/i915/dvo_ch7xxx.c

279

u8 tvco, tpcp, tpd, tlpf, idf;

sys/dev/drm/i915/dvo_ch7xxx.c

324

u8 val;

sys/dev/drm/i915/dvo_ch7xxx.c

339

u8 val;

sys/dev/drm/i915/dvo_ch7xxx.c

88

u8 vid;

sys/dev/drm/i915/dvo_ch7xxx.c

99

u8 did;

sys/dev/drm/i915/dvo_ivch.c

195

u8 out_buf[1];

sys/dev/drm/i915/dvo_ivch.c

196

u8 in_buf[2];

sys/dev/drm/i915/dvo_ivch.c

238

u8 out_buf[3];

sys/dev/drm/i915/dvo_ns2501.c

194

u8 offset;

sys/dev/drm/i915/dvo_ns2501.c

195

u8 value;

sys/dev/drm/i915/dvo_ns2501.c

205

u8 sync; /* configuration of the C0 register */

sys/dev/drm/i915/dvo_ns2501.c

206

u8 conf; /* configuration register 8 */

sys/dev/drm/i915/dvo_ns2501.c

207

u8 syncb; /* configuration register 41 */

sys/dev/drm/i915/dvo_ns2501.c

208

u8 dither; /* configuration of the dithering */

sys/dev/drm/i915/dvo_ns2501.c

209

u8 pll_a; /* PLL configuration, register A, 1B */

sys/dev/drm/i915/dvo_ns2501.c

392

static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/drm/i915/dvo_ns2501.c

396

u8 out_buf[2];

sys/dev/drm/i915/dvo_ns2501.c

397

u8 in_buf[2];

sys/dev/drm/i915/dvo_ns2501.c

437

static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/drm/i915/dvo_ns2501.c

441

u8 out_buf[2];

sys/dev/drm/i915/dvo_sil164.c

105

static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/drm/i915/dvo_sil164.c

109

u8 out_buf[2];

sys/dev/drm/i915/dvo_sil164.c

176

u8 reg9;

sys/dev/drm/i915/dvo_sil164.c

246

u8 val;

sys/dev/drm/i915/dvo_sil164.c

68

static bool sil164_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/drm/i915/dvo_sil164.c

72

u8 out_buf[2];

sys/dev/drm/i915/dvo_sil164.c

73

u8 in_buf[2];

sys/dev/drm/i915/dvo_tfp410.c

130

static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)

sys/dev/drm/i915/dvo_tfp410.c

134

u8 out_buf[2];

sys/dev/drm/i915/dvo_tfp410.c

158

u8 ch1, ch2;

sys/dev/drm/i915/dvo_tfp410.c

206

u8 ctl2;

sys/dev/drm/i915/dvo_tfp410.c

239

u8 ctl1;

sys/dev/drm/i915/dvo_tfp410.c

254

u8 ctl1;

sys/dev/drm/i915/dvo_tfp410.c

267

u8 val, val2;

sys/dev/drm/i915/dvo_tfp410.c

93

static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)

sys/dev/drm/i915/dvo_tfp410.c

97

u8 out_buf[2];

sys/dev/drm/i915/dvo_tfp410.c

98

u8 in_buf[2];

sys/dev/drm/i915/gvt/gvt.h

212

u8 *mmio_attribute;

sys/dev/drm/i915/gvt/gvt.h

383

(*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/gvt/gvt.h

391

(*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

sys/dev/drm/i915/i915_drv.c

1126

static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)

sys/dev/drm/i915/i915_drv.c

1139

skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)

sys/dev/drm/i915/i915_drv.c

1298

u8 num_active_channels;

sys/dev/drm/i915/i915_drv.c

1320

u8 size, width;

sys/dev/drm/i915/i915_drv.h

1130

u8 min_brightness; /* min_brightness/255 of max */

sys/dev/drm/i915/i915_drv.h

1131

u8 controller; /* brightness controller number */

sys/dev/drm/i915/i915_drv.h

1142

u8 seq_version;

sys/dev/drm/i915/i915_drv.h

1144

u8 *data;

sys/dev/drm/i915/i915_drv.h

1145

const u8 *sequence[MIPI_SEQ_MAX];

sys/dev/drm/i915/i915_drv.h

1146

u8 *deassert_seq; /* Used by fixup_mipi_sequences() */

sys/dev/drm/i915/i915_drv.h

1234

u8 enabled_slices; /* GEN11 has configurable 2 slices */

sys/dev/drm/i915/i915_drv.h

1585

u8 voltage_level;

sys/dev/drm/i915/i915_drv.h

1807

u8 min_voltage_level[I915_MAX_PIPES];

sys/dev/drm/i915/i915_drv.h

1957

u8 num_channels;

sys/dev/drm/i915/i915_drv.h

2024

u8 *vaddr;

sys/dev/drm/i915/i915_drv.h

2184

u8 size, width;

sys/dev/drm/i915/i915_drv.h

3463

bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);

sys/dev/drm/i915/i915_drv.h

3500

extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);

sys/dev/drm/i915/i915_drv.h

3502

extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);

sys/dev/drm/i915/i915_drv.h

3535

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);

sys/dev/drm/i915/i915_drv.h

3536

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);

sys/dev/drm/i915/i915_drv.h

3537

void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);

sys/dev/drm/i915/i915_drv.h

390

u8 initialized;

sys/dev/drm/i915/i915_drv.h

391

u8 dvo_port;

sys/dev/drm/i915/i915_drv.h

392

u8 slave_addr;

sys/dev/drm/i915/i915_drv.h

393

u8 dvo_wiring;

sys/dev/drm/i915/i915_drv.h

394

u8 i2c_pin;

sys/dev/drm/i915/i915_drv.h

395

u8 ddc_pin;

sys/dev/drm/i915/i915_drv.h

635

u8 sink_sync_latency;

sys/dev/drm/i915/i915_drv.h

780

u8 cur_freq; /* Current frequency (cached, may not == HW) */

sys/dev/drm/i915/i915_drv.h

781

u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */

sys/dev/drm/i915/i915_drv.h

782

u8 max_freq_softlimit; /* Max frequency permitted by the driver */

sys/dev/drm/i915/i915_drv.h

783

u8 max_freq; /* Maximum frequency, RP0 if not overclocking */

sys/dev/drm/i915/i915_drv.h

784

u8 min_freq; /* AKA RPn. Minimum frequency */

sys/dev/drm/i915/i915_drv.h

785

u8 boost_freq; /* Frequency to request when wait boosting */

sys/dev/drm/i915/i915_drv.h

786

u8 idle_freq; /* Frequency to request when we are idle */

sys/dev/drm/i915/i915_drv.h

787

u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */

sys/dev/drm/i915/i915_drv.h

788

u8 rp1_freq; /* "less than" RP0 power/freqency */

sys/dev/drm/i915/i915_drv.h

789

u8 rp0_freq; /* Non-overclocked max frequency. */

sys/dev/drm/i915/i915_drv.h

800

u8 up_threshold; /* Current %busy required to uplock */

sys/dev/drm/i915/i915_drv.h

801

u8 down_threshold; /* Current %busy required to downclock */

sys/dev/drm/i915/i915_drv.h

832

u8 cur_delay;

sys/dev/drm/i915/i915_drv.h

833

u8 min_delay;

sys/dev/drm/i915/i915_drv.h

834

u8 max_delay;

sys/dev/drm/i915/i915_drv.h

835

u8 fmax;

sys/dev/drm/i915/i915_drv.h

836

u8 fstart;

sys/dev/drm/i915/i915_drv.h

844

u8 corr;

sys/dev/drm/i915/i915_drv.h

904

u8 idx;

sys/dev/drm/i915/i915_drv.h

915

u8 idx;

sys/dev/drm/i915/i915_drv.h

917

u8 irq_pipe_mask;

sys/dev/drm/i915/i915_gem_context.h

194

u8 remap_slice;

sys/dev/drm/i915/i915_gem_gtt.c

3103

__alloc_ppat_entry(struct intel_ppat *ppat, unsigned int index, u8 value)

sys/dev/drm/i915/i915_gem_gtt.c

3145

intel_ppat_get(struct drm_i915_private *i915, u8 value)

sys/dev/drm/i915/i915_gem_gtt.c

3238

static unsigned int bdw_private_pat_match(u8 src, u8 dst)

sys/dev/drm/i915/i915_gem_gtt.c

3265

static unsigned int chv_private_pat_match(u8 src, u8 dst)

sys/dev/drm/i915/i915_gem_gtt.h

595

u8 value;

sys/dev/drm/i915/i915_gem_gtt.h

603

u8 clear_value;

sys/dev/drm/i915/i915_gem_gtt.h

608

unsigned int (*match)(u8 src, u8 dst);

sys/dev/drm/i915/i915_gem_gtt.h

615

intel_ppat_get(struct drm_i915_private *i915, u8 value);

sys/dev/drm/i915/i915_gpu_error.h

304

u8 *buf;

sys/dev/drm/i915/i915_irq.c

1120

u8 new_delay;

sys/dev/drm/i915/i915_irq.c

3004

const u8 instance, const u16 iir)

sys/dev/drm/i915/i915_irq.c

3015

const u8 class, const u8 instance, const u16 iir)

sys/dev/drm/i915/i915_irq.c

3035

const u8 class = GEN11_INTR_ENGINE_CLASS(identity);

sys/dev/drm/i915/i915_irq.c

3036

const u8 instance = GEN11_INTR_ENGINE_INSTANCE(identity);

sys/dev/drm/i915/i915_irq.c

3672

u8 pipe_mask)

sys/dev/drm/i915/i915_irq.c

3693

u8 pipe_mask)

sys/dev/drm/i915/i915_perf.c

600

const u8 *report)

sys/dev/drm/i915/i915_perf.c

656

u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;

sys/dev/drm/i915/i915_perf.c

708

u8 *report = oa_buf_base + head;

sys/dev/drm/i915/i915_perf.c

945

u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.vaddr;

sys/dev/drm/i915/i915_perf.c

994

u8 *report = oa_buf_base + head;

sys/dev/drm/i915/i915_pmu.c

25

static u8 engine_config_sample(u64 config)

sys/dev/drm/i915/i915_pmu.c

30

static u8 engine_event_sample(struct perf_event *event)

sys/dev/drm/i915/i915_pmu.c

35

static u8 engine_event_class(struct perf_event *event)

sys/dev/drm/i915/i915_pmu.c

370

u8 sample;

sys/dev/drm/i915/i915_pmu.c

40

static u8 engine_event_instance(struct perf_event *event)

sys/dev/drm/i915/i915_pmu.c

530

u8 sample = engine_event_sample(event);

sys/dev/drm/i915/i915_pmu.c

612

u8 sample = engine_event_sample(event);

sys/dev/drm/i915/i915_pmu.c

646

u8 sample = engine_event_sample(event);

sys/dev/drm/i915/i915_query.c

26

BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask));

sys/dev/drm/i915/intel_acpi.c

20

static char *intel_dsm_port_name(u8 id)

sys/dev/drm/i915/intel_acpi.c

56

static char *intel_dsm_mux_type(u8 type)

sys/dev/drm/i915/intel_audio.c

233

const u8 *eld = connector->eld;

sys/dev/drm/i915/intel_audio.c

281

const u8 *eld = connector->eld;

sys/dev/drm/i915/intel_audio.c

456

const u8 *eld = connector->eld;

sys/dev/drm/i915/intel_audio.c

554

const u8 *eld = connector->eld;

sys/dev/drm/i915/intel_audio.c

889

const u8 *eld;

sys/dev/drm/i915/intel_bios.c

1021

const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];

sys/dev/drm/i915/intel_bios.c

1054

u8 *init_otp;

sys/dev/drm/i915/intel_bios.c

1080

init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP];

sys/dev/drm/i915/intel_bios.c

1101

const u8 *seq_data;

sys/dev/drm/i915/intel_bios.c

1103

u8 *data;

sys/dev/drm/i915/intel_bios.c

1135

u8 seq_id = *(data + index);

sys/dev/drm/i915/intel_bios.c

1174

static u8 translate_iboost(u8 val)

sys/dev/drm/i915/intel_bios.c

1176

static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */

sys/dev/drm/i915/intel_bios.c

1256

static const u8 cnp_ddc_pin_map[] = {

sys/dev/drm/i915/intel_bios.c

1264

static const u8 icp_ddc_pin_map[] = {

sys/dev/drm/i915/intel_bios.c

1273

static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)

sys/dev/drm/i915/intel_bios.c

1275

const u8 *ddc_pin_map;

sys/dev/drm/i915/intel_bios.c

1298

u8 bdb_version)

sys/dev/drm/i915/intel_bios.c

1378

u8 ddc_pin;

sys/dev/drm/i915/intel_bios.c

1399

u8 hdmi_level_shift = child->hdmi_level_shifter_value;

sys/dev/drm/i915/intel_bios.c

1462

static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)

sys/dev/drm/i915/intel_bios.c

1486

u8 expected_size;

sys/dev/drm/i915/intel_bios.c

1722

u8 __iomem *bios = NULL;

sys/dev/drm/i915/intel_bios.c

1849

bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin)

sys/dev/drm/i915/intel_bios.c

189

size_t data_ofs = (const u8 *)data - (const u8 *)bdb;

sys/dev/drm/i915/intel_bios.c

199

return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs);

sys/dev/drm/i915/intel_bios.c

2031

u8 dvo_port;

sys/dev/drm/i915/intel_bios.c

439

parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version)

sys/dev/drm/i915/intel_bios.c

62

static u32 _get_blocksize(const u8 *block_base)

sys/dev/drm/i915/intel_bios.c

655

u8 vswing;

sys/dev/drm/i915/intel_bios.c

81

const u8 *base = _bdb;

sys/dev/drm/i915/intel_bios.c

84

u8 current_id;

sys/dev/drm/i915/intel_bios.c

860

static const u8 *

sys/dev/drm/i915/intel_bios.c

865

const u8 *data = &sequence->data[0];

sys/dev/drm/i915/intel_bios.c

866

u8 current_id;

sys/dev/drm/i915/intel_bios.c

908

static int goto_next_sequence(const u8 *data, int index, int total)

sys/dev/drm/i915/intel_bios.c

914

u8 operation_byte = *(data + index);

sys/dev/drm/i915/intel_bios.c

946

static int goto_next_sequence_v3(const u8 *data, int index, int total)

sys/dev/drm/i915/intel_bios.c

979

u8 operation_byte = *(data + index);

sys/dev/drm/i915/intel_bios.h

140

u8 rsvd5;

sys/dev/drm/i915/intel_bios.h

148

u8 byte_clk_sel:2;

sys/dev/drm/i915/intel_bios.h

150

u8 rsvd6:6;

sys/dev/drm/i915/intel_bios.h

181

u8 tclk_miss;

sys/dev/drm/i915/intel_bios.h

182

u8 tclk_post;

sys/dev/drm/i915/intel_bios.h

183

u8 rsvd12;

sys/dev/drm/i915/intel_bios.h

184

u8 tclk_pre;

sys/dev/drm/i915/intel_bios.h

185

u8 tclk_prepare;

sys/dev/drm/i915/intel_bios.h

186

u8 tclk_settle;

sys/dev/drm/i915/intel_bios.h

187

u8 tclk_term_enable;

sys/dev/drm/i915/intel_bios.h

188

u8 tclk_trail;

sys/dev/drm/i915/intel_bios.h

190

u8 rsvd13;

sys/dev/drm/i915/intel_bios.h

191

u8 td_term_enable;

sys/dev/drm/i915/intel_bios.h

192

u8 teot;

sys/dev/drm/i915/intel_bios.h

193

u8 ths_exit;

sys/dev/drm/i915/intel_bios.h

194

u8 ths_prepare;

sys/dev/drm/i915/intel_bios.h

196

u8 rsvd14;

sys/dev/drm/i915/intel_bios.h

197

u8 ths_settle;

sys/dev/drm/i915/intel_bios.h

198

u8 ths_skip;

sys/dev/drm/i915/intel_bios.h

199

u8 ths_trail;

sys/dev/drm/i915/intel_bios.h

200

u8 tinit;

sys/dev/drm/i915/intel_bios.h

201

u8 tlpx;

sys/dev/drm/i915/intel_bios.h

202

u8 rsvd15[3];

sys/dev/drm/i915/intel_bios.h

205

u8 panel_enable;

sys/dev/drm/i915/intel_bios.h

206

u8 bl_enable;

sys/dev/drm/i915/intel_bios.h

207

u8 pwm_enable;

sys/dev/drm/i915/intel_bios.h

208

u8 reset_r_n;

sys/dev/drm/i915/intel_bios.h

209

u8 pwr_down_r;

sys/dev/drm/i915/intel_bios.h

210

u8 stdby_r_n;

sys/dev/drm/i915/intel_cdclk.c

1204

static u8 bxt_calc_voltage_level(int cdclk)

sys/dev/drm/i915/intel_cdclk.c

1557

static u8 cnl_calc_voltage_level(int cdclk)

sys/dev/drm/i915/intel_cdclk.c

1890

static u8 icl_calc_voltage_level(int cdclk)

sys/dev/drm/i915/intel_cdclk.c

2256

static u8 cnl_compute_min_voltage_level(struct intel_atomic_state *state)

sys/dev/drm/i915/intel_cdclk.c

2261

u8 min_voltage_level;

sys/dev/drm/i915/intel_cdclk.c

441

static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)

sys/dev/drm/i915/intel_cdclk.c

655

static u8 bdw_calc_voltage_level(int cdclk)

sys/dev/drm/i915/intel_cdclk.c

797

static u8 skl_calc_voltage_level(int cdclk)

sys/dev/drm/i915/intel_ddi.c

2231

u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder)

sys/dev/drm/i915/intel_ddi.c

2274

u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, u8 voltage_swing)

sys/dev/drm/i915/intel_ddi.c

305

u8 margin; /* swing value */

sys/dev/drm/i915/intel_ddi.c

306

u8 scale; /* scale value */

sys/dev/drm/i915/intel_ddi.c

307

u8 enable; /* scale enable */

sys/dev/drm/i915/intel_ddi.c

308

u8 deemphasis;

sys/dev/drm/i915/intel_ddi.c

35

u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */

sys/dev/drm/i915/intel_ddi.c

357

u8 dw2_swing_sel;

sys/dev/drm/i915/intel_ddi.c

358

u8 dw7_n_scalar;

sys/dev/drm/i915/intel_ddi.c

359

u8 dw4_cursor_coeff;

sys/dev/drm/i915/intel_ddi.c

3596

u8 config;

sys/dev/drm/i915/intel_ddi.c

360

u8 dw4_post_cursor_2;

sys/dev/drm/i915/intel_ddi.c

361

u8 dw4_post_cursor_1;

sys/dev/drm/i915/intel_ddi.c

38

static const u8 index_to_dp_signal_levels[] = {

sys/dev/drm/i915/intel_device_info.c

164

u8 s_en;

sys/dev/drm/i915/intel_device_info.c

166

u8 eu_en;

sys/dev/drm/i915/intel_device_info.c

290

u8 disabled_mask =

sys/dev/drm/i915/intel_device_info.c

301

u8 disabled_mask =

sys/dev/drm/i915/intel_device_info.c

336

const u8 eu_mask = 0xff;

sys/dev/drm/i915/intel_device_info.c

368

u8 eu_disabled_mask;

sys/dev/drm/i915/intel_device_info.c

474

u8 eu_disabled_mask;

sys/dev/drm/i915/intel_device_info.c

809

u8 disabled_mask = 0;

sys/dev/drm/i915/intel_device_info.c

875

u8 vdbox_disable, vebox_disable;

sys/dev/drm/i915/intel_device_info.h

120

u8 slice_mask;

sys/dev/drm/i915/intel_device_info.h

121

u8 subslice_mask[GEN_MAX_SUBSLICES];

sys/dev/drm/i915/intel_device_info.h

123

u8 eu_per_subslice;

sys/dev/drm/i915/intel_device_info.h

124

u8 min_eu_in_pool;

sys/dev/drm/i915/intel_device_info.h

126

u8 subslice_7eu[3];

sys/dev/drm/i915/intel_device_info.h

127

u8 has_slice_pg:1;

sys/dev/drm/i915/intel_device_info.h

128

u8 has_subslice_pg:1;

sys/dev/drm/i915/intel_device_info.h

129

u8 has_eu_pg:1;

sys/dev/drm/i915/intel_device_info.h

132

u8 max_slices;

sys/dev/drm/i915/intel_device_info.h

133

u8 max_subslices;

sys/dev/drm/i915/intel_device_info.h

134

u8 max_eus_per_subslice;

sys/dev/drm/i915/intel_device_info.h

140

u8 eu_mask[GEN_MAX_SLICES * GEN_MAX_SUBSLICES];

sys/dev/drm/i915/intel_device_info.h

143

typedef u8 intel_ring_mask_t;

sys/dev/drm/i915/intel_device_info.h

149

u8 gen;

sys/dev/drm/i915/intel_device_info.h

150

u8 gt; /* GT number, 0 if undefined */

sys/dev/drm/i915/intel_device_info.h

151

u8 num_rings;

sys/dev/drm/i915/intel_device_info.h

161

u8 num_pipes;

sys/dev/drm/i915/intel_device_info.h

162

u8 num_sprites[I915_MAX_PIPES];

sys/dev/drm/i915/intel_device_info.h

163

u8 num_scalers[I915_MAX_PIPES];

sys/dev/drm/i915/intel_device_info.h

165

#define DEFINE_FLAG(name) u8 name:1

sys/dev/drm/i915/intel_display.c

12662

u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;

sys/dev/drm/i915/intel_display.c

12663

u8 required_slices = intel_state->wm_results.ddb.enabled_slices;

sys/dev/drm/i915/intel_display.c

15149

u8 sr1;

sys/dev/drm/i915/intel_dp.c

1430

intel_dp_aux_header(u8 txbuf[HEADER_SIZE],

sys/dev/drm/i915/intel_dp.c

3990

u8 sink_count;

sys/dev/drm/i915/intel_dp.c

4038

u8 mstm_cap;

sys/dev/drm/i915/intel_dp.c

4076

intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)

sys/dev/drm/i915/intel_dp.c

4083

intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)

sys/dev/drm/i915/intel_dp.c

4287

u8 esi[DP_DPRX_ESI_LEN] = { 0 };

sys/dev/drm/i915/intel_dp.c

4343

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/drm/i915/intel_dp.c

4486

u8 sink_irq_vector = 0;

sys/dev/drm/i915/intel_dp.c

4487

u8 old_sink_count = intel_dp->sink_count;

sys/dev/drm/i915/intel_dp.c

5055

u8 sink_irq_vector = 0;

sys/dev/drm/i915/intel_dp.c

5339

u8 *an)

sys/dev/drm/i915/intel_dp.c

5383

u8 *bksv)

sys/dev/drm/i915/intel_dp.c

5396

u8 *bstatus)

sys/dev/drm/i915/intel_dp.c

5415

u8 *bcaps)

sys/dev/drm/i915/intel_dp.c

5434

u8 bcaps;

sys/dev/drm/i915/intel_dp.c

5446

u8 *ri_prime)

sys/dev/drm/i915/intel_dp.c

5463

u8 bstatus;

sys/dev/drm/i915/intel_dp.c

5476

int num_downstream, u8 *ksv_fifo)

sys/dev/drm/i915/intel_dp.c

5528

u8 bstatus;

sys/dev/drm/i915/intel_dp.c

5545

u8 bcaps;

sys/dev/drm/i915/intel_dp_aux_backlight.c

114

u8 pn, pn_min, pn_max;

sys/dev/drm/i915/intel_dp_aux_backlight.c

169

DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {

sys/dev/drm/i915/intel_dp_aux_backlight.c

181

u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;

sys/dev/drm/i915/intel_dp_aux_backlight.c

29

u8 reg_val = 0;

sys/dev/drm/i915/intel_dp_aux_backlight.c

60

u8 read_val[2] = { 0x0 };

sys/dev/drm/i915/intel_dp_aux_backlight.c

85

u8 vals[2] = { 0x0 };

sys/dev/drm/i915/intel_drv.h

1000

u8 guard_size;

sys/dev/drm/i915/intel_drv.h

1001

u8 cacheline_size;

sys/dev/drm/i915/intel_drv.h

1074

u8 test_lane_count;

sys/dev/drm/i915/intel_drv.h

1412

u8 pipe_mask);

sys/dev/drm/i915/intel_drv.h

1414

u8 pipe_mask);

sys/dev/drm/i915/intel_drv.h

1449

u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);

sys/dev/drm/i915/intel_drv.h

1450

u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,

sys/dev/drm/i915/intel_drv.h

1451

u8 voltage_swing);

sys/dev/drm/i915/intel_drv.h

2015

u8 req_slices);

sys/dev/drm/i915/intel_drv.h

302

u8 controller; /* bxt+ only */

sys/dev/drm/i915/intel_drv.h

351

int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);

sys/dev/drm/i915/intel_drv.h

354

int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);

sys/dev/drm/i915/intel_drv.h

363

u8 *bstatus);

sys/dev/drm/i915/intel_drv.h

370

int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);

sys/dev/drm/i915/intel_drv.h

378

int num_downstream, u8 *ksv_fifo);

sys/dev/drm/i915/intel_drv.h

419

u8 polled;

sys/dev/drm/i915/intel_drv.h

490

u8 min_voltage_level[I915_MAX_PIPES];

sys/dev/drm/i915/intel_drv.h

562

u8 rotation;

sys/dev/drm/i915/intel_drv.h

862

u8 min_voltage_level;

sys/dev/drm/i915/intel_drv.h

906

u8 active_planes;

sys/dev/drm/i915/intel_drv.h

907

u8 nv12_planes;

sys/dev/drm/i915/intel_drv.h

928

u8 plane_ids_mask;

sys/dev/drm/i915/intel_drv.h

999

u8 default_wm;

sys/dev/drm/i915/intel_dsi.h

75

u8 eotp_pkt;

sys/dev/drm/i915/intel_dsi.h

76

u8 clock_stop;

sys/dev/drm/i915/intel_dsi.h

78

u8 escape_clk_div;

sys/dev/drm/i915/intel_dsi.h

79

u8 dual_link;

sys/dev/drm/i915/intel_dsi.h

84

u8 pixel_overlap;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

120

u8 ctrl = 0;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

136

u8 cabc = POWER_SAVE_MEDIUM;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

49

u8 data = 0;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

67

u8 data = level;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

87

u8 cabc = POWER_SAVE_OFF;

sys/dev/drm/i915/intel_dsi_dcs_backlight.c

95

u8 ctrl = 0;

sys/dev/drm/i915/intel_dsi_vbt.c

106

static inline enum port intel_dsi_seq_port_to_port(u8 port)

sys/dev/drm/i915/intel_dsi_vbt.c

111

static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,

sys/dev/drm/i915/intel_dsi_vbt.c

112

const u8 *data)

sys/dev/drm/i915/intel_dsi_vbt.c

115

u8 type, flags, seq_port;

sys/dev/drm/i915/intel_dsi_vbt.c

192

static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/drm/i915/intel_dsi_vbt.c

205

u8 gpio_source, u8 gpio_index, bool value)

sys/dev/drm/i915/intel_dsi_vbt.c

210

u8 port;

sys/dev/drm/i915/intel_dsi_vbt.c

250

u8 gpio_source, u8 gpio_index, bool value)

sys/dev/drm/i915/intel_dsi_vbt.c

254

u8 port;

sys/dev/drm/i915/intel_dsi_vbt.c

301

u8 gpio_source, u8 gpio_index, bool value)

sys/dev/drm/i915/intel_dsi_vbt.c

325

static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/drm/i915/intel_dsi_vbt.c

329

u8 gpio_source, gpio_index = 0, gpio_number;

sys/dev/drm/i915/intel_dsi_vbt.c

358

static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/drm/i915/intel_dsi_vbt.c

365

static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/drm/i915/intel_dsi_vbt.c

372

static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)

sys/dev/drm/i915/intel_dsi_vbt.c

379

typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,

sys/dev/drm/i915/intel_dsi_vbt.c

380

const u8 *data);

sys/dev/drm/i915/intel_dsi_vbt.c

422

const u8 *data;

sys/dev/drm/i915/intel_dsi_vbt.c

445

u8 operation_byte = *data++;

sys/dev/drm/i915/intel_dsi_vbt.c

446

u8 operation_size = 0;

sys/dev/drm/i915/intel_dsi_vbt.c

461

const u8 *next = data + operation_size;

sys/dev/drm/i915/intel_engine_cs.c

1347

u8 read, write;

sys/dev/drm/i915/intel_engine_cs.c

1582

static u8 user_class_map[] = {

sys/dev/drm/i915/intel_engine_cs.c

1590

intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance)

sys/dev/drm/i915/intel_engine_cs.c

190

__intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)

sys/dev/drm/i915/intel_engine_cs.c

53

u8 uabi_class;

sys/dev/drm/i915/intel_engine_cs.c

87

u8 class;

sys/dev/drm/i915/intel_engine_cs.c

88

u8 instance;

sys/dev/drm/i915/intel_guc_ads.c

85

u8 reg_state_buffer[GUC_S3_SAVE_SPACE_PAGES * PAGE_SIZE];

sys/dev/drm/i915/intel_guc_fwif.h

186

u8 day;

sys/dev/drm/i915/intel_guc_fwif.h

187

u8 month;

sys/dev/drm/i915/intel_guc_fwif.h

198

u8 hour;

sys/dev/drm/i915/intel_guc_fwif.h

199

u8 min;

sys/dev/drm/i915/intel_guc_fwif.h

278

u8 engine_state_submit_value;

sys/dev/drm/i915/intel_guc_fwif.h

279

u8 engine_state_wait_value;

sys/dev/drm/i915/intel_guc_fwif.h

297

u8 engines_used;

sys/dev/drm/i915/intel_guc_fwif.h

305

u8 attribute;

sys/dev/drm/i915/intel_guc_fwif.h

318

u8 engine_suspended;

sys/dev/drm/i915/intel_guc_fwif.h

320

u8 reserved0[3];

sys/dev/drm/i915/intel_hdcp.c

171

bool intel_hdcp_is_ksv_valid(u8 *ksv)

sys/dev/drm/i915/intel_hdcp.c

185

u8 *ksv_fifo, u8 num_downstream, u8 *bstatus)

sys/dev/drm/i915/intel_hdcp.c

218

u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN];

sys/dev/drm/i915/intel_hdcp.c

402

u8 bstatus[2], num_downstream, *ksv_fifo;

sys/dev/drm/i915/intel_hdcp.c

475

u8 shim[DRM_HDCP_AN_LEN];

sys/dev/drm/i915/intel_hdcp.c

479

u8 shim[DRM_HDCP_KSV_LEN];

sys/dev/drm/i915/intel_hdcp.c

483

u8 shim[DRM_HDCP_RI_LEN];

sys/dev/drm/i915/intel_hdmi.c

1008

u8 val;

sys/dev/drm/i915/intel_hdmi.c

1021

u8 *ri_prime)

sys/dev/drm/i915/intel_hdmi.c

1036

u8 val;

sys/dev/drm/i915/intel_hdmi.c

1049

int num_downstream, u8 *ksv_fifo)

sys/dev/drm/i915/intel_hdmi.c

1104

u8 shim[DRM_HDCP_RI_LEN];

sys/dev/drm/i915/intel_hdmi.c

2168

static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)

sys/dev/drm/i915/intel_hdmi.c

2170

u8 ddc_pin;

sys/dev/drm/i915/intel_hdmi.c

2190

static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)

sys/dev/drm/i915/intel_hdmi.c

2192

u8 ddc_pin;

sys/dev/drm/i915/intel_hdmi.c

2209

static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_hdmi.c

2212

u8 ddc_pin;

sys/dev/drm/i915/intel_hdmi.c

2235

static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)

sys/dev/drm/i915/intel_hdmi.c

2237

u8 ddc_pin;

sys/dev/drm/i915/intel_hdmi.c

2266

static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_hdmi.c

2269

u8 ddc_pin;

sys/dev/drm/i915/intel_hdmi.c

2289

static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_hdmi.c

2294

u8 ddc_pin;

sys/dev/drm/i915/intel_hdmi.c

451

u8 buffer[VIDEO_DIP_DATA_SIZE];

sys/dev/drm/i915/intel_hdmi.c

899

u8 start = offset & 0xff;

sys/dev/drm/i915/intel_hdmi.c

929

u8 *write_buf;

sys/dev/drm/i915/intel_hdmi.c

956

u8 *an)

sys/dev/drm/i915/intel_hdmi.c

981

u8 *bksv)

sys/dev/drm/i915/intel_hdmi.c

993

u8 *bstatus)

sys/dev/drm/i915/intel_i2c.c

371

unsigned short addr, u8 *buf, unsigned int len,

sys/dev/drm/i915/intel_i2c.c

436

u8 *buf = msg->buf;

sys/dev/drm/i915/intel_i2c.c

461

unsigned short addr, u8 *buf, unsigned int len,

sys/dev/drm/i915/intel_i2c.c

501

u8 *buf = msg->buf;

sys/dev/drm/i915/intel_i2c.c

729

u8 cmd = DRM_HDCP_DDC_AKSV;

sys/dev/drm/i915/intel_i2c.c

730

u8 buf[DRM_HDCP_KSV_LEN] = { 0 };

sys/dev/drm/i915/intel_lrc.c

2388

const u8 irq_shifts[] = {

sys/dev/drm/i915/intel_lrc.c

2527

u8 slices = hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask);

sys/dev/drm/i915/intel_lrc.c

2528

u8 subslices = hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]);

sys/dev/drm/i915/intel_lrc.c

922

u8 head, tail;

sys/dev/drm/i915/intel_lspcon.c

119

u8 rev;

sys/dev/drm/i915/intel_lvds.c

872

u8 pin;

sys/dev/drm/i915/intel_opregion.c

102

u8 rsvd[244];

sys/dev/drm/i915/intel_opregion.c

117

u8 plut[74]; /* panel LUT and identifier */

sys/dev/drm/i915/intel_opregion.c

128

u8 rsvd[58];

sys/dev/drm/i915/intel_opregion.c

134

u8 bddc[256]; /* Panel EDID */

sys/dev/drm/i915/intel_opregion.c

135

u8 rsvd[764];

sys/dev/drm/i915/intel_opregion.c

60

u8 signature[16];

sys/dev/drm/i915/intel_opregion.c

63

u8 bios_ver[32];

sys/dev/drm/i915/intel_opregion.c

64

u8 vbios_ver[16];

sys/dev/drm/i915/intel_opregion.c

65

u8 driver_ver[16];

sys/dev/drm/i915/intel_opregion.c

69

u8 dver[32];

sys/dev/drm/i915/intel_opregion.c

70

u8 rsvd[124];

sys/dev/drm/i915/intel_opregion.c

78

u8 rsvd1[20];

sys/dev/drm/i915/intel_opregion.c

94

u8 rsvd2[4];

sys/dev/drm/i915/intel_overlay.c

195

u8 val;

sys/dev/drm/i915/intel_panel.c

488

u8 lbpc;

sys/dev/drm/i915/intel_panel.c

559

u8 lbpc;

sys/dev/drm/i915/intel_pm.c

3617

static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_pm.c

3619

u8 enabled_slices;

sys/dev/drm/i915/intel_pm.c

6194

bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6220

u8 fmax, fmin, fstart, vstart;

sys/dev/drm/i915/intel_pm.c

6316

static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6416

static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6475

static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6494

static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6529

static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6595

u8 freq;

sys/dev/drm/i915/intel_pm.c

6676

int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)

sys/dev/drm/i915/intel_pm.c

6862

clamp_t(u8,

sys/dev/drm/i915/intel_pm.c

6881

int (*set)(struct drm_i915_private *, u8))

sys/dev/drm/i915/intel_pm.c

6884

u8 freq = rps->cur_freq;

sys/dev/drm/i915/intel_pm.c

7871

static int _pxvid_to_vd(u8 pxvid)

sys/dev/drm/i915/intel_pm.c

7882

static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)

sys/dev/drm/i915/intel_pm.c

8165

u8 pxw[16];

sys/dev/drm/i915/intel_psr.c

1091

u8 val;

sys/dev/drm/i915/intel_psr.c

1092

const u8 errors = DP_PSR_RFB_STORAGE_ERROR |

sys/dev/drm/i915/intel_psr.c

205

static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)

sys/dev/drm/i915/intel_psr.c

207

u8 val = 8; /* assume the worst if we can't read the value */

sys/dev/drm/i915/intel_psr.c

337

u8 dpcd_val = DP_PSR_ENABLE;

sys/dev/drm/i915/intel_ringbuffer.h

1120

intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance);

sys/dev/drm/i915/intel_ringbuffer.h

342

u8 csb_head;

sys/dev/drm/i915/intel_ringbuffer.h

357

u8 uabi_id;

sys/dev/drm/i915/intel_ringbuffer.h

358

u8 uabi_class;

sys/dev/drm/i915/intel_ringbuffer.h

360

u8 class;

sys/dev/drm/i915/intel_ringbuffer.h

361

u8 instance;

sys/dev/drm/i915/intel_runtime_pm.c

263

u8 irq_pipe_mask, bool has_vga)

sys/dev/drm/i915/intel_runtime_pm.c

288

u8 irq_pipe_mask)

sys/dev/drm/i915/intel_runtime_pm.c

3169

static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)

sys/dev/drm/i915/intel_runtime_pm.c

3177

u8 req_slices)

sys/dev/drm/i915/intel_runtime_pm.c

3179

const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;

sys/dev/drm/i915/intel_sdvo.c

129

u8 tv_format_supported[TV_FORMAT_NUM];

sys/dev/drm/i915/intel_sdvo.c

1447

u8 val;

sys/dev/drm/i915/intel_sdvo.c

1769

u8 ddc, saved_ddc = intel_sdvo->ddc_bus;

sys/dev/drm/i915/intel_sdvo.c

2355

u8 pin;

sys/dev/drm/i915/intel_sdvo.c

2391

static u8

sys/dev/drm/i915/intel_sdvo.c

248

static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)

sys/dev/drm/i915/intel_sdvo.c

276

u8 cmd;

sys/dev/drm/i915/intel_sdvo.c

3084

u8 byte;

sys/dev/drm/i915/intel_sdvo.c

394

static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/drm/i915/intel_sdvo.c

406

BUF_PRINT("%02X ", ((u8 *)args)[i]);

sys/dev/drm/i915/intel_sdvo.c

437

static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/drm/i915/intel_sdvo.c

441

u8 *buf, status;

sys/dev/drm/i915/intel_sdvo.c

464

buf[2*i + 1] = ((u8*)args)[i];

sys/dev/drm/i915/intel_sdvo.c

506

static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/drm/i915/intel_sdvo.c

515

u8 retry = 15; /* 5 quick checks, followed by 10 long checks */

sys/dev/drm/i915/intel_sdvo.c

516

u8 status;

sys/dev/drm/i915/intel_sdvo.c

572

&((u8 *)response)[i]))

sys/dev/drm/i915/intel_sdvo.c

574

BUF_PRINT(" %02X", ((u8 *)response)[i]);

sys/dev/drm/i915/intel_sdvo.c

599

u8 ddc_bus)

sys/dev/drm/i915/intel_sdvo.c

607

static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)

sys/dev/drm/i915/intel_sdvo.c

616

intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)

sys/dev/drm/i915/intel_sdvo.c

671

u8 state = SDVO_ENCODER_STATE_ON;

sys/dev/drm/i915/intel_sdvo.c

718

static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/drm/i915/intel_sdvo.c

72

u8 slave_addr;

sys/dev/drm/i915/intel_sdvo.c

725

static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,

sys/dev/drm/i915/intel_sdvo.c

789

static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)

sys/dev/drm/i915/intel_sdvo_regs.h

108

u8 interlace:1;

sys/dev/drm/i915/intel_sdvo_regs.h

109

u8 scaled:1;

sys/dev/drm/i915/intel_sdvo_regs.h

110

u8 pad:6;

sys/dev/drm/i915/intel_sdvo_regs.h

49

u8 vendor_id;

sys/dev/drm/i915/intel_sdvo_regs.h

50

u8 device_id;

sys/dev/drm/i915/intel_sdvo_regs.h

51

u8 device_rev_id;

sys/dev/drm/i915/intel_sdvo_regs.h

52

u8 sdvo_version_major;

sys/dev/drm/i915/intel_sdvo_regs.h

53

u8 sdvo_version_minor;

sys/dev/drm/i915/intel_sdvo_regs.h

547

u8 t0;

sys/dev/drm/i915/intel_sdvo_regs.h

548

u8 t1;

sys/dev/drm/i915/intel_sdvo_regs.h

549

u8 t2;

sys/dev/drm/i915/intel_sdvo_regs.h

550

u8 t3;

sys/dev/drm/i915/intel_sdvo_regs.h

551

u8 t4;

sys/dev/drm/i915/intel_sdvo_regs.h

564

u8 max_value;

sys/dev/drm/i915/intel_sdvo_regs.h

565

u8 default_value;

sys/dev/drm/i915/intel_sdvo_regs.h

728

u8 dvi_rev;

sys/dev/drm/i915/intel_sdvo_regs.h

729

u8 hdmi_rev;

sys/dev/drm/i915/intel_sdvo_regs.h

73

u8 h_active; /* lower 8 bits (pixels) */

sys/dev/drm/i915/intel_sdvo_regs.h

74

u8 h_blank; /* lower 8 bits (pixels) */

sys/dev/drm/i915/intel_sdvo_regs.h

75

u8 h_high; /* upper 4 bits each h_active, h_blank */

sys/dev/drm/i915/intel_sdvo_regs.h

76

u8 v_active; /* lower 8 bits (lines) */

sys/dev/drm/i915/intel_sdvo_regs.h

77

u8 v_blank; /* lower 8 bits (lines) */

sys/dev/drm/i915/intel_sdvo_regs.h

78

u8 v_high; /* upper 4 bits each v_active, v_blank */

sys/dev/drm/i915/intel_sdvo_regs.h

82

u8 h_sync_off; /* lower 8 bits, from hblank start */

sys/dev/drm/i915/intel_sdvo_regs.h

83

u8 h_sync_width; /* lower 8 bits (pixels) */

sys/dev/drm/i915/intel_sdvo_regs.h

85

u8 v_sync_off_width;

sys/dev/drm/i915/intel_sdvo_regs.h

90

u8 sync_off_width_high;

sys/dev/drm/i915/intel_sdvo_regs.h

91

u8 dtd_flags;

sys/dev/drm/i915/intel_sdvo_regs.h

92

u8 sdvo_flags;

sys/dev/drm/i915/intel_sdvo_regs.h

94

u8 v_sync_off_high;

sys/dev/drm/i915/intel_sdvo_regs.h

95

u8 reserved;

sys/dev/drm/i915/intel_sideband.c

124

u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)

sys/dev/drm/i915/intel_sideband.c

138

u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)

sys/dev/drm/i915/intel_sideband.c

147

u8 port, u32 reg, u32 val)

sys/dev/drm/i915/intel_tv.c

311

u8 hsync_end;

sys/dev/drm/i915/intel_tv.c

314

u8 vsync_start_f1, vsync_start_f2, vsync_len;

sys/dev/drm/i915/intel_tv.c

316

u8 veq_start_f1, veq_start_f2, veq_len;

sys/dev/drm/i915/intel_tv.c

317

u8 vi_end_f1, vi_end_f2;

sys/dev/drm/i915/intel_tv.c

320

u8 hburst_start, hburst_len;

sys/dev/drm/i915/intel_tv.c

321

u8 vburst_start_f1;

sys/dev/drm/i915/intel_tv.c

323

u8 vburst_start_f2;

sys/dev/drm/i915/intel_tv.c

325

u8 vburst_start_f3;

sys/dev/drm/i915/intel_tv.c

327

u8 vburst_start_f4;

sys/dev/drm/i915/intel_tv.c

333

u8 dda1_inc;

sys/dev/drm/i915/intel_tv.c

54

u8 burst;

sys/dev/drm/i915/intel_uncore.c

1659

u8 size;

sys/dev/drm/i915/intel_uncore.c

1756

u8 gdrst;

sys/dev/drm/i915/intel_uncore.c

1785

u8 gdrst;

sys/dev/drm/i915/intel_uncore.h

70

u8 (*mmio_readb)(struct drm_i915_private *dev_priv,

sys/dev/drm/i915/intel_uncore.h

80

i915_reg_t r, u8 val, bool trace);

sys/dev/drm/i915/intel_vbt_defs.h

140

u8 panel_fitting:2;

sys/dev/drm/i915/intel_vbt_defs.h

141

u8 flexaim:1;

sys/dev/drm/i915/intel_vbt_defs.h

142

u8 msg_enable:1;

sys/dev/drm/i915/intel_vbt_defs.h

143

u8 clear_screen:3;

sys/dev/drm/i915/intel_vbt_defs.h

144

u8 color_flip:1;

sys/dev/drm/i915/intel_vbt_defs.h

147

u8 download_ext_vbt:1;

sys/dev/drm/i915/intel_vbt_defs.h

148

u8 enable_ssc:1;

sys/dev/drm/i915/intel_vbt_defs.h

149

u8 ssc_freq:1;

sys/dev/drm/i915/intel_vbt_defs.h

150

u8 enable_lfp_on_override:1;

sys/dev/drm/i915/intel_vbt_defs.h

151

u8 disable_ssc_ddt:1;

sys/dev/drm/i915/intel_vbt_defs.h

152

u8 underscan_vga_timings:1;

sys/dev/drm/i915/intel_vbt_defs.h

153

u8 display_clock_mode:1;

sys/dev/drm/i915/intel_vbt_defs.h

154

u8 vbios_hotplug_support:1;

sys/dev/drm/i915/intel_vbt_defs.h

157

u8 disable_smooth_vision:1;

sys/dev/drm/i915/intel_vbt_defs.h

158

u8 single_dvi:1;

sys/dev/drm/i915/intel_vbt_defs.h

159

u8 rotate_180:1; /* 181 */

sys/dev/drm/i915/intel_vbt_defs.h

160

u8 fdi_rx_polarity_inverted:1;

sys/dev/drm/i915/intel_vbt_defs.h

161

u8 vbios_extended_mode:1; /* 160 */

sys/dev/drm/i915/intel_vbt_defs.h

162

u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */

sys/dev/drm/i915/intel_vbt_defs.h

163

u8 panel_best_fit_timing:1; /* 160 */

sys/dev/drm/i915/intel_vbt_defs.h

164

u8 ignore_strap_state:1; /* 160 */

sys/dev/drm/i915/intel_vbt_defs.h

167

u8 legacy_monitor_detect;

sys/dev/drm/i915/intel_vbt_defs.h

170

u8 int_crt_support:1;

sys/dev/drm/i915/intel_vbt_defs.h

171

u8 int_tv_support:1;

sys/dev/drm/i915/intel_vbt_defs.h

172

u8 int_efp_support:1;

sys/dev/drm/i915/intel_vbt_defs.h

173

u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */

sys/dev/drm/i915/intel_vbt_defs.h

174

u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */

sys/dev/drm/i915/intel_vbt_defs.h

175

u8 dp_ssc_dongle_supported:1;

sys/dev/drm/i915/intel_vbt_defs.h

176

u8 rsvd11:2; /* finish byte */

sys/dev/drm/i915/intel_vbt_defs.h

357

u8 device_id[10]; /* ascii string */

sys/dev/drm/i915/intel_vbt_defs.h

359

u8 i2c_speed;

sys/dev/drm/i915/intel_vbt_defs.h

360

u8 dp_onboard_redriver; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

361

u8 dp_ondock_redriver; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

362

u8 hdmi_level_shifter_value:5; /* 169 */

sys/dev/drm/i915/intel_vbt_defs.h

363

u8 hdmi_max_data_rate:3; /* 204 */

sys/dev/drm/i915/intel_vbt_defs.h

365

u8 edidless_efp:1; /* 161 */

sys/dev/drm/i915/intel_vbt_defs.h

366

u8 compression_enable:1; /* 198 */

sys/dev/drm/i915/intel_vbt_defs.h

367

u8 compression_method:1; /* 198 */

sys/dev/drm/i915/intel_vbt_defs.h

368

u8 ganged_edp:1; /* 202 */

sys/dev/drm/i915/intel_vbt_defs.h

369

u8 reserved0:4;

sys/dev/drm/i915/intel_vbt_defs.h

370

u8 compression_structure_index:4; /* 198 */

sys/dev/drm/i915/intel_vbt_defs.h

371

u8 reserved1:4;

sys/dev/drm/i915/intel_vbt_defs.h

372

u8 slave_port; /* 202 */

sys/dev/drm/i915/intel_vbt_defs.h

373

u8 reserved2;

sys/dev/drm/i915/intel_vbt_defs.h

378

u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */

sys/dev/drm/i915/intel_vbt_defs.h

379

u8 i2c_pin;

sys/dev/drm/i915/intel_vbt_defs.h

380

u8 slave_addr;

sys/dev/drm/i915/intel_vbt_defs.h

381

u8 ddc_pin;

sys/dev/drm/i915/intel_vbt_defs.h

383

u8 dvo_cfg; /* See DEVICE_CFG_* above */

sys/dev/drm/i915/intel_vbt_defs.h

387

u8 dvo2_port;

sys/dev/drm/i915/intel_vbt_defs.h

388

u8 i2c2_pin;

sys/dev/drm/i915/intel_vbt_defs.h

389

u8 slave2_addr;

sys/dev/drm/i915/intel_vbt_defs.h

390

u8 ddc2_pin;

sys/dev/drm/i915/intel_vbt_defs.h

393

u8 efp_routed:1; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

394

u8 lane_reversal:1; /* 184 */

sys/dev/drm/i915/intel_vbt_defs.h

395

u8 lspcon:1; /* 192 */

sys/dev/drm/i915/intel_vbt_defs.h

396

u8 iboost:1; /* 196 */

sys/dev/drm/i915/intel_vbt_defs.h

397

u8 hpd_invert:1; /* 196 */

sys/dev/drm/i915/intel_vbt_defs.h

398

u8 flag_reserved:3;

sys/dev/drm/i915/intel_vbt_defs.h

399

u8 hdmi_support:1; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

400

u8 dp_support:1; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

401

u8 tmds_support:1; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

402

u8 support_reserved:5;

sys/dev/drm/i915/intel_vbt_defs.h

403

u8 aux_channel;

sys/dev/drm/i915/intel_vbt_defs.h

404

u8 dongle_detect;

sys/dev/drm/i915/intel_vbt_defs.h

408

u8 pipe_cap:2;

sys/dev/drm/i915/intel_vbt_defs.h

409

u8 sdvo_stall:1; /* 158 */

sys/dev/drm/i915/intel_vbt_defs.h

410

u8 hpd_status:2;

sys/dev/drm/i915/intel_vbt_defs.h

411

u8 integrated_encoder:1;

sys/dev/drm/i915/intel_vbt_defs.h

412

u8 capabilities_reserved:2;

sys/dev/drm/i915/intel_vbt_defs.h

413

u8 dvo_wiring; /* See DEVICE_WIRE_* above */

sys/dev/drm/i915/intel_vbt_defs.h

416

u8 dvo2_wiring;

sys/dev/drm/i915/intel_vbt_defs.h

417

u8 mipi_bridge_type; /* 171 */

sys/dev/drm/i915/intel_vbt_defs.h

421

u8 dvo_function;

sys/dev/drm/i915/intel_vbt_defs.h

422

u8 dp_usb_type_c:1; /* 195 */

sys/dev/drm/i915/intel_vbt_defs.h

423

u8 tbt:1; /* 209 */

sys/dev/drm/i915/intel_vbt_defs.h

424

u8 flags2_reserved:2; /* 195 */

sys/dev/drm/i915/intel_vbt_defs.h

425

u8 dp_port_trace_length:4; /* 209 */

sys/dev/drm/i915/intel_vbt_defs.h

426

u8 dp_gpio_index; /* 195 */

sys/dev/drm/i915/intel_vbt_defs.h

428

u8 dp_iboost_level:4; /* 196 */

sys/dev/drm/i915/intel_vbt_defs.h

429

u8 hdmi_iboost_level:4; /* 196 */

sys/dev/drm/i915/intel_vbt_defs.h

430

u8 dp_max_link_rate:2; /* 216 CNL+ */

sys/dev/drm/i915/intel_vbt_defs.h

431

u8 dp_max_link_rate_reserved:6; /* 216 */

sys/dev/drm/i915/intel_vbt_defs.h

436

u8 crt_ddc_gmbus_pin;

sys/dev/drm/i915/intel_vbt_defs.h

439

u8 dpms_acpi:1;

sys/dev/drm/i915/intel_vbt_defs.h

440

u8 skip_boot_crt_detect:1;

sys/dev/drm/i915/intel_vbt_defs.h

441

u8 dpms_aim:1;

sys/dev/drm/i915/intel_vbt_defs.h

442

u8 rsvd1:5; /* finish byte */

sys/dev/drm/i915/intel_vbt_defs.h

445

u8 boot_display[2];

sys/dev/drm/i915/intel_vbt_defs.h

446

u8 child_dev_size;

sys/dev/drm/i915/intel_vbt_defs.h

459

u8 devices[0];

sys/dev/drm/i915/intel_vbt_defs.h

466

u8 panel_type;

sys/dev/drm/i915/intel_vbt_defs.h

467

u8 rsvd1;

sys/dev/drm/i915/intel_vbt_defs.h

469

u8 pfit_mode:2;

sys/dev/drm/i915/intel_vbt_defs.h

470

u8 pfit_text_mode_enhanced:1;

sys/dev/drm/i915/intel_vbt_defs.h

471

u8 pfit_gfx_mode_enhanced:1;

sys/dev/drm/i915/intel_vbt_defs.h

472

u8 pfit_ratio_auto:1;

sys/dev/drm/i915/intel_vbt_defs.h

473

u8 pixel_dither:1;

sys/dev/drm/i915/intel_vbt_defs.h

474

u8 lvds_edid:1;

sys/dev/drm/i915/intel_vbt_defs.h

475

u8 rsvd2:1;

sys/dev/drm/i915/intel_vbt_defs.h

476

u8 rsvd4;

sys/dev/drm/i915/intel_vbt_defs.h

494

u8 fp_table_size;

sys/dev/drm/i915/intel_vbt_defs.h

496

u8 dvo_table_size;

sys/dev/drm/i915/intel_vbt_defs.h

498

u8 pnp_table_size;

sys/dev/drm/i915/intel_vbt_defs.h

502

u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */

sys/dev/drm/i915/intel_vbt_defs.h

525

u8 hactive_lo;

sys/dev/drm/i915/intel_vbt_defs.h

526

u8 hblank_lo;

sys/dev/drm/i915/intel_vbt_defs.h

527

u8 hblank_hi:4;

sys/dev/drm/i915/intel_vbt_defs.h

528

u8 hactive_hi:4;

sys/dev/drm/i915/intel_vbt_defs.h

529

u8 vactive_lo;

sys/dev/drm/i915/intel_vbt_defs.h

530

u8 vblank_lo;

sys/dev/drm/i915/intel_vbt_defs.h

531

u8 vblank_hi:4;

sys/dev/drm/i915/intel_vbt_defs.h

532

u8 vactive_hi:4;

sys/dev/drm/i915/intel_vbt_defs.h

533

u8 hsync_off_lo;

sys/dev/drm/i915/intel_vbt_defs.h

534

u8 hsync_pulse_width_lo;

sys/dev/drm/i915/intel_vbt_defs.h

535

u8 vsync_pulse_width_lo:4;

sys/dev/drm/i915/intel_vbt_defs.h

536

u8 vsync_off_lo:4;

sys/dev/drm/i915/intel_vbt_defs.h

537

u8 vsync_pulse_width_hi:2;

sys/dev/drm/i915/intel_vbt_defs.h

538

u8 vsync_off_hi:2;

sys/dev/drm/i915/intel_vbt_defs.h

539

u8 hsync_pulse_width_hi:2;

sys/dev/drm/i915/intel_vbt_defs.h

54

u8 signature[20];

sys/dev/drm/i915/intel_vbt_defs.h

540

u8 hsync_off_hi:2;

sys/dev/drm/i915/intel_vbt_defs.h

541

u8 himage_lo;

sys/dev/drm/i915/intel_vbt_defs.h

542

u8 vimage_lo;

sys/dev/drm/i915/intel_vbt_defs.h

543

u8 vimage_hi:4;

sys/dev/drm/i915/intel_vbt_defs.h

544

u8 himage_hi:4;

sys/dev/drm/i915/intel_vbt_defs.h

545

u8 h_border;

sys/dev/drm/i915/intel_vbt_defs.h

546

u8 v_border;

sys/dev/drm/i915/intel_vbt_defs.h

547

u8 rsvd1:3;

sys/dev/drm/i915/intel_vbt_defs.h

548

u8 digital:2;

sys/dev/drm/i915/intel_vbt_defs.h

549

u8 vsync_positive:1;

sys/dev/drm/i915/intel_vbt_defs.h

550

u8 hsync_positive:1;

sys/dev/drm/i915/intel_vbt_defs.h

551

u8 non_interlaced:1;

sys/dev/drm/i915/intel_vbt_defs.h

558

u8 mfg_week;

sys/dev/drm/i915/intel_vbt_defs.h

559

u8 mfg_year;

sys/dev/drm/i915/intel_vbt_defs.h

576

u8 type:2;

sys/dev/drm/i915/intel_vbt_defs.h

577

u8 active_low_pwm:1;

sys/dev/drm/i915/intel_vbt_defs.h

578

u8 obsolete1:5;

sys/dev/drm/i915/intel_vbt_defs.h

58

u8 vbt_checksum;

sys/dev/drm/i915/intel_vbt_defs.h

580

u8 min_brightness;

sys/dev/drm/i915/intel_vbt_defs.h

581

u8 obsolete2;

sys/dev/drm/i915/intel_vbt_defs.h

582

u8 obsolete3;

sys/dev/drm/i915/intel_vbt_defs.h

586

u8 type:4;

sys/dev/drm/i915/intel_vbt_defs.h

587

u8 controller:4;

sys/dev/drm/i915/intel_vbt_defs.h

59

u8 reserved0;

sys/dev/drm/i915/intel_vbt_defs.h

591

u8 entry_size;

sys/dev/drm/i915/intel_vbt_defs.h

593

u8 level[16];

sys/dev/drm/i915/intel_vbt_defs.h

606

u8 aimdb_id;

sys/dev/drm/i915/intel_vbt_defs.h

612

u8 fp_timing_size;

sys/dev/drm/i915/intel_vbt_defs.h

614

u8 dvo_timing_size;

sys/dev/drm/i915/intel_vbt_defs.h

616

u8 text_fitting_size;

sys/dev/drm/i915/intel_vbt_defs.h

618

u8 graphics_fitting_size;

sys/dev/drm/i915/intel_vbt_defs.h

627

u8 panel_backlight;

sys/dev/drm/i915/intel_vbt_defs.h

628

u8 h40_set_panel_type;

sys/dev/drm/i915/intel_vbt_defs.h

629

u8 panel_type;

sys/dev/drm/i915/intel_vbt_defs.h

630

u8 ssc_clk_freq;

sys/dev/drm/i915/intel_vbt_defs.h

633

u8 sclalarcoeff_tab_row_num;

sys/dev/drm/i915/intel_vbt_defs.h

634

u8 sclalarcoeff_tab_row_size;

sys/dev/drm/i915/intel_vbt_defs.h

635

u8 coefficient[8];

sys/dev/drm/i915/intel_vbt_defs.h

636

u8 panel_misc_bits_1;

sys/dev/drm/i915/intel_vbt_defs.h

637

u8 panel_misc_bits_2;

sys/dev/drm/i915/intel_vbt_defs.h

638

u8 panel_misc_bits_3;

sys/dev/drm/i915/intel_vbt_defs.h

639

u8 panel_misc_bits_4;

sys/dev/drm/i915/intel_vbt_defs.h

649

u8 boot_dev_algorithm:1;

sys/dev/drm/i915/intel_vbt_defs.h

650

u8 block_display_switch:1;

sys/dev/drm/i915/intel_vbt_defs.h

651

u8 allow_display_switch:1;

sys/dev/drm/i915/intel_vbt_defs.h

652

u8 hotplug_dvo:1;

sys/dev/drm/i915/intel_vbt_defs.h

653

u8 dual_view_zoom:1;

sys/dev/drm/i915/intel_vbt_defs.h

654

u8 int15h_hook:1;

sys/dev/drm/i915/intel_vbt_defs.h

655

u8 sprite_in_clone:1;

sys/dev/drm/i915/intel_vbt_defs.h

656

u8 primary_lfp_id:1;

sys/dev/drm/i915/intel_vbt_defs.h

660

u8 boot_mode_bpp;

sys/dev/drm/i915/intel_vbt_defs.h

661

u8 boot_mode_refresh;

sys/dev/drm/i915/intel_vbt_defs.h

678

u8 static_display:1;

sys/dev/drm/i915/intel_vbt_defs.h

679

u8 reserved2:7;

sys/dev/drm/i915/intel_vbt_defs.h

682

u8 legacy_crt_max_refresh;

sys/dev/drm/i915/intel_vbt_defs.h

684

u8 hdmi_termination;

sys/dev/drm/i915/intel_vbt_defs.h

685

u8 custom_vbt_version;

sys/dev/drm/i915/intel_vbt_defs.h

72

u8 signature[16];

sys/dev/drm/i915/intel_vbt_defs.h

721

u8 rate:4;

sys/dev/drm/i915/intel_vbt_defs.h

722

u8 lanes:4;

sys/dev/drm/i915/intel_vbt_defs.h

723

u8 preemphasis:4;

sys/dev/drm/i915/intel_vbt_defs.h

724

u8 vswing:4;

sys/dev/drm/i915/intel_vbt_defs.h

733

u8 preemphasis:4;

sys/dev/drm/i915/intel_vbt_defs.h

734

u8 vswing:4;

sys/dev/drm/i915/intel_vbt_defs.h

756

u8 full_link:1;

sys/dev/drm/i915/intel_vbt_defs.h

757

u8 require_aux_to_wakeup:1;

sys/dev/drm/i915/intel_vbt_defs.h

758

u8 feature_bits_rsvd:6;

sys/dev/drm/i915/intel_vbt_defs.h

761

u8 idle_frames:4;

sys/dev/drm/i915/intel_vbt_defs.h

762

u8 lines_to_wait:3;

sys/dev/drm/i915/intel_vbt_defs.h

763

u8 wait_times_rsvd:1;

sys/dev/drm/i915/intel_vbt_defs.h

80

u8 type; /* 0 == desktop, 1 == mobile */

sys/dev/drm/i915/intel_vbt_defs.h

81

u8 relstage;

sys/dev/drm/i915/intel_vbt_defs.h

82

u8 chipset;

sys/dev/drm/i915/intel_vbt_defs.h

83

u8 lvds_present:1;

sys/dev/drm/i915/intel_vbt_defs.h

84

u8 tv_present:1;

sys/dev/drm/i915/intel_vbt_defs.h

85

u8 rsvd2:6; /* finish byte */

sys/dev/drm/i915/intel_vbt_defs.h

86

u8 rsvd3[4];

sys/dev/drm/i915/intel_vbt_defs.h

87

u8 signon[155];

sys/dev/drm/i915/intel_vbt_defs.h

88

u8 copyright[61];

sys/dev/drm/i915/intel_vbt_defs.h

90

u8 dos_boot_mode;

sys/dev/drm/i915/intel_vbt_defs.h

91

u8 bandwidth_percent;

sys/dev/drm/i915/intel_vbt_defs.h

911

u8 version;

sys/dev/drm/i915/intel_vbt_defs.h

912

u8 data[0];

sys/dev/drm/i915/intel_vbt_defs.h

92

u8 rsvd4; /* popup memory size */

sys/dev/drm/i915/intel_vbt_defs.h

93

u8 resize_pci_bios;

sys/dev/drm/i915/intel_vbt_defs.h

94

u8 rsvd5; /* is crt already on ddc2 */

sys/dev/drm/i915/intel_workarounds.c

325

u8 vals[3] = { 0, 0, 0 };

sys/dev/drm/i915/intel_workarounds.c

329

u8 ss;

sys/dev/drm/i915/intel_workarounds.c

789

u8 ss_mask = sseu->subslice_mask[slice];

sys/dev/drm/i915/intel_workarounds.c

791

u8 enabled_mask = (ss_mask | ss_mask >>

sys/dev/drm/i915/intel_workarounds.c

793

u8 disabled_mask = fuse3 & GEN10_L3BANK_MASK;

sys/dev/drm/i915/vlv_dsi.c

106

u8 *data, u32 len)

sys/dev/drm/i915/vlv_dsi.c

127

const u8 *header, *data;

sys/dev/drm/i915/vlv_dsi.c

90

const u8 *data, u32 len)

sys/dev/drm/i915/vlv_dsi_pll.c

479

u8 dsi_ratio, dsi_ratio_min, dsi_ratio_max;

sys/dev/drm/include/asm/io.h

164

outb(u8 value, u_int port)

sys/dev/drm/include/asm/io.h

39

static inline u8

sys/dev/drm/include/asm/io.h

42

return *(const volatile u8*)addr;

sys/dev/drm/include/asm/io.h

61

writeb(u8 value, volatile void __iomem *addr)

sys/dev/drm/include/drm/drm_connector.h

1286

u8 group_data[8];

sys/dev/drm/include/drm/drm_connector.h

208

u8 y420_dc_modes;

sys/dev/drm/include/drm/drm_connector.h

372

u8 edid_hdmi_dc_modes;

sys/dev/drm/include/drm/drm_connector.h

377

u8 cea_rev;

sys/dev/drm/include/drm/drm_displayid.h

55

u8 rev;

sys/dev/drm/include/drm/drm_displayid.h

56

u8 bytes;

sys/dev/drm/include/drm/drm_displayid.h

57

u8 prod_id;

sys/dev/drm/include/drm/drm_displayid.h

58

u8 ext_count;

sys/dev/drm/include/drm/drm_displayid.h

62

u8 tag;

sys/dev/drm/include/drm/drm_displayid.h

63

u8 rev;

sys/dev/drm/include/drm/drm_displayid.h

64

u8 num_bytes;

sys/dev/drm/include/drm/drm_displayid.h

69

u8 tile_cap;

sys/dev/drm/include/drm/drm_displayid.h

70

u8 topo[3];

sys/dev/drm/include/drm/drm_displayid.h

71

u8 tile_size[4];

sys/dev/drm/include/drm/drm_displayid.h

72

u8 tile_pixel_bezel[5];

sys/dev/drm/include/drm/drm_displayid.h

73

u8 topology_id[8];

sys/dev/drm/include/drm/drm_displayid.h

77

u8 pixel_clock[3];

sys/dev/drm/include/drm/drm_displayid.h

78

u8 flags;

sys/dev/drm/include/drm/drm_displayid.h

79

u8 hactive[2];

sys/dev/drm/include/drm/drm_displayid.h

80

u8 hblank[2];

sys/dev/drm/include/drm/drm_displayid.h

81

u8 hsync[2];

sys/dev/drm/include/drm/drm_displayid.h

82

u8 hsw[2];

sys/dev/drm/include/drm/drm_displayid.h

83

u8 vactive[2];

sys/dev/drm/include/drm/drm_displayid.h

84

u8 vblank[2];

sys/dev/drm/include/drm/drm_displayid.h

85

u8 vsync[2];

sys/dev/drm/include/drm/drm_displayid.h

86

u8 vsw[2];

sys/dev/drm/include/drm/drm_dp_dual_mode_helper.h

68

u8 offset, void *buffer, size_t size);

sys/dev/drm/include/drm/drm_dp_dual_mode_helper.h

70

u8 offset, const void *buffer, size_t size);

sys/dev/drm/include/drm/drm_dp_helper.h

1000

u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */

sys/dev/drm/include/drm/drm_dp_helper.h

1001

u8 DB2; /* CRC value bits 7:0 of the R or Cr component */

sys/dev/drm/include/drm/drm_dp_helper.h

1002

u8 DB3; /* CRC value bits 15:8 of the R or Cr component */

sys/dev/drm/include/drm/drm_dp_helper.h

1003

u8 DB4; /* CRC value bits 7:0 of the G or Y component */

sys/dev/drm/include/drm/drm_dp_helper.h

1004

u8 DB5; /* CRC value bits 15:8 of the G or Y component */

sys/dev/drm/include/drm/drm_dp_helper.h

1005

u8 DB6; /* CRC value bits 7:0 of the B or Cb component */

sys/dev/drm/include/drm/drm_dp_helper.h

1006

u8 DB7; /* CRC value bits 15:8 of the B or Cb component */

sys/dev/drm/include/drm/drm_dp_helper.h

1007

u8 DB8_31[24]; /* Reserved */

sys/dev/drm/include/drm/drm_dp_helper.h

1014

int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);

sys/dev/drm/include/drm/drm_dp_helper.h

1017

drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1022

static inline u8

sys/dev/drm/include/drm/drm_dp_helper.h

1023

drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1029

drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1036

drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1043

drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1049

static inline u8

sys/dev/drm/include/drm/drm_dp_helper.h

1050

drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1057

drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])

sys/dev/drm/include/drm/drm_dp_helper.h

1076

u8 request;

sys/dev/drm/include/drm/drm_dp_helper.h

1077

u8 reply;

sys/dev/drm/include/drm/drm_dp_helper.h

1148

u8 crc_count;

sys/dev/drm/include/drm/drm_dp_helper.h

1180

unsigned int offset, u8 *valuep)

sys/dev/drm/include/drm/drm_dp_helper.h

1195

unsigned int offset, u8 value)

sys/dev/drm/include/drm/drm_dp_helper.h

1201

u8 status[DP_LINK_STATUS_SIZE]);

sys/dev/drm/include/drm/drm_dp_helper.h

1219

int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

1220

const u8 port_cap[4]);

sys/dev/drm/include/drm/drm_dp_helper.h

1221

int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

1222

const u8 port_cap[4]);

sys/dev/drm/include/drm/drm_dp_helper.h

1224

void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

1225

const u8 port_cap[4], struct drm_dp_aux *aux);

sys/dev/drm/include/drm/drm_dp_helper.h

1235

u8 oui[3];

sys/dev/drm/include/drm/drm_dp_helper.h

1236

u8 device_id[6];

sys/dev/drm/include/drm/drm_dp_helper.h

1237

u8 hw_rev;

sys/dev/drm/include/drm/drm_dp_helper.h

1238

u8 sw_major_rev;

sys/dev/drm/include/drm/drm_dp_helper.h

1239

u8 sw_minor_rev;

sys/dev/drm/include/drm/drm_dp_helper.h

955

bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

957

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

959

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

961

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/include/drm/drm_dp_helper.h

969

void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/drm/include/drm/drm_dp_helper.h

970

void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);

sys/dev/drm/include/drm/drm_dp_helper.h

972

u8 drm_dp_link_rate_to_bw_code(int link_rate);

sys/dev/drm/include/drm/drm_dp_helper.h

973

int drm_dp_bw_code_to_link_rate(u8 link_bw);

sys/dev/drm/include/drm/drm_dp_helper.h

988

u8 HB0; /* Secondary Data Packet ID */

sys/dev/drm/include/drm/drm_dp_helper.h

989

u8 HB1; /* Secondary Data Packet Type */

sys/dev/drm/include/drm/drm_dp_helper.h

990

u8 HB2; /* Secondary Data Packet Specific header, Byte 0 */

sys/dev/drm/include/drm/drm_dp_helper.h

991

u8 HB3; /* Secondary Data packet Specific header, Byte 1 */

sys/dev/drm/include/drm/drm_dp_helper.h

999

u8 DB0; /* Stereo Interface */

sys/dev/drm/include/drm/drm_dp_mst_helper.h

125

u8 rad[8];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

126

u8 lct;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

142

u8 guid[16];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

148

u8 lct;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

149

u8 lcr;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

150

u8 rad[8];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

153

u8 msg_len;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

160

u8 guid[16];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

161

u8 reason;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

162

u8 nak_data;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

166

u8 guid[16];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

167

u8 nports;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

170

u8 peer_device_type;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

171

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

175

u8 dpcd_revision;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

176

u8 peer_guid[16];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

177

u8 num_sdp_streams;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

178

u8 num_sdp_stream_sinks;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

183

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

184

u8 num_bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

185

u8 bytes[255];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

189

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

193

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

194

u8 reason;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

195

u8 bytes_written_before_failure;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

199

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

200

u8 num_bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

201

u8 bytes[255];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

205

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

206

u8 nak_reason;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

207

u8 i2c_nak_transaction;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

211

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

216

u8 chunk[48];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

217

u8 msg[256];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

218

u8 curchunk_len;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

219

u8 curchunk_idx; /* chunk we are parsing now */

sys/dev/drm/include/drm/drm_dp_mst_helper.h

220

u8 curchunk_hdrlen;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

221

u8 curlen; /* total length of the msg */

sys/dev/drm/include/drm/drm_dp_mst_helper.h

229

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

230

u8 number_sdp_streams;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

231

u8 vcpi;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

233

u8 sdp_stream_sink[DRM_DP_MAX_SDP_STREAMS];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

237

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

238

u8 vcpi;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

243

u8 guid[16];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

244

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

249

u8 peer_device_type;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

253

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

255

u8 num_bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

259

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

261

u8 num_bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

262

u8 *bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

267

u8 num_transactions;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

268

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

270

u8 i2c_dev_id;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

271

u8 num_bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

272

u8 *bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

273

u8 no_stop_bit;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

274

u8 i2c_transaction_delay;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

276

u8 read_i2c_device_id;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

277

u8 num_bytes_read;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

281

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

282

u8 write_i2c_device_id;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

283

u8 num_bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

284

u8 *bytes;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

289

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

293

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

300

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

304

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

305

u8 vcpi;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

309

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

310

u8 guid[16];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

315

u8 port_number;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

316

u8 allocated_pbn;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

320

u8 req_type;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

338

u8 reply_type;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

339

u8 req_type;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

370

u8 msg[256];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

371

u8 chunk[48];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

372

u8 cur_offset;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

373

u8 cur_len;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

490

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/drm/include/drm/drm_dp_mst_helper.h

494

u8 sink_count;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

584

int drm_dp_mst_hpd_irq(struct drm_dp_mst_topology_mgr *mgr, u8 *esi, bool *handled);

sys/dev/drm/include/drm/drm_dp_mst_helper.h

72

u8 port_num;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

76

u8 pdt;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

78

u8 dpcd_rev;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

79

u8 num_sdp_streams;

sys/dev/drm/include/drm/drm_dp_mst_helper.h

80

u8 num_sdp_stream_sinks;

sys/dev/drm/include/drm/drm_edid.h

102

u8 reserved;

sys/dev/drm/include/drm/drm_edid.h

103

u8 hfreq_start_khz; /* need to multiply by 2 */

sys/dev/drm/include/drm/drm_edid.h

104

u8 c; /* need to divide by 2 */

sys/dev/drm/include/drm/drm_edid.h

106

u8 k;

sys/dev/drm/include/drm/drm_edid.h

107

u8 j; /* need to divide by 2 */

sys/dev/drm/include/drm/drm_edid.h

110

u8 version;

sys/dev/drm/include/drm/drm_edid.h

111

u8 data1; /* high 6 bits: extra clock resolution */

sys/dev/drm/include/drm/drm_edid.h

112

u8 data2; /* plus low 2 of above: max hactive */

sys/dev/drm/include/drm/drm_edid.h

113

u8 supported_aspects;

sys/dev/drm/include/drm/drm_edid.h

114

u8 flags; /* preferred aspect and blanking support */

sys/dev/drm/include/drm/drm_edid.h

115

u8 supported_scalings;

sys/dev/drm/include/drm/drm_edid.h

116

u8 preferred_refresh;

sys/dev/drm/include/drm/drm_edid.h

122

u8 white_yx_lo; /* Lower 2 bits each */

sys/dev/drm/include/drm/drm_edid.h

123

u8 white_x_hi;

sys/dev/drm/include/drm/drm_edid.h

124

u8 white_y_hi;

sys/dev/drm/include/drm/drm_edid.h

125

u8 gamma; /* need to divide by 100 then add 1 */

sys/dev/drm/include/drm/drm_edid.h

129

u8 windex1;

sys/dev/drm/include/drm/drm_edid.h

130

u8 wpindex1[3];

sys/dev/drm/include/drm/drm_edid.h

131

u8 windex2;

sys/dev/drm/include/drm/drm_edid.h

132

u8 wpindex2[3];

sys/dev/drm/include/drm/drm_edid.h

136

u8 code[3];

sys/dev/drm/include/drm/drm_edid.h

140

u8 pad1;

sys/dev/drm/include/drm/drm_edid.h

141

u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name

sys/dev/drm/include/drm/drm_edid.h

144

u8 pad2;

sys/dev/drm/include/drm/drm_edid.h

283

u8 header[8];

sys/dev/drm/include/drm/drm_edid.h

285

u8 mfg_id[2];

sys/dev/drm/include/drm/drm_edid.h

286

u8 prod_code[2];

sys/dev/drm/include/drm/drm_edid.h

288

u8 mfg_week;

sys/dev/drm/include/drm/drm_edid.h

289

u8 mfg_year;

sys/dev/drm/include/drm/drm_edid.h

291

u8 version;

sys/dev/drm/include/drm/drm_edid.h

292

u8 revision;

sys/dev/drm/include/drm/drm_edid.h

294

u8 input;

sys/dev/drm/include/drm/drm_edid.h

295

u8 width_cm;

sys/dev/drm/include/drm/drm_edid.h

296

u8 height_cm;

sys/dev/drm/include/drm/drm_edid.h

297

u8 gamma;

sys/dev/drm/include/drm/drm_edid.h

298

u8 features;

sys/dev/drm/include/drm/drm_edid.h

300

u8 red_green_lo;

sys/dev/drm/include/drm/drm_edid.h

301

u8 black_white_lo;

sys/dev/drm/include/drm/drm_edid.h

302

u8 red_x;

sys/dev/drm/include/drm/drm_edid.h

303

u8 red_y;

sys/dev/drm/include/drm/drm_edid.h

304

u8 green_x;

sys/dev/drm/include/drm/drm_edid.h

305

u8 green_y;

sys/dev/drm/include/drm/drm_edid.h

306

u8 blue_x;

sys/dev/drm/include/drm/drm_edid.h

307

u8 blue_y;

sys/dev/drm/include/drm/drm_edid.h

308

u8 white_x;

sys/dev/drm/include/drm/drm_edid.h

309

u8 white_y;

sys/dev/drm/include/drm/drm_edid.h

317

u8 extensions;

sys/dev/drm/include/drm/drm_edid.h

319

u8 checksum;

sys/dev/drm/include/drm/drm_edid.h

326

u8 format;

sys/dev/drm/include/drm/drm_edid.h

327

u8 channels; /* max number of channels - 1 */

sys/dev/drm/include/drm/drm_edid.h

328

u8 freq;

sys/dev/drm/include/drm/drm_edid.h

329

u8 byte2; /* meaning depends on format */

sys/dev/drm/include/drm/drm_edid.h

337

int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb);

sys/dev/drm/include/drm/drm_edid.h

44

u8 t1;

sys/dev/drm/include/drm/drm_edid.h

441

static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld)

sys/dev/drm/include/drm/drm_edid.h

45

u8 t2;

sys/dev/drm/include/drm/drm_edid.h

453

static inline u8 drm_eld_get_conn_type(const uint8_t *eld)

sys/dev/drm/include/drm/drm_edid.h

46

u8 mfg_rsvd;

sys/dev/drm/include/drm/drm_edid.h

460

int (*get_edid_block)(void *data, u8 *buf, unsigned int block,

sys/dev/drm/include/drm/drm_edid.h

470

u8 drm_match_cea_mode(const struct drm_display_mode *to_match);

sys/dev/drm/include/drm/drm_edid.h

471

enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code);

sys/dev/drm/include/drm/drm_edid.h

482

int drm_edid_header_is_valid(const u8 *raw_edid);

sys/dev/drm/include/drm/drm_edid.h

483

bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,

sys/dev/drm/include/drm/drm_edid.h

58

u8 hsize; /* need to multiply by 8 then add 248 */

sys/dev/drm/include/drm/drm_edid.h

59

u8 vfreq_aspect;

sys/dev/drm/include/drm/drm_edid.h

70

u8 hactive_lo;

sys/dev/drm/include/drm/drm_edid.h

71

u8 hblank_lo;

sys/dev/drm/include/drm/drm_edid.h

72

u8 hactive_hblank_hi;

sys/dev/drm/include/drm/drm_edid.h

73

u8 vactive_lo;

sys/dev/drm/include/drm/drm_edid.h

74

u8 vblank_lo;

sys/dev/drm/include/drm/drm_edid.h

75

u8 vactive_vblank_hi;

sys/dev/drm/include/drm/drm_edid.h

76

u8 hsync_offset_lo;

sys/dev/drm/include/drm/drm_edid.h

77

u8 hsync_pulse_width_lo;

sys/dev/drm/include/drm/drm_edid.h

78

u8 vsync_offset_pulse_width_lo;

sys/dev/drm/include/drm/drm_edid.h

79

u8 hsync_vsync_offset_pulse_width_hi;

sys/dev/drm/include/drm/drm_edid.h

80

u8 width_mm_lo;

sys/dev/drm/include/drm/drm_edid.h

81

u8 height_mm_lo;

sys/dev/drm/include/drm/drm_edid.h

82

u8 width_height_mm_hi;

sys/dev/drm/include/drm/drm_edid.h

83

u8 hborder;

sys/dev/drm/include/drm/drm_edid.h

84

u8 vborder;

sys/dev/drm/include/drm/drm_edid.h

85

u8 misc;

sys/dev/drm/include/drm/drm_edid.h

90

u8 str[13];

sys/dev/drm/include/drm/drm_edid.h

94

u8 min_vfreq;

sys/dev/drm/include/drm/drm_edid.h

95

u8 max_vfreq;

sys/dev/drm/include/drm/drm_edid.h

96

u8 min_hfreq_khz;

sys/dev/drm/include/drm/drm_edid.h

97

u8 max_hfreq_khz;

sys/dev/drm/include/drm/drm_edid.h

98

u8 pixel_clock_mhz; /* need to multiply by 10 */

sys/dev/drm/include/drm/drm_edid.h

99

u8 flags;

sys/dev/drm/include/drm/drm_fourcc.h

68

u8 depth;

sys/dev/drm/include/drm/drm_fourcc.h

69

u8 num_planes;

sys/dev/drm/include/drm/drm_fourcc.h

70

u8 cpp[3];

sys/dev/drm/include/drm/drm_fourcc.h

71

u8 hsub;

sys/dev/drm/include/drm/drm_fourcc.h

72

u8 vsub;

sys/dev/drm/include/drm/drm_hashtab.h

49

u8 order;

sys/dev/drm/include/drm/drm_mipi_dsi.h

252

ssize_t mipi_dsi_dcs_write(struct mipi_dsi_device *dsi, u8 cmd,

sys/dev/drm/include/drm/drm_mipi_dsi.h

254

ssize_t mipi_dsi_dcs_read(struct mipi_dsi_device *dsi, u8 cmd, void *data,

sys/dev/drm/include/drm/drm_mipi_dsi.h

258

int mipi_dsi_dcs_get_power_mode(struct mipi_dsi_device *dsi, u8 *mode);

sys/dev/drm/include/drm/drm_mipi_dsi.h

259

int mipi_dsi_dcs_get_pixel_format(struct mipi_dsi_device *dsi, u8 *format);

sys/dev/drm/include/drm/drm_mipi_dsi.h

271

int mipi_dsi_dcs_set_pixel_format(struct mipi_dsi_device *dsi, u8 format);

sys/dev/drm/include/drm/drm_mipi_dsi.h

36

u8 channel;

sys/dev/drm/include/drm/drm_mipi_dsi.h

37

u8 type;

sys/dev/drm/include/drm/drm_mipi_dsi.h

47

bool mipi_dsi_packet_format_is_short(u8 type);

sys/dev/drm/include/drm/drm_mipi_dsi.h

48

bool mipi_dsi_packet_format_is_long(u8 type);

sys/dev/drm/include/drm/drm_mipi_dsi.h

60

u8 header[4];

sys/dev/drm/include/drm/drm_mipi_dsi.h

62

const u8 *payload;

sys/dev/drm/include/drm/drm_scdc_helper.h

108

static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,

sys/dev/drm/include/drm/drm_scdc_helper.h

109

u8 *value)

sys/dev/drm/include/drm/drm_scdc_helper.h

126

static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,

sys/dev/drm/include/drm/drm_scdc_helper.h

127

u8 value)

sys/dev/drm/include/drm/drm_scdc_helper.h

91

ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,

sys/dev/drm/include/drm/drm_scdc_helper.h

93

ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,

sys/dev/drm/include/drm/intel_lpe_audio.h

35

u8 eld[HDMI_MAX_ELD_BYTES];

sys/dev/drm/include/linux/hdmi.h

294

u8 vic;

sys/dev/drm/include/linux/kernel.h

48

#define U8_MAX ((u8)~0U)

sys/dev/drm/include/linux/pci.h

122

pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val)

sys/dev/drm/include/linux/pci.h

124

*val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);

sys/dev/drm/include/linux/pci.h

143

pci_write_config_byte(struct pci_dev *pdev, int where, u8 val)

sys/dev/drm/include/linux/pci.h

316

pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)

sys/dev/drm/include/linux/pci.h

320

*val = (u8)pci_read_config(pdev->dev.bsddev, where, 1);

sys/dev/drm/linux_hdmi.c

1013

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

1076

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

1114

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

1160

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

1163

u8 hdmi_video_format;

sys/dev/drm/linux_hdmi.c

1226

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

195

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

260

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

34

static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size)

sys/dev/drm/linux_hdmi.c

341

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

36

u8 csum = 0;

sys/dev/drm/linux_hdmi.c

48

u8 *ptr = buffer;

sys/dev/drm/linux_hdmi.c

747

u8 buf[17];

sys/dev/drm/linux_hdmi.c

88

u8 *ptr = buffer;

sys/dev/drm/radeon/atombios_crtc.c

677

u8 frev, crev;

sys/dev/drm/radeon/atombios_crtc.c

774

u8 frev, crev;

sys/dev/drm/radeon/atombios_crtc.c

836

u8 frev, crev;

sys/dev/drm/radeon/atombios_dp.c

164

u8 tx_buf[20];

sys/dev/drm/radeon/atombios_dp.c

166

u8 ack, delay = 0;

sys/dev/drm/radeon/atombios_dp.c

256

static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

sys/dev/drm/radeon/atombios_dp.c

258

u8 train_set[4])

sys/dev/drm/radeon/atombios_dp.c

260

u8 v = 0;

sys/dev/drm/radeon/atombios_dp.c

261

u8 p = 0;

sys/dev/drm/radeon/atombios_dp.c

265

u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);

sys/dev/drm/radeon/atombios_dp.c

266

u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

sys/dev/drm/radeon/atombios_dp.c

306

const u8 dpcd[DP_DPCD_SIZE],

sys/dev/drm/radeon/atombios_dp.c

342

static u8 radeon_dp_encoder_service(struct radeon_device *rdev,

sys/dev/drm/radeon/atombios_dp.c

344

u8 ucconfig, u8 lane_num)

sys/dev/drm/radeon/atombios_dp.c

360

u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)

sys/dev/drm/radeon/atombios_dp.c

372

u8 buf[3];

sys/dev/drm/radeon/atombios_dp.c

389

u8 msg[DP_DPCD_SIZE];

sys/dev/drm/radeon/atombios_dp.c

418

u8 tmp;

sys/dev/drm/radeon/atombios_dp.c

508

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/drm/radeon/atombios_dp.c

520

u8 power_state)

sys/dev/drm/radeon/atombios_dp.c

547

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/drm/radeon/atombios_dp.c

548

u8 train_set[4];

sys/dev/drm/radeon/atombios_dp.c

549

u8 link_status[DP_LINK_STATUS_SIZE];

sys/dev/drm/radeon/atombios_dp.c

550

u8 tries;

sys/dev/drm/radeon/atombios_dp.c

57

void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)

sys/dev/drm/radeon/atombios_dp.c

606

u8 tmp;

sys/dev/drm/radeon/atombios_dp.c

62

u8 align_num_bytes = ALIGN(num_bytes, 4);

sys/dev/drm/radeon/atombios_dp.c

671

u8 voltage;

sys/dev/drm/radeon/atombios_dp.c

797

u8 tmp, frev, crev;

sys/dev/drm/radeon/atombios_dp.c

86

u8 *send, int send_bytes,

sys/dev/drm/radeon/atombios_dp.c

87

u8 *recv, int recv_size,

sys/dev/drm/radeon/atombios_dp.c

88

u8 delay, u8 *ack)

sys/dev/drm/radeon/atombios_encoders.c

140

static u8 radeon_atom_bl_level(struct backlight_device *bd)

sys/dev/drm/radeon/atombios_encoders.c

142

u8 level;

sys/dev/drm/radeon/atombios_encoders.c

1502

u8 frev, crev;

sys/dev/drm/radeon/atombios_encoders.c

36

static u8

sys/dev/drm/radeon/atombios_encoders.c

39

u8 backlight_level;

sys/dev/drm/radeon/atombios_encoders.c

512

static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)

sys/dev/drm/radeon/atombios_encoders.c

55

u8 backlight_level)

sys/dev/drm/radeon/atombios_encoders.c

74

u8

sys/dev/drm/radeon/atombios_encoders.c

87

atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)

sys/dev/drm/radeon/atombios_i2c.c

113

u8 flags;

sys/dev/drm/radeon/atombios_i2c.c

37

u8 slave_addr, u8 flags,

sys/dev/drm/radeon/atombios_i2c.c

38

u8 *buf, u8 num)

sys/dev/drm/radeon/btc_dpm.c

1683

(u8 *)table,

sys/dev/drm/radeon/btc_dpm.c

1900

u8 i, j;

sys/dev/drm/radeon/btc_dpm.c

1917

u8 i, j, k;

sys/dev/drm/radeon/btc_dpm.c

1990

u8 i, j;

sys/dev/drm/radeon/btc_dpm.c

2020

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/drm/radeon/ci_dpm.c

1056

(u8 *)(&fan_table),

sys/dev/drm/radeon/ci_dpm.c

1364

(u8 *)&low_sclk_interrupt_t,

sys/dev/drm/radeon/ci_dpm.c

169

extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);

sys/dev/drm/radeon/ci_dpm.c

2486

static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/ci_dpm.c

2503

return (u8)i;

sys/dev/drm/radeon/ci_dpm.c

2575

arb_regs->McArbBurstTime = (u8)burst_time;

sys/dev/drm/radeon/ci_dpm.c

2603

(u8 *)&arb_regs,

sys/dev/drm/radeon/ci_dpm.c

262

static u8 ci_convert_to_vid(u16 vddc)

sys/dev/drm/radeon/ci_dpm.c

2669

(u8)dpm_table->pcie_speed_table.dpm_levels[i].value;

sys/dev/drm/radeon/ci_dpm.c

2677

pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;

sys/dev/drm/radeon/ci_dpm.c

270

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/radeon/ci_dpm.c

2707

table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

271

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/radeon/ci_dpm.c

2715

table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

272

u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;

sys/dev/drm/radeon/ci_dpm.c

2748

table->VceLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2765

table->AcpLevelCount = (u8)

sys/dev/drm/radeon/ci_dpm.c

2781

table->AcpLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

2813

table->SamuLevel[count].Divider = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

299

u8 *vid = pi->smc_powertune_table.VddCVid;

sys/dev/drm/radeon/ci_dpm.c

3052

table->ACPILevel.SclkDid = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

3180

state->VddcOffsetVid = (u8)

sys/dev/drm/radeon/ci_dpm.c

3244

sclk->SclkDid = (u8)dividers.post_divider;

sys/dev/drm/radeon/ci_dpm.c

3338

pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/drm/radeon/ci_dpm.c

3343

(u8 *)levels, level_array_size,

sys/dev/drm/radeon/ci_dpm.c

3392

pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;

sys/dev/drm/radeon/ci_dpm.c

3400

(u8 *)levels, level_array_size,

sys/dev/drm/radeon/ci_dpm.c

3728

(u8 *)&table->SystemFlags,

sys/dev/drm/radeon/ci_dpm.c

377

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/radeon/ci_dpm.c

378

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/radeon/ci_dpm.c

400

pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/drm/radeon/ci_dpm.c

401

pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;

sys/dev/drm/radeon/ci_dpm.c

4133

static u8 ci_get_vce_boot_level(struct radeon_device *rdev)

sys/dev/drm/radeon/ci_dpm.c

4135

u8 i;

sys/dev/drm/radeon/ci_dpm.c

4374

u8 i, j, k;

sys/dev/drm/radeon/ci_dpm.c

438

dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;

sys/dev/drm/radeon/ci_dpm.c

440

(u8)(pi->thermal_temp_setting.temperature_high / 1000);

sys/dev/drm/radeon/ci_dpm.c

4516

u8 i, j;

sys/dev/drm/radeon/ci_dpm.c

4544

u8 i, j;

sys/dev/drm/radeon/ci_dpm.c

4571

u8 i, k;

sys/dev/drm/radeon/ci_dpm.c

4663

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/drm/radeon/ci_dpm.c

4733

mc_reg_table->last = (u8)i;

sys/dev/drm/radeon/ci_dpm.c

4798

(u8 *)&pi->smc_mc_reg_table,

sys/dev/drm/radeon/ci_dpm.c

4817

(u8 *)&pi->smc_mc_reg_table.data[0],

sys/dev/drm/radeon/ci_dpm.c

4929

u8 request;

sys/dev/drm/radeon/ci_dpm.c

509

(u8 *)&pi->smc_powertune_table,

sys/dev/drm/radeon/ci_dpm.c

5486

u8 table_rev)

sys/dev/drm/radeon/ci_dpm.c

5588

u8 frev, crev;

sys/dev/drm/radeon/ci_dpm.c

5589

u8 *power_state_offset;

sys/dev/drm/radeon/ci_dpm.c

5612

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/radeon/ci_dpm.c

5615

u8 *idx;

sys/dev/drm/radeon/ci_dpm.c

5634

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/radeon/ci_dpm.c

5642

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/radeon/ci_dpm.c

5682

u8 frev, crev;

sys/dev/drm/radeon/ci_dpm.c

5722

u8 frev, crev;

sys/dev/drm/radeon/ci_dpm.h

176

u8 svi_load_line_en;

sys/dev/drm/radeon/ci_dpm.h

177

u8 svi_load_line_vddc;

sys/dev/drm/radeon/ci_dpm.h

178

u8 tdc_vddc_throttle_release_limit_perc;

sys/dev/drm/radeon/ci_dpm.h

179

u8 tdc_mawt;

sys/dev/drm/radeon/ci_dpm.h

180

u8 tdc_waterfall_ctl;

sys/dev/drm/radeon/ci_dpm.h

181

u8 dte_ambient_temp_base;

sys/dev/drm/radeon/ci_dpm.h

326

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/radeon/ci_dpm.h

82

u8 last;

sys/dev/drm/radeon/ci_dpm.h

83

u8 num_entries;

sys/dev/drm/radeon/ci_smc.c

132

static const u8 data[] = { 0xE0, 0x00, 0x80, 0x40 };

sys/dev/drm/radeon/ci_smc.c

191

const u8 *src;

sys/dev/drm/radeon/ci_smc.c

205

src = (const u8 *)

sys/dev/drm/radeon/ci_smc.c

222

src = (const u8 *)rdev->smc_fw->data;

sys/dev/drm/radeon/ci_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/radeon/cik.c

7572

u8 me_id, pipe_id, queue_id;

sys/dev/drm/radeon/cypress_dpm.c

1031

eg_pi->mc_reg_table.last = (u8)i;

sys/dev/drm/radeon/cypress_dpm.c

1077

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1092

static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)

sys/dev/drm/radeon/cypress_dpm.c

1578

u8 module_index;

sys/dev/drm/radeon/cypress_dpm.c

1663

(u8 *)table, sizeof(RV770_SMC_STATETABLE),

sys/dev/drm/radeon/cypress_dpm.c

1691

(u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),

sys/dev/drm/radeon/cypress_dpm.c

301

u8 perf_req, bool advertise)

sys/dev/drm/radeon/cypress_dpm.c

367

u8 request;

sys/dev/drm/radeon/cypress_dpm.c

389

u8 request;

sys/dev/drm/radeon/cypress_dpm.c

411

voltage->index = (u8)i;

sys/dev/drm/radeon/cypress_dpm.c

423

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/drm/radeon/cypress_dpm.c

426

u8 result = 0;

sys/dev/drm/radeon/cypress_dpm.c

614

u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,

sys/dev/drm/radeon/cypress_dpm.c

617

u8 mc_para_index;

sys/dev/drm/radeon/cypress_dpm.c

626

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/drm/radeon/cypress_dpm.c

633

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/drm/radeon/cypress_dpm.c

642

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/drm/radeon/cypress_dpm.c

649

mc_para_index = (u8)((memory_clock - 40000) / 5000);

sys/dev/drm/radeon/cypress_dpm.c

682

u8 watermark_level)

sys/dev/drm/radeon/cypress_dpm.c

883

return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,

sys/dev/drm/radeon/cypress_dpm.c

902

(u8 *)&mc_reg_table.data[2],

sys/dev/drm/radeon/cypress_dpm.c

967

mc_reg_table->last = (u8)i;

sys/dev/drm/radeon/cypress_dpm.h

116

u8 watermark_level);

sys/dev/drm/radeon/cypress_dpm.h

156

u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,

sys/dev/drm/radeon/cypress_dpm.h

158

u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk);

sys/dev/drm/radeon/cypress_dpm.h

35

u8 last;

sys/dev/drm/radeon/cypress_dpm.h

36

u8 num_entries;

sys/dev/drm/radeon/cypress_dpm.h

80

u8 mvdd_high_index;

sys/dev/drm/radeon/cypress_dpm.h

81

u8 mvdd_low_index;

sys/dev/drm/radeon/dce3_1_afmt.c

31

u8 *sadb, int sad_count);

sys/dev/drm/radeon/dce3_1_afmt.c

33

u8 *sadb, int sad_count)

sys/dev/drm/radeon/dce3_1_afmt.c

51

u8 *sadb, int sad_count);

sys/dev/drm/radeon/dce3_1_afmt.c

53

u8 *sadb, int sad_count)

sys/dev/drm/radeon/dce3_1_afmt.c

94

u8 stereo_freqs = 0;

sys/dev/drm/radeon/dce6_afmt.c

162

u8 *sadb, int sad_count);

sys/dev/drm/radeon/dce6_afmt.c

164

u8 *sadb, int sad_count)

sys/dev/drm/radeon/dce6_afmt.c

189

u8 *sadb, int sad_count);

sys/dev/drm/radeon/dce6_afmt.c

191

u8 *sadb, int sad_count)

sys/dev/drm/radeon/dce6_afmt.c

242

u8 stereo_freqs = 0;

sys/dev/drm/radeon/dce6_afmt.c

272

u8 enable_mask)

sys/dev/drm/radeon/evergreen_hdmi.c

127

u8 *sadb, int sad_count);

sys/dev/drm/radeon/evergreen_hdmi.c

129

u8 *sadb, int sad_count)

sys/dev/drm/radeon/evergreen_hdmi.c

147

u8 *sadb, int sad_count);

sys/dev/drm/radeon/evergreen_hdmi.c

149

u8 *sadb, int sad_count)

sys/dev/drm/radeon/evergreen_hdmi.c

190

u8 stereo_freqs = 0;

sys/dev/drm/radeon/evergreen_hdmi.c

39

u8 enable_mask);

sys/dev/drm/radeon/evergreen_hdmi.c

42

u8 enable_mask)

sys/dev/drm/radeon/kv_dpm.c

1004

(u8 *)&pi->samu_level,

sys/dev/drm/radeon/kv_dpm.c

1035

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

1043

(u8 *)&pi->acp_level_count,

sys/dev/drm/radeon/kv_dpm.c

1044

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

1054

(u8 *)&pi->acp_interval,

sys/dev/drm/radeon/kv_dpm.c

1055

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

1063

(u8 *)&pi->acp_level,

sys/dev/drm/radeon/kv_dpm.c

1336

(u8 *)&value, sizeof(u16), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1369

(u8 *)&pi->fps_high_t,

sys/dev/drm/radeon/kv_dpm.c

1378

(u8 *)&pi->fps_low_t,

sys/dev/drm/radeon/kv_dpm.c

1444

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1456

static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk)

sys/dev/drm/radeon/kv_dpm.c

1458

u8 i;

sys/dev/drm/radeon/kv_dpm.c

1491

(u8 *)&pi->vce_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1492

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

1529

(u8 *)&pi->samu_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1530

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

1544

static u8 kv_get_acp_boot_level(struct radeon_device *rdev)

sys/dev/drm/radeon/kv_dpm.c

1546

u8 i;

sys/dev/drm/radeon/kv_dpm.c

1564

u8 acp_boot_level;

sys/dev/drm/radeon/kv_dpm.c

1593

(u8 *)&pi->acp_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1594

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

1770

u8 clk_bypass_cntl;

sys/dev/drm/radeon/kv_dpm.c

1781

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

2076

static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/kv_dpm.c

2097

return (u8)i;

sys/dev/drm/radeon/kv_dpm.c

2491

u8 frev, crev;

sys/dev/drm/radeon/kv_dpm.c

2582

u8 table_rev)

sys/dev/drm/radeon/kv_dpm.c

2641

u8 frev, crev;

sys/dev/drm/radeon/kv_dpm.c

2642

u8 *power_state_offset;

sys/dev/drm/radeon/kv_dpm.c

2664

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/radeon/kv_dpm.c

2666

u8 *idx;

sys/dev/drm/radeon/kv_dpm.c

2680

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/radeon/kv_dpm.c

2688

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/radeon/kv_dpm.c

485

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

501

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

515

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

542

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

616

pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;

sys/dev/drm/radeon/kv_dpm.c

705

(u8 *)&low_sclk_interrupt_t,

sys/dev/drm/radeon/kv_dpm.c

724

pi->graphics_boot_level = (u8)i;

sys/dev/drm/radeon/kv_dpm.c

738

pi->graphics_boot_level = (u8)i;

sys/dev/drm/radeon/kv_dpm.c

755

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

768

(u8 *)&pi->graphics_level,

sys/dev/drm/radeon/kv_dpm.c

779

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

837

(u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);

sys/dev/drm/radeon/kv_dpm.c

839

(u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);

sys/dev/drm/radeon/kv_dpm.c

845

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

851

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

859

(u8 *)&pi->uvd_level_count,

sys/dev/drm/radeon/kv_dpm.c

860

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

870

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

877

(u8 *)&pi->uvd_level,

sys/dev/drm/radeon/kv_dpm.c

907

(u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);

sys/dev/drm/radeon/kv_dpm.c

913

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

921

(u8 *)&pi->vce_level_count,

sys/dev/drm/radeon/kv_dpm.c

922

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

932

(u8 *)&pi->vce_interval,

sys/dev/drm/radeon/kv_dpm.c

933

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

941

(u8 *)&pi->vce_level,

sys/dev/drm/radeon/kv_dpm.c

970

(u8)kv_get_clk_bypass(rdev, table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

976

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

984

(u8 *)&pi->samu_level_count,

sys/dev/drm/radeon/kv_dpm.c

985

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.c

995

(u8 *)&pi->samu_interval,

sys/dev/drm/radeon/kv_dpm.c

996

sizeof(u8),

sys/dev/drm/radeon/kv_dpm.h

100

u8 htc_hyst_lmt;

sys/dev/drm/radeon/kv_dpm.h

125

u8 graphics_dpm_level_count;

sys/dev/drm/radeon/kv_dpm.h

126

u8 uvd_level_count;

sys/dev/drm/radeon/kv_dpm.h

127

u8 vce_level_count;

sys/dev/drm/radeon/kv_dpm.h

128

u8 acp_level_count;

sys/dev/drm/radeon/kv_dpm.h

129

u8 samu_level_count;

sys/dev/drm/radeon/kv_dpm.h

137

u8 uvd_boot_level;

sys/dev/drm/radeon/kv_dpm.h

138

u8 vce_boot_level;

sys/dev/drm/radeon/kv_dpm.h

139

u8 acp_boot_level;

sys/dev/drm/radeon/kv_dpm.h

140

u8 samu_boot_level;

sys/dev/drm/radeon/kv_dpm.h

141

u8 uvd_interval;

sys/dev/drm/radeon/kv_dpm.h

142

u8 vce_interval;

sys/dev/drm/radeon/kv_dpm.h

143

u8 acp_interval;

sys/dev/drm/radeon/kv_dpm.h

144

u8 samu_interval;

sys/dev/drm/radeon/kv_dpm.h

145

u8 graphics_boot_level;

sys/dev/drm/radeon/kv_dpm.h

146

u8 graphics_interval;

sys/dev/drm/radeon/kv_dpm.h

147

u8 graphics_therm_throttle_enable;

sys/dev/drm/radeon/kv_dpm.h

148

u8 graphics_voltage_change_enable;

sys/dev/drm/radeon/kv_dpm.h

149

u8 graphics_clk_slow_enable;

sys/dev/drm/radeon/kv_dpm.h

150

u8 graphics_clk_slow_divider;

sys/dev/drm/radeon/kv_dpm.h

151

u8 fps_low_t;

sys/dev/drm/radeon/kv_dpm.h

198

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/radeon/kv_dpm.h

72

u8 vddc_index;

sys/dev/drm/radeon/kv_dpm.h

73

u8 ds_divider_index;

sys/dev/drm/radeon/kv_dpm.h

74

u8 ss_divider_index;

sys/dev/drm/radeon/kv_dpm.h

75

u8 allow_gnb_slow;

sys/dev/drm/radeon/kv_dpm.h

76

u8 force_nbp_state;

sys/dev/drm/radeon/kv_dpm.h

77

u8 display_wm;

sys/dev/drm/radeon/kv_dpm.h

78

u8 vce_wm;

sys/dev/drm/radeon/kv_dpm.h

85

u8 dpm0_pg_nb_ps_lo;

sys/dev/drm/radeon/kv_dpm.h

86

u8 dpm0_pg_nb_ps_hi;

sys/dev/drm/radeon/kv_dpm.h

87

u8 dpmx_nb_ps_lo;

sys/dev/drm/radeon/kv_dpm.h

88

u8 dpmx_nb_ps_hi;

sys/dev/drm/radeon/kv_dpm.h

99

u8 htc_tmp_lmt;

sys/dev/drm/radeon/kv_smc.c

120

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/radeon/ni_dpm.c

1308

voltage->index = (u8)i;

sys/dev/drm/radeon/ni_dpm.c

1356

u16 value, u8 index,

sys/dev/drm/radeon/ni_dpm.c

1495

(u8 *)(&smc_table->dpm2Params.TDPLimit),

sys/dev/drm/radeon/ni_dpm.c

1621

(u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);

sys/dev/drm/radeon/ni_dpm.c

1654

(u8 *)&arb_regs,

sys/dev/drm/radeon/ni_dpm.c

1992

return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,

sys/dev/drm/radeon/ni_dpm.c

2150

ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,

sys/dev/drm/radeon/ni_dpm.c

2467

u8 max_ps_percent;

sys/dev/drm/radeon/ni_dpm.c

2526

(u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

sys/dev/drm/radeon/ni_dpm.c

2648

(u8)(NISLANDS_DRIVER_STATE_ARB_INDEX + i);

sys/dev/drm/radeon/ni_dpm.c

2703

ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

2715

u8 i, j, k;

sys/dev/drm/radeon/ni_dpm.c

2822

u8 i, j;

sys/dev/drm/radeon/ni_dpm.c

2848

u8 i, j;

sys/dev/drm/radeon/ni_dpm.c

2877

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/drm/radeon/ni_dpm.c

2939

mc_reg_table->last = (u8)i;

sys/dev/drm/radeon/ni_dpm.c

3018

(u8 *)mc_reg_table,

sys/dev/drm/radeon/ni_dpm.c

3041

(u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

sys/dev/drm/radeon/ni_dpm.c

3194

ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,

sys/dev/drm/radeon/ni_dpm.c

3419

u8 perf_req, bool advertise)

sys/dev/drm/radeon/ni_dpm.c

3897

u8 table_rev)

sys/dev/drm/radeon/ni_dpm.c

3995

u8 frev, crev;

sys/dev/drm/radeon/ni_dpm.c

4019

u8 *idx;

sys/dev/drm/radeon/ni_dpm.c

4029

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/drm/radeon/ni_dpm.h

100

u8 lts_truncate_n;

sys/dev/drm/radeon/ni_dpm.h

161

u8 mc_read_weight;

sys/dev/drm/radeon/ni_dpm.h

162

u8 mc_write_weight;

sys/dev/drm/radeon/ni_dpm.h

203

u8 lta_window_size;

sys/dev/drm/radeon/ni_dpm.h

204

u8 lts_truncate;

sys/dev/drm/radeon/ni_dpm.h

53

u8 last;

sys/dev/drm/radeon/ni_dpm.h

54

u8 num_entries;

sys/dev/drm/radeon/ni_dpm.h

95

u8 mc_wr_weight;

sys/dev/drm/radeon/ni_dpm.h

96

u8 mc_rd_weight;

sys/dev/drm/radeon/ni_dpm.h

97

u8 allow_ovrflw;

sys/dev/drm/radeon/ni_dpm.h

98

u8 num_win_tdp;

sys/dev/drm/radeon/ni_dpm.h

99

u8 l2num_win_tdp;

sys/dev/drm/radeon/r100.c

2747

u8 byte;

sys/dev/drm/radeon/r600_dpm.c

1011

((u8 *)entry + sizeof(ATOM_PPLIB_PhaseSheddingLimits_Record));

sys/dev/drm/radeon/r600_dpm.c

1061

((u8 *)entry + sizeof(ATOM_PPLIB_CAC_Leakage_Record));

sys/dev/drm/radeon/r600_dpm.c

1106

((u8 *)&array->entries[0] +

sys/dev/drm/radeon/r600_dpm.c

1115

((u8 *)entry + sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record));

sys/dev/drm/radeon/r600_dpm.c

1121

((u8 *)&array->entries[0] +

sys/dev/drm/radeon/r600_dpm.c

1132

((u8 *)state_entry + sizeof(ATOM_PPLIB_VCE_State_Record));

sys/dev/drm/radeon/r600_dpm.c

1159

((u8 *)&array->entries[0] +

sys/dev/drm/radeon/r600_dpm.c

1168

((u8 *)entry + sizeof(ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record));

sys/dev/drm/radeon/r600_dpm.c

1195

((u8 *)entry + sizeof(ATOM_PPLIB_SAMClk_Voltage_Limit_Record));

sys/dev/drm/radeon/r600_dpm.c

1253

((u8 *)entry + sizeof(ATOM_PPLIB_ACPClk_Voltage_Limit_Record));

sys/dev/drm/radeon/r600_dpm.c

1258

u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset +

sys/dev/drm/radeon/r600_dpm.c

1363

u8 r600_encode_pci_lane_width(u32 lanes)

sys/dev/drm/radeon/r600_dpm.c

1365

u8 encoded_lanes[] = { 0, 1, 2, 0, 3, 0, 0, 0, 4, 0, 0, 0, 5, 0, 0, 0, 6 };

sys/dev/drm/radeon/r600_dpm.c

839

((u8 *)entry + sizeof(ATOM_PPLIB_Clock_Voltage_Dependency_Record));

sys/dev/drm/radeon/r600_dpm.c

852

u8 frev, crev;

sys/dev/drm/radeon/r600_dpm.c

882

u8 frev, crev;

sys/dev/drm/radeon/r600_dpm.h

234

u8 r600_encode_pci_lane_width(u32 lanes);

sys/dev/drm/radeon/r600_hdmi.c

143

u8 enable_mask)

sys/dev/drm/radeon/r600_hdmi.c

255

const u8 *frame = (const u8*)buffer + 3;

sys/dev/drm/radeon/radeon.h

1274

u8 vddc_id; /* index into vddc voltage table */

sys/dev/drm/radeon/radeon.h

1275

u8 vddci_id; /* index into vddci voltage table */

sys/dev/drm/radeon/radeon.h

1439

u8 count;

sys/dev/drm/radeon/radeon.h

1450

u8 count;

sys/dev/drm/radeon/radeon.h

1455

u8 ppm_design;

sys/dev/drm/radeon/radeon.h

1509

u8 t_hyst;

sys/dev/drm/radeon/radeon.h

1512

u8 control_mode;

sys/dev/drm/radeon/radeon.h

1539

u8 clk_idx;

sys/dev/drm/radeon/radeon.h

1540

u8 pstate;

sys/dev/drm/radeon/radeon.h

1654

u8 fan_pulses_per_revolution;

sys/dev/drm/radeon/radeon.h

1655

u8 fan_min_rpm;

sys/dev/drm/radeon/radeon.h

1656

u8 fan_max_rpm;

sys/dev/drm/radeon/radeon.h

1760

u8 status_bits;

sys/dev/drm/radeon/radeon.h

1761

u8 category_code;

sys/dev/drm/radeon/radeon.h

1913

void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);

sys/dev/drm/radeon/radeon.h

1915

u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);

sys/dev/drm/radeon/radeon.h

2896

u8 enable_mask);

sys/dev/drm/radeon/radeon.h

2899

u8 enable_mask);

sys/dev/drm/radeon/radeon.h

2956

u8 perf_req, bool advertise);

sys/dev/drm/radeon/radeon.h

297

u8 clock_type,

sys/dev/drm/radeon/radeon.h

305

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);

sys/dev/drm/radeon/radeon.h

307

u16 voltage_level, u8 voltage_type,

sys/dev/drm/radeon/radeon.h

312

u8 voltage_type, u16 *voltage_step);

sys/dev/drm/radeon/radeon.h

313

int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,

sys/dev/drm/radeon/radeon.h

328

u8 voltage_type,

sys/dev/drm/radeon/radeon.h

332

u8 voltage_type, u16 *min_voltage);

sys/dev/drm/radeon/radeon.h

334

u8 voltage_type, u16 *max_voltage);

sys/dev/drm/radeon/radeon.h

336

u8 voltage_type, u8 voltage_mode,

sys/dev/drm/radeon/radeon.h

339

u8 voltage_type, u8 voltage_mode);

sys/dev/drm/radeon/radeon.h

341

u8 voltage_type,

sys/dev/drm/radeon/radeon.h

342

u8 *svd_gpio_id, u8 *svc_gpio_id);

sys/dev/drm/radeon/radeon.h

348

u8 module_index,

sys/dev/drm/radeon/radeon.h

351

u8 module_index, struct atom_memory_info *mem_info);

sys/dev/drm/radeon/radeon.h

353

bool gddr5, u8 module_index,

sys/dev/drm/radeon/radeon_acpi.c

49

u8 command_code; /* notify command code */

sys/dev/drm/radeon/radeon_acpi.c

55

u8 panel_exp_mode; /* panel expansion mode */

sys/dev/drm/radeon/radeon_acpi.c

56

u8 thermal_gfx; /* thermal state: target gfx controller */

sys/dev/drm/radeon/radeon_acpi.c

57

u8 thermal_state; /* thermal state: state id (0: exit state, non-0: state) */

sys/dev/drm/radeon/radeon_acpi.c

58

u8 forced_power_gfx; /* forced power state: target gfx controller */

sys/dev/drm/radeon/radeon_acpi.c

581

u8 perf_req, bool advertise)

sys/dev/drm/radeon/radeon_acpi.c

59

u8 forced_power_state; /* forced power state: state id */

sys/dev/drm/radeon/radeon_acpi.c

60

u8 system_power_src; /* system power source */

sys/dev/drm/radeon/radeon_acpi.c

61

u8 backlight_level; /* panel backlight level (0-255) */

sys/dev/drm/radeon/radeon_acpi.c

82

u8 req_type; /* request type */

sys/dev/drm/radeon/radeon_acpi.c

83

u8 perf_req; /* performance request */

sys/dev/drm/radeon/radeon_acpi.c

88

u8 ret_val; /* return value */

sys/dev/drm/radeon/radeon_asic.h

45

void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);

sys/dev/drm/radeon/radeon_asic.h

46

u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);

sys/dev/drm/radeon/radeon_asic.h

47

void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);

sys/dev/drm/radeon/radeon_asic.h

48

u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);

sys/dev/drm/radeon/radeon_asic.h

754

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);

sys/dev/drm/radeon/radeon_asic.h

755

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);

sys/dev/drm/radeon/radeon_atombios.c

1114

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

1301

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

1399

((u8 *)&ss_info->asSS_Info[0]);

sys/dev/drm/radeon/radeon_atombios.c

1412

((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));

sys/dev/drm/radeon/radeon_atombios.c

1426

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

151

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/drm/radeon/radeon_atombios.c

1539

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);

sys/dev/drm/radeon/radeon_atombios.c

1551

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));

sys/dev/drm/radeon/radeon_atombios.c

1557

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);

sys/dev/drm/radeon/radeon_atombios.c

1573

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));

sys/dev/drm/radeon/radeon_atombios.c

1579

ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);

sys/dev/drm/radeon/radeon_atombios.c

1600

((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));

sys/dev/drm/radeon/radeon_atombios.c

1695

u8 *record;

sys/dev/drm/radeon/radeon_atombios.c

1699

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/drm/radeon/radeon_atombios.c

1703

record = (u8 *)(mode_info->atom_context->bios +

sys/dev/drm/radeon/radeon_atombios.c

1725

memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],

sys/dev/drm/radeon/radeon_atombios.c

1797

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

186

((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));

sys/dev/drm/radeon/radeon_atombios.c

192

u8 id)

sys/dev/drm/radeon/radeon_atombios.c

2091

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

222

((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));

sys/dev/drm/radeon/radeon_atombios.c

2377

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

2582

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

2673

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

2674

u8 *power_state_offset;

sys/dev/drm/radeon/radeon_atombios.c

2697

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/radeon/radeon_atombios.c

2758

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

2828

u8 clock_type,

sys/dev/drm/radeon/radeon_atombios.c

2835

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

2951

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3097

void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)

sys/dev/drm/radeon/radeon_atombios.c

3101

u8 frev, crev, volt_index = voltage_level;

sys/dev/drm/radeon/radeon_atombios.c

3134

int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,

sys/dev/drm/radeon/radeon_atombios.c

3139

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3185

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3215

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3332

u16 voltage_level, u8 voltage_type,

sys/dev/drm/radeon/radeon_atombios.c

3337

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3383

u8 voltage_type)

sys/dev/drm/radeon/radeon_atombios.c

3387

u8 *start = (u8 *)v1;

sys/dev/drm/radeon/radeon_atombios.c

3400

u8 voltage_type)

sys/dev/drm/radeon/radeon_atombios.c

3404

u8 *start = (u8*)v2;

sys/dev/drm/radeon/radeon_atombios.c

3417

u8 voltage_type, u8 voltage_mode)

sys/dev/drm/radeon/radeon_atombios.c

3421

u8 *start = (u8*)v3;

sys/dev/drm/radeon/radeon_atombios.c

3435

u8 voltage_type, u8 voltage_mode)

sys/dev/drm/radeon/radeon_atombios.c

3438

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3493

u8 voltage_type,

sys/dev/drm/radeon/radeon_atombios.c

3494

u8 *svd_gpio_id, u8 *svc_gpio_id)

sys/dev/drm/radeon/radeon_atombios.c

3497

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3537

u8 voltage_type, u16 *max_voltage)

sys/dev/drm/radeon/radeon_atombios.c

3540

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3578

((u8 *)&formula->asVIDAdjustEntries[0] +

sys/dev/drm/radeon/radeon_atombios.c

3596

u8 voltage_type, u16 *min_voltage)

sys/dev/drm/radeon/radeon_atombios.c

3599

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3646

u8 voltage_type, u16 *voltage_step)

sys/dev/drm/radeon/radeon_atombios.c

3649

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3687

u8 voltage_type,

sys/dev/drm/radeon/radeon_atombios.c

3713

u8 voltage_type, u8 voltage_mode,

sys/dev/drm/radeon/radeon_atombios.c

3717

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

3756

((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));

sys/dev/drm/radeon/radeon_atombios.c

3786

((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));

sys/dev/drm/radeon/radeon_atombios.c

3814

u8 module_index, struct atom_memory_info *mem_info)

sys/dev/drm/radeon/radeon_atombios.c

3817

u8 frev, crev, i;

sys/dev/drm/radeon/radeon_atombios.c

3840

((u8 *)vram_module + le16_to_cpu(vram_module->usSize));

sys/dev/drm/radeon/radeon_atombios.c

3857

((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));

sys/dev/drm/radeon/radeon_atombios.c

3881

((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));

sys/dev/drm/radeon/radeon_atombios.c

3903

bool gddr5, u8 module_index,

sys/dev/drm/radeon/radeon_atombios.c

3907

u8 frev, crev, i;

sys/dev/drm/radeon/radeon_atombios.c

3936

((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));

sys/dev/drm/radeon/radeon_atombios.c

3938

mclk_range_table->num_entries = (u8)

sys/dev/drm/radeon/radeon_atombios.c

3945

((u8 *)format + mem_timing_size);

sys/dev/drm/radeon/radeon_atombios.c

3976

u8 module_index,

sys/dev/drm/radeon/radeon_atombios.c

3980

u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;

sys/dev/drm/radeon/radeon_atombios.c

4001

((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));

sys/dev/drm/radeon/radeon_atombios.c

4004

((u8 *)reg_block + (2 * sizeof(u16)) +

sys/dev/drm/radeon/radeon_atombios.c

4007

num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /

sys/dev/drm/radeon/radeon_atombios.c

4017

(u8)(format->ucPreRegDataLength);

sys/dev/drm/radeon/radeon_atombios.c

4020

((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));

sys/dev/drm/radeon/radeon_atombios.c

4025

t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)

sys/dev/drm/radeon/radeon_atombios.c

4044

((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));

sys/dev/drm/radeon/radeon_atombios.c

42

u8 index)

sys/dev/drm/radeon/radeon_atombios.c

516

u8 frev, crev;

sys/dev/drm/radeon/radeon_atombios.c

696

u8 *num_dst_objs = (u8 *)

sys/dev/drm/radeon/radeon_atombios.c

697

((u8 *)router_src_dst_table + 1 +

sys/dev/drm/radeon/radeon_atombios.c

975

u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;

sys/dev/drm/radeon/radeon_audio.c

252

struct r600_audio_pin *pin, u8 enable_mask)

sys/dev/drm/radeon/radeon_audio.c

34

u8 enable_mask);

sys/dev/drm/radeon/radeon_audio.c

37

u8 enable_mask);

sys/dev/drm/radeon/radeon_audio.c

392

u8 *sadb = NULL;

sys/dev/drm/radeon/radeon_audio.c

40

u8 enable_mask);

sys/dev/drm/radeon/radeon_audio.c

518

u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];

sys/dev/drm/radeon/radeon_audio.c

52

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_audio.c

54

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_audio.c

56

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_audio.c

58

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_audio.c

599

u8 i;

sys/dev/drm/radeon/radeon_audio.c

60

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_audio.c

62

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_audio.h

41

struct r600_audio_pin *pin, u8 enable_mask);

sys/dev/drm/radeon/radeon_audio.h

53

u8 *sadb, int sad_count);

sys/dev/drm/radeon/radeon_combios.c

2634

u8 rev, blocks, tmp;

sys/dev/drm/radeon/radeon_combios.c

2657

u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;

sys/dev/drm/radeon/radeon_combios.c

2754

u8 entries = RBIOS8(offset + 0x5 + 0xb);

sys/dev/drm/radeon/radeon_combios.c

643

u8 id, blocks, clk, data;

sys/dev/drm/radeon/radeon_device.c

1793

u8 bl_level = radeon_get_backlight_level(rdev,

sys/dev/drm/radeon/radeon_device.c

1907

u8 bl_level = radeon_get_backlight_level(rdev,

sys/dev/drm/radeon/radeon_dp_auxch.c

64

u8 byte;

sys/dev/drm/radeon/radeon_dp_auxch.c

65

u8 *buf = msg->buffer;

sys/dev/drm/radeon/radeon_dp_mst.c

676

u8 msg[1];

sys/dev/drm/radeon/radeon_dp_mst.c

711

u8 esi[16] = { 0 };

sys/dev/drm/radeon/radeon_i2c.c

1053

u8 slave_addr,

sys/dev/drm/radeon/radeon_i2c.c

1054

u8 addr,

sys/dev/drm/radeon/radeon_i2c.c

1055

u8 *val)

sys/dev/drm/radeon/radeon_i2c.c

1057

u8 out_buf[2];

sys/dev/drm/radeon/radeon_i2c.c

1058

u8 in_buf[2];

sys/dev/drm/radeon/radeon_i2c.c

1087

u8 slave_addr,

sys/dev/drm/radeon/radeon_i2c.c

1088

u8 addr,

sys/dev/drm/radeon/radeon_i2c.c

1089

u8 val)

sys/dev/drm/radeon/radeon_i2c.c

1110

u8 val;

sys/dev/drm/radeon/radeon_i2c.c

1138

u8 val;

sys/dev/drm/radeon/radeon_i2c.c

241

u8 n, m, loop;

sys/dev/drm/radeon/radeon_i2c.c

44

u8 out = 0x0;

sys/dev/drm/radeon/radeon_i2c.c

45

u8 buf[8];

sys/dev/drm/radeon/radeon_legacy_encoders.c

270

u8

sys/dev/drm/radeon/radeon_legacy_encoders.c

275

u8 backlight_level;

sys/dev/drm/radeon/radeon_legacy_encoders.c

284

radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)

sys/dev/drm/radeon/radeon_mode.h

347

u8 h_border;

sys/dev/drm/radeon/radeon_mode.h

348

u8 v_border;

sys/dev/drm/radeon/radeon_mode.h

490

u8 dpcd[DP_RECEIVER_CAP_SIZE];

sys/dev/drm/radeon/radeon_mode.h

491

u8 dp_sink_type;

sys/dev/drm/radeon/radeon_mode.h

500

u8 id;

sys/dev/drm/radeon/radeon_mode.h

508

u8 plugged_state;

sys/dev/drm/radeon/radeon_mode.h

515

u8 i2c_addr;

sys/dev/drm/radeon/radeon_mode.h

518

u8 ddc_mux_type;

sys/dev/drm/radeon/radeon_mode.h

519

u8 ddc_mux_control_pin;

sys/dev/drm/radeon/radeon_mode.h

520

u8 ddc_mux_state;

sys/dev/drm/radeon/radeon_mode.h

523

u8 cd_mux_type;

sys/dev/drm/radeon/radeon_mode.h

524

u8 cd_mux_control_pin;

sys/dev/drm/radeon/radeon_mode.h

525

u8 cd_mux_state;

sys/dev/drm/radeon/radeon_mode.h

638

u8 mem_vendor;

sys/dev/drm/radeon/radeon_mode.h

639

u8 mem_type;

sys/dev/drm/radeon/radeon_mode.h

646

u8 num_entries;

sys/dev/drm/radeon/radeon_mode.h

647

u8 rsv[3];

sys/dev/drm/radeon/radeon_mode.h

661

u8 pre_reg_data;

sys/dev/drm/radeon/radeon_mode.h

665

u8 last;

sys/dev/drm/radeon/radeon_mode.h

666

u8 num_entries;

sys/dev/drm/radeon/radeon_mode.h

755

extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);

sys/dev/drm/radeon/radeon_mode.h

760

u8 power_state);

sys/dev/drm/radeon/radeon_mode.h

779

void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);

sys/dev/drm/radeon/radeon_mode.h

795

u8 slave_addr,

sys/dev/drm/radeon/radeon_mode.h

796

u8 addr,

sys/dev/drm/radeon/radeon_mode.h

797

u8 *val);

sys/dev/drm/radeon/radeon_mode.h

799

u8 slave_addr,

sys/dev/drm/radeon/radeon_mode.h

800

u8 addr,

sys/dev/drm/radeon/radeon_mode.h

801

u8 val);

sys/dev/drm/radeon/radeon_mode.h

813

u8 id);

sys/dev/drm/radeon/rs780_dpm.c

720

u8 table_rev)

sys/dev/drm/radeon/rs780_dpm.c

799

u8 frev, crev;

sys/dev/drm/radeon/rs780_dpm.c

852

u8 frev, crev;

sys/dev/drm/radeon/rv6xx_dpm.c

1003

int d_l, int d_r, u8 *l, u8 *r)

sys/dev/drm/radeon/rv6xx_dpm.c

1883

u8 frev, crev;

sys/dev/drm/radeon/rv6xx_dpm.c

1907

u8 *idx;

sys/dev/drm/radeon/rv6xx_dpm.c

1916

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/drm/radeon/rv6xx_dpm.c

242

u32 start_index, u8 *end_index)

sys/dev/drm/radeon/rv6xx_dpm.c

293

*end_index = (u8)step_index - 1;

sys/dev/drm/radeon/rv6xx_dpm.h

43

u8 high_sclk_index;

sys/dev/drm/radeon/rv6xx_dpm.h

44

u8 medium_sclk_index;

sys/dev/drm/radeon/rv6xx_dpm.h

45

u8 low_sclk_index;

sys/dev/drm/radeon/rv6xx_dpm.h

46

u8 high_mclk_index;

sys/dev/drm/radeon/rv6xx_dpm.h

47

u8 medium_mclk_index;

sys/dev/drm/radeon/rv6xx_dpm.h

48

u8 low_mclk_index;

sys/dev/drm/radeon/rv6xx_dpm.h

49

u8 high_vddc_index;

sys/dev/drm/radeon/rv6xx_dpm.h

50

u8 medium_vddc_index;

sys/dev/drm/radeon/rv6xx_dpm.h

51

u8 low_vddc_index;

sys/dev/drm/radeon/rv6xx_dpm.h

52

u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];

sys/dev/drm/radeon/rv6xx_dpm.h

53

u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];

sys/dev/drm/radeon/rv730_dpm.c

500

pi->odt_value_0[0] = (u8)0;

sys/dev/drm/radeon/rv730_dpm.c

501

pi->odt_value_1[0] = (u8)0x80;

sys/dev/drm/radeon/rv730_dpm.c

504

pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);

sys/dev/drm/radeon/rv730_dpm.c

507

pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);

sys/dev/drm/radeon/rv740_dpm.c

410

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/radeon/rv740_dpm.c

412

u8 mc_para_index;

sys/dev/drm/radeon/rv740_dpm.c

417

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/drm/radeon/rv770_dpm.c

1231

(const u8 *)table,

sys/dev/drm/radeon/rv770_dpm.c

1241

u8 vddc_index = 0;

sys/dev/drm/radeon/rv770_dpm.c

1274

pi->valid_vddc_entries = (u8)steps;

sys/dev/drm/radeon/rv770_dpm.c

1308

u8 rv770_get_memory_module_index(struct radeon_device *rdev)

sys/dev/drm/radeon/rv770_dpm.c

1310

return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);

sys/dev/drm/radeon/rv770_dpm.c

1316

u8 memory_module_index;

sys/dev/drm/radeon/rv770_dpm.c

1399

return rv770_copy_bytes_to_smc(rdev, address, (const u8 *)&state,

sys/dev/drm/radeon/rv770_dpm.c

1677

u8 memory_module_index;

sys/dev/drm/radeon/rv770_dpm.c

2151

u8 table_rev)

sys/dev/drm/radeon/rv770_dpm.c

2281

u8 frev, crev;

sys/dev/drm/radeon/rv770_dpm.c

2305

u8 *idx;

sys/dev/drm/radeon/rv770_dpm.c

231

u8 rv770_get_seq_value(struct radeon_device *rdev,

sys/dev/drm/radeon/rv770_dpm.c

2315

idx = (u8 *)&power_state->v1.ucClockStateIndices[0];

sys/dev/drm/radeon/rv770_dpm.c

269

u8 l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];

sys/dev/drm/radeon/rv770_dpm.c

270

u8 r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];

sys/dev/drm/radeon/rv770_dpm.c

281

l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

282

r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

289

l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

290

r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

395

u8 encoded_reference_dividers[] = { 0, 16, 17, 20, 21 };

sys/dev/drm/radeon/rv770_dpm.c

621

u8 watermark_level)

sys/dev/drm/radeon/rv770_dpm.h

106

u8 valid_vddc_entries;

sys/dev/drm/radeon/rv770_dpm.h

109

u8 odt_value_0[2];

sys/dev/drm/radeon/rv770_dpm.h

110

u8 odt_value_1[2];

sys/dev/drm/radeon/rv770_dpm.h

211

u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);

sys/dev/drm/radeon/rv770_dpm.h

221

u8 rv770_get_seq_value(struct radeon_device *rdev,

sys/dev/drm/radeon/rv770_dpm.h

237

u8 rv770_get_memory_module_index(struct radeon_device *rdev);

sys/dev/drm/radeon/rv770_dpm.h

66

u8 vddc_index;

sys/dev/drm/radeon/rv770_dpm.h

67

u8 high_smio;

sys/dev/drm/radeon/rv770_smc.c

117

static const u8 cedar_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

137

static const u8 redwood_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

157

static const u8 juniper_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

177

static const u8 cypress_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

197

static const u8 barts_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

217

static const u8 turks_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

237

static const u8 caicos_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

257

static const u8 cayman_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

296

u16 smc_start_address, const u8 *src,

sys/dev/drm/radeon/rv770_smc.c

363

u32 smc_first_vector, const u8 *src,

sys/dev/drm/radeon/rv770_smc.c

37

static const u8 rv770_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

484

const u8 *int_vect;

sys/dev/drm/radeon/rv770_smc.c

487

const u8 *ucode_data;

sys/dev/drm/radeon/rv770_smc.c

500

int_vect = (const u8 *)&rv770_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

507

int_vect = (const u8 *)&rv730_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

514

int_vect = (const u8 *)&rv710_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

521

int_vect = (const u8 *)&rv740_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

528

int_vect = (const u8 *)&cedar_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

535

int_vect = (const u8 *)&redwood_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

542

int_vect = (const u8 *)&juniper_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

550

int_vect = (const u8 *)&cypress_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

557

int_vect = (const u8 *)&barts_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

564

int_vect = (const u8 *)&turks_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

57

static const u8 rv730_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

571

int_vect = (const u8 *)&caicos_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

578

int_vect = (const u8 *)&cayman_smc_int_vectors;

sys/dev/drm/radeon/rv770_smc.c

588

ucode_data = (const u8 *)rdev->smc_fw->data;

sys/dev/drm/radeon/rv770_smc.c

77

static const u8 rv710_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.c

97

static const u8 rv740_smc_int_vectors[] =

sys/dev/drm/radeon/rv770_smc.h

191

u16 smc_start_address, const u8 *src,

sys/dev/drm/radeon/si_dpm.c

2194

(u8 *)(&(smc_table->dpm2Params.TDPLimit)),

sys/dev/drm/radeon/si_dpm.c

2211

(u8 *)papm_parm,

sys/dev/drm/radeon/si_dpm.c

2243

(u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),

sys/dev/drm/radeon/si_dpm.c

2302

u8 max_ps_percent;

sys/dev/drm/radeon/si_dpm.c

2371

smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);

sys/dev/drm/radeon/si_dpm.c

2475

u8 tdep_count;

sys/dev/drm/radeon/si_dpm.c

2526

ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,

sys/dev/drm/radeon/si_dpm.c

2718

ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,

sys/dev/drm/radeon/si_dpm.c

2906

(u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),

sys/dev/drm/radeon/si_dpm.c

3827

u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)

sys/dev/drm/radeon/si_dpm.c

3829

u8 mc_para_index;

sys/dev/drm/radeon/si_dpm.c

3836

mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);

sys/dev/drm/radeon/si_dpm.c

3840

u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)

sys/dev/drm/radeon/si_dpm.c

3842

u8 mc_para_index;

sys/dev/drm/radeon/si_dpm.c

3850

mc_para_index = (u8)((memory_clock - 10000) / 2500);

sys/dev/drm/radeon/si_dpm.c

3857

mc_para_index = (u8)((memory_clock - 60000) / 5000);

sys/dev/drm/radeon/si_dpm.c

3862

static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)

sys/dev/drm/radeon/si_dpm.c

3866

u8 result = 0;

sys/dev/drm/radeon/si_dpm.c

4056

u8 i;

sys/dev/drm/radeon/si_dpm.c

4121

voltage->index = (u8)i;

sys/dev/drm/radeon/si_dpm.c

4143

voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;

sys/dev/drm/radeon/si_dpm.c

4202

u16 value, u8 index,

sys/dev/drm/radeon/si_dpm.c

4225

smc_voltage->phase_settings = (u8)i;

sys/dev/drm/radeon/si_dpm.c

4304

(u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);

sys/dev/drm/radeon/si_dpm.c

4316

arb_regs->mc_arb_burst_time = (u8)burst_time;

sys/dev/drm/radeon/si_dpm.c

4338

(u8 *)&arb_regs,

sys/dev/drm/radeon/si_dpm.c

4459

table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;

sys/dev/drm/radeon/si_dpm.c

4552

table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,

sys/dev/drm/radeon/si_dpm.c

4652

state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);

sys/dev/drm/radeon/si_dpm.c

4682

(u8 *)&arb_regs,

sys/dev/drm/radeon/si_dpm.c

4780

(u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),

sys/dev/drm/radeon/si_dpm.c

4993

level->gen2PCIE = (u8)si_pi->force_pcie_gen;

sys/dev/drm/radeon/si_dpm.c

4995

level->gen2PCIE = (u8)pl->pcie_gen;

sys/dev/drm/radeon/si_dpm.c

5233

(u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);

sys/dev/drm/radeon/si_dpm.c

5290

ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,

sys/dev/drm/radeon/si_dpm.c

5312

ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,

sys/dev/drm/radeon/si_dpm.c

5362

u8 i, j, k;

sys/dev/drm/radeon/si_dpm.c

5485

u8 i, j;

sys/dev/drm/radeon/si_dpm.c

5511

u8 i, j;

sys/dev/drm/radeon/si_dpm.c

5540

u8 module_index = rv770_get_memory_module_index(rdev);

sys/dev/drm/radeon/si_dpm.c

5602

mc_reg_table->last = (u8)i;

sys/dev/drm/radeon/si_dpm.c

5687

(u8 *)smc_mc_reg_table,

sys/dev/drm/radeon/si_dpm.c

5707

(u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],

sys/dev/drm/radeon/si_dpm.c

5790

u8 request;

sys/dev/drm/radeon/si_dpm.c

6095

(u8 *)(&fan_table),

sys/dev/drm/radeon/si_dpm.c

6709

u8 table_rev)

sys/dev/drm/radeon/si_dpm.c

6821

u8 frev, crev;

sys/dev/drm/radeon/si_dpm.c

6822

u8 *power_state_offset;

sys/dev/drm/radeon/si_dpm.c

6844

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/radeon/si_dpm.c

6846

u8 *idx;

sys/dev/drm/radeon/si_dpm.c

6863

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/radeon/si_dpm.c

6871

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/radeon/si_dpm.h

113

u8 last;

sys/dev/drm/radeon/si_dpm.h

114

u8 num_entries;

sys/dev/drm/radeon/si_dpm.h

199

u8 svd_gpio_id;

sys/dev/drm/radeon/si_dpm.h

200

u8 svc_gpio_id;

sys/dev/drm/radeon/si_dpm.h

49

u8 lts_truncate_default;

sys/dev/drm/radeon/si_dpm.h

50

u8 shift_n_default;

sys/dev/drm/radeon/si_dpm.h

51

u8 operating_temp;

sys/dev/drm/radeon/si_dpm.h

55

u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];

sys/dev/drm/radeon/si_dpm.h

65

u8 lts_truncate;

sys/dev/drm/radeon/si_dpm.h

66

u8 shift_n;

sys/dev/drm/radeon/si_dpm.h

67

u8 dc_pwr_value;

sys/dev/drm/radeon/si_dpm.h

78

u8 window_size;

sys/dev/drm/radeon/si_dpm.h

79

u8 temp_select;

sys/dev/drm/radeon/si_dpm.h

80

u8 dte_mode;

sys/dev/drm/radeon/si_dpm.h

81

u8 tdep_count;

sys/dev/drm/radeon/si_dpm.h

82

u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];

sys/dev/drm/radeon/si_smc.c

138

static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };

sys/dev/drm/radeon/si_smc.c

216

const u8 *src;

sys/dev/drm/radeon/si_smc.c

230

src = (const u8 *)

sys/dev/drm/radeon/si_smc.c

258

src = (const u8 *)rdev->smc_fw->data;

sys/dev/drm/radeon/si_smc.c

49

const u8 *src, u32 byte_count, u32 limit)

sys/dev/drm/radeon/sislands_smc.h

408

const u8 *src, u32 byte_count, u32 limit);

sys/dev/drm/radeon/sumo_dpm.c

1408

u8 table_rev)

sys/dev/drm/radeon/sumo_dpm.c

1468

u8 frev, crev;

sys/dev/drm/radeon/sumo_dpm.c

1469

u8 *power_state_offset;

sys/dev/drm/radeon/sumo_dpm.c

1491

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/radeon/sumo_dpm.c

1493

u8 *idx;

sys/dev/drm/radeon/sumo_dpm.c

1507

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/radeon/sumo_dpm.c

1514

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/radeon/sumo_dpm.c

1663

u8 frev, crev;

sys/dev/drm/radeon/sumo_dpm.h

85

u8 htc_tmp_lmt;

sys/dev/drm/radeon/sumo_dpm.h

86

u8 htc_hyst_lmt;

sys/dev/drm/radeon/trinity_dpm.c

1339

static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk)

sys/dev/drm/radeon/trinity_dpm.c

1362

static u8 trinity_get_sleep_divider_id_from_clock(struct radeon_device *rdev,

sys/dev/drm/radeon/trinity_dpm.c

1383

return (u8)i;

sys/dev/drm/radeon/trinity_dpm.c

1436

static u8 trinity_calculate_display_wm(struct radeon_device *rdev,

sys/dev/drm/radeon/trinity_dpm.c

1688

u8 table_rev)

sys/dev/drm/radeon/trinity_dpm.c

1747

u8 frev, crev;

sys/dev/drm/radeon/trinity_dpm.c

1748

u8 *power_state_offset;

sys/dev/drm/radeon/trinity_dpm.c

1770

power_state_offset = (u8 *)state_array->states;

sys/dev/drm/radeon/trinity_dpm.c

1772

u8 *idx;

sys/dev/drm/radeon/trinity_dpm.c

1786

idx = (u8 *)&power_state->v2.clockInfoIndex[0];

sys/dev/drm/radeon/trinity_dpm.c

1794

((u8 *)&clock_info_array->clockInfo[0] +

sys/dev/drm/radeon/trinity_dpm.c

1831

static u32 trinity_convert_did_to_freq(struct radeon_device *rdev, u8 did)

sys/dev/drm/radeon/trinity_dpm.c

1856

u8 frev, crev;

sys/dev/drm/radeon/trinity_dpm.h

32

u8 vddc_index;

sys/dev/drm/radeon/trinity_dpm.h

33

u8 ds_divider_index;

sys/dev/drm/radeon/trinity_dpm.h

34

u8 ss_divider_index;

sys/dev/drm/radeon/trinity_dpm.h

35

u8 allow_gnb_slow;

sys/dev/drm/radeon/trinity_dpm.h

36

u8 force_nbp_state;

sys/dev/drm/radeon/trinity_dpm.h

37

u8 display_wm;

sys/dev/drm/radeon/trinity_dpm.h

38

u8 vce_wm;

sys/dev/drm/radeon/trinity_dpm.h

54

u8 Dpm0PgNbPsLo;

sys/dev/drm/radeon/trinity_dpm.h

55

u8 Dpm0PgNbPsHi;

sys/dev/drm/radeon/trinity_dpm.h

56

u8 DpmXNbPsLo;

sys/dev/drm/radeon/trinity_dpm.h

57

u8 DpmXNbPsHi;

sys/dev/drm/radeon/trinity_dpm.h

71

u8 vclk_did;

sys/dev/drm/radeon/trinity_dpm.h

72

u8 dclk_did;

sys/dev/drm/radeon/trinity_dpm.h

73

u8 rsv[2];

sys/dev/drm/radeon/trinity_dpm.h

86

u8 htc_tmp_lmt;

sys/dev/drm/radeon/trinity_dpm.h

87

u8 htc_hyst_lmt;

sys/dev/drm/ttm/ttm_bo_util.c

544

map->virtual = (void *)(((u8 *)bo->mem.bus.addr) + offset);

sys/dev/netif/ig_hal/e1000_82540.c

705

hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);

sys/dev/netif/ig_hal/e1000_82540.c

706

hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);

sys/dev/netif/ig_hal/e1000_82542.c

414

static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_82542.c

50

static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_82542.c

582

hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);

sys/dev/netif/ig_hal/e1000_82542.c

583

hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);

sys/dev/netif/ig_hal/e1000_82543.c

409

u8 *mac_addr, u32 max_frame_size)

sys/dev/netif/ig_hal/e1000_82543.c

682

u8 i;

sys/dev/netif/ig_hal/e1000_82543.h

51

u32 frame_len, u8 *mac_addr,

sys/dev/netif/ig_hal/e1000_82575.c

108

static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);

sys/dev/netif/ig_hal/e1000_82575.c

109

static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);

sys/dev/netif/ig_hal/e1000_82575.c

1238

u8 port = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1860

u8 tranceiver_type = 0;

sys/dev/netif/ig_hal/e1000_82575.c

1885

(u8 *)eth_flags);

sys/dev/netif/ig_hal/e1000_82575.c

3270

s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,

sys/dev/netif/ig_hal/e1000_82575.c

3271

u8 dev_addr, u8 *data)

sys/dev/netif/ig_hal/e1000_82575.c

3361

s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,

sys/dev/netif/ig_hal/e1000_82575.c

3362

u8 dev_addr, u8 data)

sys/dev/netif/ig_hal/e1000_82575.c

3487

static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)

sys/dev/netif/ig_hal/e1000_82575.c

3510

static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)

sys/dev/netif/ig_hal/e1000_82575.h

518

s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,

sys/dev/netif/ig_hal/e1000_82575.h

519

u8 dev_addr, u8 *data);

sys/dev/netif/ig_hal/e1000_82575.h

520

s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,

sys/dev/netif/ig_hal/e1000_82575.h

521

u8 dev_addr, u8 data);

sys/dev/netif/ig_hal/e1000_api.c

1243

s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size)

sys/dev/netif/ig_hal/e1000_api.c

1353

u8 data)

sys/dev/netif/ig_hal/e1000_api.c

601

void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,

sys/dev/netif/ig_hal/e1000_api.c

661

s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length)

sys/dev/netif/ig_hal/e1000_api.c

880

int e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_api.c

911

u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)

sys/dev/netif/ig_hal/e1000_api.c

942

s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,

sys/dev/netif/ig_hal/e1000_api.c

943

u16 offset, u8 *sum)

sys/dev/netif/ig_hal/e1000_api.h

100

s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);

sys/dev/netif/ig_hal/e1000_api.h

114

s32 e1000_mng_host_if_write(struct e1000_hw *hw, u8 *buffer, u16 length,

sys/dev/netif/ig_hal/e1000_api.h

115

u16 offset, u8 *sum);

sys/dev/netif/ig_hal/e1000_api.h

118

s32 e1000_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);

sys/dev/netif/ig_hal/e1000_api.h

72

int e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_api.h

73

u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);

sys/dev/netif/ig_hal/e1000_api.h

74

void e1000_update_mc_addr_list(struct e1000_hw *hw, u8 *mc_addr_list,

sys/dev/netif/ig_hal/e1000_api.h

90

u8 data);

sys/dev/netif/ig_hal/e1000_hw.h

1021

u8 *hw_addr;

sys/dev/netif/ig_hal/e1000_hw.h

1022

u8 *flash_address;

sys/dev/netif/ig_hal/e1000_hw.h

1049

u8 revision_id;

sys/dev/netif/ig_hal/e1000_hw.h

414

u8 status; /* Descriptor status */

sys/dev/netif/ig_hal/e1000_hw.h

415

u8 errors; /* Descriptor Errors */

sys/dev/netif/ig_hal/e1000_hw.h

487

u8 cso; /* Checksum offset */

sys/dev/netif/ig_hal/e1000_hw.h

488

u8 cmd; /* Descriptor control */

sys/dev/netif/ig_hal/e1000_hw.h

494

u8 status; /* Descriptor status */

sys/dev/netif/ig_hal/e1000_hw.h

495

u8 css; /* Checksum start */

sys/dev/netif/ig_hal/e1000_hw.h

506

u8 ipcss; /* IP checksum start */

sys/dev/netif/ig_hal/e1000_hw.h

507

u8 ipcso; /* IP checksum offset */

sys/dev/netif/ig_hal/e1000_hw.h

514

u8 tucss; /* TCP checksum start */

sys/dev/netif/ig_hal/e1000_hw.h

515

u8 tucso; /* TCP checksum offset */

sys/dev/netif/ig_hal/e1000_hw.h

523

u8 status; /* Descriptor status */

sys/dev/netif/ig_hal/e1000_hw.h

524

u8 hdr_len; /* Header length */

sys/dev/netif/ig_hal/e1000_hw.h

537

u8 typ_len_ext;

sys/dev/netif/ig_hal/e1000_hw.h

538

u8 cmd;

sys/dev/netif/ig_hal/e1000_hw.h

544

u8 status; /* Descriptor status */

sys/dev/netif/ig_hal/e1000_hw.h

545

u8 popts; /* Packet Options */

sys/dev/netif/ig_hal/e1000_hw.h

675

u8 status;

sys/dev/netif/ig_hal/e1000_hw.h

676

u8 reserved0;

sys/dev/netif/ig_hal/e1000_hw.h

680

u8 reserved3;

sys/dev/netif/ig_hal/e1000_hw.h

681

u8 checksum;

sys/dev/netif/ig_hal/e1000_hw.h

686

u8 command_id;

sys/dev/netif/ig_hal/e1000_hw.h

687

u8 command_length;

sys/dev/netif/ig_hal/e1000_hw.h

688

u8 command_options;

sys/dev/netif/ig_hal/e1000_hw.h

689

u8 checksum;

sys/dev/netif/ig_hal/e1000_hw.h

695

u8 command_data[E1000_HI_MAX_DATA_LENGTH];

sys/dev/netif/ig_hal/e1000_hw.h

700

u8 command_id;

sys/dev/netif/ig_hal/e1000_hw.h

701

u8 checksum;

sys/dev/netif/ig_hal/e1000_hw.h

710

u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];

sys/dev/netif/ig_hal/e1000_hw.h

734

void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);

sys/dev/netif/ig_hal/e1000_hw.h

744

int (*rar_set)(struct e1000_hw *, u8*, u32);

sys/dev/netif/ig_hal/e1000_hw.h

790

s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);

sys/dev/netif/ig_hal/e1000_hw.h

791

s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);

sys/dev/netif/ig_hal/e1000_hw.h

809

u8 addr[ETH_ADDR_LEN];

sys/dev/netif/ig_hal/e1000_hw.h

810

u8 perm_addr[ETH_ADDR_LEN];

sys/dev/netif/ig_hal/e1000_hw.h

835

u8 forced_speed_duplex;

sys/dev/netif/ig_hal/e1000_hw.h

876

u8 mdix;

sys/dev/netif/ig_hal/e1000_hw.h

996

u8 media_port;

sys/dev/netif/ig_hal/e1000_i210.c

376

static s32 e1000_read_invm_word_i210(struct e1000_hw *hw, u8 address, u16 *data)

sys/dev/netif/ig_hal/e1000_i210.c

381

u8 record_type, word_address;

sys/dev/netif/ig_hal/e1000_i210.c

428

ret_val = e1000_read_invm_word_i210(hw, (u8)offset, &data[0]);

sys/dev/netif/ig_hal/e1000_i210.c

429

ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+1,

sys/dev/netif/ig_hal/e1000_i210.c

431

ret_val |= e1000_read_invm_word_i210(hw, (u8)offset+2,

sys/dev/netif/ig_hal/e1000_i210.c

437

ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);

sys/dev/netif/ig_hal/e1000_i210.c

444

ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);

sys/dev/netif/ig_hal/e1000_i210.c

451

ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);

sys/dev/netif/ig_hal/e1000_i210.c

458

ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);

sys/dev/netif/ig_hal/e1000_i210.c

465

ret_val = e1000_read_invm_word_i210(hw, (u8)offset, data);

sys/dev/netif/ig_hal/e1000_i210.c

856

u8 dev_addr, u16 *data, bool read)

sys/dev/netif/ig_hal/e1000_i210.c

897

s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data)

sys/dev/netif/ig_hal/e1000_i210.c

911

s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data)

sys/dev/netif/ig_hal/e1000_i210.h

50

s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,

sys/dev/netif/ig_hal/e1000_i210.h

52

s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,

sys/dev/netif/ig_hal/e1000_i210.h

60

(u8)((invm_dword) & 0x7)

sys/dev/netif/ig_hal/e1000_i210.h

62

(u8)(((invm_dword) & 0x0000FE00) >> 9)

sys/dev/netif/ig_hal/e1000_ich8lan.c

126

u32 offset, u8 *data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

128

u8 size, u16 *data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

140

u32 offset, u8 byte);

sys/dev/netif/ig_hal/e1000_ich8lan.c

1406

u8 ulp_exit_timeout = 30;

sys/dev/netif/ig_hal/e1000_ich8lan.c

2003

static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_ich8lan.c

2072

static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_ich8lan.c

2150

u8 *mc_addr_list,

sys/dev/netif/ig_hal/e1000_ich8lan.c

2734

static u32 e1000_calc_rx_da_crc(u8 mac[])

sys/dev/netif/ig_hal/e1000_ich8lan.c

2782

u8 mac_addr[ETH_ADDR_LEN] = {0};

sys/dev/netif/ig_hal/e1000_ich8lan.c

3403

u8 sig_byte = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3422

sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3435

sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3830

u8 *data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

3846

*data = (u8)word;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3861

u8 size, u16 *data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

3868

u8 count = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

3902

*data = (u8)(flash_data & 0x000000FF);

sys/dev/netif/ig_hal/e1000_ich8lan.c

3942

u8 count = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4284

(u8)data);

sys/dev/netif/ig_hal/e1000_ich8lan.c

4291

(u8)(data >> 8));

sys/dev/netif/ig_hal/e1000_ich8lan.c

4316

(u8)(data >> 8));

sys/dev/netif/ig_hal/e1000_ich8lan.c

4418

u8 size, u16 data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

4425

u8 count = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4521

u8 count = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

4604

u8 data)

sys/dev/netif/ig_hal/e1000_ich8lan.c

4660

u32 offset, u8 byte)

sys/dev/netif/ig_hal/e1000_ich8lan.c

5545

u8 retry = 0;

sys/dev/netif/ig_hal/e1000_ich8lan.c

80

static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_ich8lan.c

81

static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_ich8lan.c

84

u8 *mc_addr_list,

sys/dev/netif/ig_hal/e1000_mac.c

133

u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)

sys/dev/netif/ig_hal/e1000_mac.c

159

u8 E1000_UNUSEDARG *h, u32 E1000_UNUSEDARG a)

sys/dev/netif/ig_hal/e1000_mac.c

2236

u32 offset, u8 data)

sys/dev/netif/ig_hal/e1000_mac.c

380

u8 mac_addr[ETH_ADDR_LEN] = {0};

sys/dev/netif/ig_hal/e1000_mac.c

412

u8 alt_mac_addr[ETH_ADDR_LEN];

sys/dev/netif/ig_hal/e1000_mac.c

456

alt_mac_addr[i] = (u8)(nvm_data & 0xFF);

sys/dev/netif/ig_hal/e1000_mac.c

457

alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);

sys/dev/netif/ig_hal/e1000_mac.c

484

int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)

sys/dev/netif/ig_hal/e1000_mac.c

522

u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)

sys/dev/netif/ig_hal/e1000_mac.c

525

u8 bit_shift = 0;

sys/dev/netif/ig_hal/e1000_mac.c

594

u8 *mc_addr_list, u32 mc_addr_count)

sys/dev/netif/ig_hal/e1000_mac.h

44

void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);

sys/dev/netif/ig_hal/e1000_mac.h

46

int e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);

sys/dev/netif/ig_hal/e1000_mac.h

72

u8 *mc_addr_list, u32 mc_addr_count);

sys/dev/netif/ig_hal/e1000_mac.h

73

int e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);

sys/dev/netif/ig_hal/e1000_mac.h

81

u32 offset, u8 data);

sys/dev/netif/ig_hal/e1000_mac.h

83

u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);

sys/dev/netif/ig_hal/e1000_manage.c

137

u8 i, len;

sys/dev/netif/ig_hal/e1000_manage.c

166

csum = e1000_calculate_checksum((u8 *)hdr,

sys/dev/netif/ig_hal/e1000_manage.c

200

hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);

sys/dev/netif/ig_hal/e1000_manage.c

225

s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,

sys/dev/netif/ig_hal/e1000_manage.c

226

u16 length, u16 offset, u8 *sum)

sys/dev/netif/ig_hal/e1000_manage.c

228

u8 *tmp;

sys/dev/netif/ig_hal/e1000_manage.c

229

u8 *bufptr = buffer;

sys/dev/netif/ig_hal/e1000_manage.c

240

tmp = (u8 *)&data;

sys/dev/netif/ig_hal/e1000_manage.c

297

s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,

sys/dev/netif/ig_hal/e1000_manage.c

396

s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)

sys/dev/netif/ig_hal/e1000_manage.c

46

u8 e1000_calculate_checksum(u8 *buffer, u32 length)

sys/dev/netif/ig_hal/e1000_manage.c

469

s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)

sys/dev/netif/ig_hal/e1000_manage.c

49

u8 sum = 0;

sys/dev/netif/ig_hal/e1000_manage.c

59

return (u8) (0 - sum);

sys/dev/netif/ig_hal/e1000_manage.c

75

u8 i;

sys/dev/netif/ig_hal/e1000_manage.h

41

s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,

sys/dev/netif/ig_hal/e1000_manage.h

42

u16 length, u16 offset, u8 *sum);

sys/dev/netif/ig_hal/e1000_manage.h

46

u8 *buffer, u16 length);

sys/dev/netif/ig_hal/e1000_manage.h

48

u8 e1000_calculate_checksum(u8 *buffer, u32 length);

sys/dev/netif/ig_hal/e1000_manage.h

49

s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length);

sys/dev/netif/ig_hal/e1000_manage.h

50

s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length);

sys/dev/netif/ig_hal/e1000_nvm.c

1147

hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));

sys/dev/netif/ig_hal/e1000_nvm.c

1150

hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));

sys/dev/netif/ig_hal/e1000_nvm.c

1252

u8 q, hval, rem, result;

sys/dev/netif/ig_hal/e1000_nvm.c

392

u8 spi_stat_reg;

sys/dev/netif/ig_hal/e1000_nvm.c

420

spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);

sys/dev/netif/ig_hal/e1000_nvm.c

453

u8 read_opcode = NVM_READ_OPCODE_SPI;

sys/dev/netif/ig_hal/e1000_nvm.c

513

u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;

sys/dev/netif/ig_hal/e1000_nvm.c

628

u8 write_opcode = NVM_WRITE_OPCODE_SPI;

sys/dev/netif/ig_hal/e1000_nvm.c

774

s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,

sys/dev/netif/ig_hal/e1000_nvm.c

873

pba_num[offset * 2] = (u8)(nvm_data >> 8);

sys/dev/netif/ig_hal/e1000_nvm.c

874

pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);

sys/dev/netif/ig_hal/e1000_nvm.h

49

u8 invm_major;

sys/dev/netif/ig_hal/e1000_nvm.h

50

u8 invm_minor;

sys/dev/netif/ig_hal/e1000_nvm.h

51

u8 invm_img_type;

sys/dev/netif/ig_hal/e1000_nvm.h

69

s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,

sys/dev/netif/ig_hal/e1000_phy.c

172

u8 E1000_UNUSEDARG byte_offset,

sys/dev/netif/ig_hal/e1000_phy.c

173

u8 E1000_UNUSEDARG dev_addr,

sys/dev/netif/ig_hal/e1000_phy.c

174

u8 E1000_UNUSEDARG *data)

sys/dev/netif/ig_hal/e1000_phy.c

189

u8 E1000_UNUSEDARG byte_offset,

sys/dev/netif/ig_hal/e1000_phy.c

190

u8 E1000_UNUSEDARG dev_addr,

sys/dev/netif/ig_hal/e1000_phy.c

191

u8 E1000_UNUSEDARG data)

sys/dev/netif/ig_hal/e1000_phy.c

529

s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)

sys/dev/netif/ig_hal/e1000_phy.c

566

*data = (u8) data_local & 0xFF;

sys/dev/netif/ig_hal/e1000_phy.c

584

s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data)

sys/dev/netif/ig_hal/e1000_phy.h

110

s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);

sys/dev/netif/ig_hal/e1000_phy.h

111

s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);

sys/dev/netif/ig_hal/e1000_phy.h

308

u8 e1000_base_sx:1;

sys/dev/netif/ig_hal/e1000_phy.h

309

u8 e1000_base_lx:1;

sys/dev/netif/ig_hal/e1000_phy.h

310

u8 e1000_base_cx:1;

sys/dev/netif/ig_hal/e1000_phy.h

311

u8 e1000_base_t:1;

sys/dev/netif/ig_hal/e1000_phy.h

312

u8 e100_base_lx:1;

sys/dev/netif/ig_hal/e1000_phy.h

313

u8 e100_base_fx:1;

sys/dev/netif/ig_hal/e1000_phy.h

314

u8 e10_base_bx10:1;

sys/dev/netif/ig_hal/e1000_phy.h

315

u8 e10_base_px:1;

sys/dev/netif/ig_hal/e1000_phy.h

44

s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,

sys/dev/netif/ig_hal/e1000_phy.h

45

u8 dev_addr, u8 *data);

sys/dev/netif/ig_hal/e1000_phy.h

46

s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,

sys/dev/netif/ig_hal/e1000_phy.h

47

u8 dev_addr, u8 data);

sys/dev/netif/ig_hal/e1000_vf.c

264

u8 *addr = (u8 *)(&msgbuf[1]);

sys/dev/netif/ig_hal/e1000_vf.c

323

static int e1000_rar_set_vf(struct e1000_hw *hw, u8 *addr,

sys/dev/netif/ig_hal/e1000_vf.c

328

u8 *msg_addr = (u8 *)(&msgbuf[1]);

sys/dev/netif/ig_hal/e1000_vf.c

357

static u32 e1000_hash_mc_addr_vf(struct e1000_hw *hw, u8 *mc_addr)

sys/dev/netif/ig_hal/e1000_vf.c

360

u8 bit_shift = 0;

sys/dev/netif/ig_hal/e1000_vf.c

401

u8 *mc_addr_list, u32 mc_addr_count)

sys/dev/netif/ig_hal/e1000_vf.c

51

static void e1000_update_mc_addr_list_vf(struct e1000_hw *hw, u8 *, u32);

sys/dev/netif/ig_hal/e1000_vf.c

52

static int e1000_rar_set_vf(struct e1000_hw *, u8 *, u32);

sys/dev/netif/ig_hal/e1000_vf.h

206

void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);

sys/dev/netif/ig_hal/e1000_vf.h

211

int (*rar_set)(struct e1000_hw *, u8*, u32);

sys/dev/netif/ig_hal/e1000_vf.h

217

u8 addr[6];

sys/dev/netif/ig_hal/e1000_vf.h

218

u8 perm_addr[6];

sys/dev/netif/ig_hal/e1000_vf.h

264

u8 *hw_addr;

sys/dev/netif/ig_hal/e1000_vf.h

265

u8 *flash_address;

sys/dev/netif/ig_hal/e1000_vf.h

280

u8 revision_id;

sys/dev/netif/ix/ixgbe_82598.c

1079

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_82598.c

1090

*val = (u8)atlas_ctl;

sys/dev/netif/ix/ixgbe_82598.c

1103

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_82598.c

1126

static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,

sys/dev/netif/ix/ixgbe_82598.c

1127

u8 byte_offset, u8 *eeprom_data)

sys/dev/netif/ix/ixgbe_82598.c

1181

*eeprom_data = (u8)(sfp_data >> 8);

sys/dev/netif/ix/ixgbe_82598.c

1199

s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82598.c

1200

u8 *eeprom_data)

sys/dev/netif/ix/ixgbe_82598.c

1214

static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82598.c

1215

u8 *sff8472_data)

sys/dev/netif/ix/ixgbe_82598.c

1398

u8 i = 0;

sys/dev/netif/ix/ixgbe_82598.c

68

static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82598.c

69

u8 *sff8472_data);

sys/dev/netif/ix/ixgbe_82598.c

818

u8 analog_val;

sys/dev/netif/ix/ixgbe_82598.h

45

s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_82598.h

46

s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_82598.h

47

s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82598.h

48

u8 *eeprom_data);

sys/dev/netif/ix/ixgbe_82599.c

1409

void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)

sys/dev/netif/ix/ixgbe_82599.c

1542

u8 queue)

sys/dev/netif/ix/ixgbe_82599.c

1545

u8 flow_type;

sys/dev/netif/ix/ixgbe_82599.c

1876

u16 soft_id, u8 queue, bool cloud_mode)

sys/dev/netif/ix/ixgbe_82599.c

2015

u16 soft_id, u8 queue, bool cloud_mode)

sys/dev/netif/ix/ixgbe_82599.c

2075

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_82599.c

2086

*val = (u8)core_ctl;

sys/dev/netif/ix/ixgbe_82599.c

2099

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_82599.c

2534

static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82599.c

2535

u8 dev_addr, u8 *data)

sys/dev/netif/ix/ixgbe_82599.c

2592

static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82599.c

2593

u8 dev_addr, u8 data)

sys/dev/netif/ix/ixgbe_82599.c

56

static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82599.c

57

u8 dev_addr, u8 *data);

sys/dev/netif/ix/ixgbe_82599.c

58

static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_82599.c

59

u8 dev_addr, u8 data);

sys/dev/netif/ix/ixgbe_82599.h

56

s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_82599.h

57

s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_api.c

1001

s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,

sys/dev/netif/ix/ixgbe_api.c

1022

s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,

sys/dev/netif/ix/ixgbe_api.c

1139

s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,

sys/dev/netif/ix/ixgbe_api.c

1140

u8 ver, u16 len, char *driver_ver)

sys/dev/netif/ix/ixgbe_api.c

1409

s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value)

sys/dev/netif/ix/ixgbe_api.c

1423

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val)

sys/dev/netif/ix/ixgbe_api.c

1437

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val)

sys/dev/netif/ix/ixgbe_api.c

1465

s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,

sys/dev/netif/ix/ixgbe_api.c

1466

u8 *data)

sys/dev/netif/ix/ixgbe_api.c

1481

s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_api.c

1482

u8 dev_addr, u8 *data)

sys/dev/netif/ix/ixgbe_api.c

1498

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/netif/ix/ixgbe_api.c

1513

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val)

sys/dev/netif/ix/ixgbe_api.c

1529

s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,

sys/dev/netif/ix/ixgbe_api.c

1530

u8 data)

sys/dev/netif/ix/ixgbe_api.c

1546

s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_api.c

1547

u8 dev_addr, u8 data)

sys/dev/netif/ix/ixgbe_api.c

1563

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_api.c

1578

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_api.c

1593

u8 byte_offset, u8 eeprom_data)

sys/dev/netif/ix/ixgbe_api.c

1608

s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data)

sys/dev/netif/ix/ixgbe_api.c

315

s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr)

sys/dev/netif/ix/ixgbe_api.c

329

s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)

sys/dev/netif/ix/ixgbe_api.c

342

s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr)

sys/dev/netif/ix/ixgbe_api.c

449

s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)

sys/dev/netif/ix/ixgbe_api.c

67

void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map)

sys/dev/netif/ix/ixgbe_api.c

894

s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)

sys/dev/netif/ix/ixgbe_api.c

911

s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_api.h

110

s32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

111

s32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_api.h

119

s32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list,

sys/dev/netif/ix/ixgbe_api.h

121

s32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list,

sys/dev/netif/ix/ixgbe_api.h

124

void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr_list, u32 vmdq);

sys/dev/netif/ix/ixgbe_api.h

135

s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,

sys/dev/netif/ix/ixgbe_api.h

136

u8 ver, u16 len, char *driver_ver);

sys/dev/netif/ix/ixgbe_api.h

137

void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);

sys/dev/netif/ix/ixgbe_api.h

140

s32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val);

sys/dev/netif/ix/ixgbe_api.h

141

s32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val);

sys/dev/netif/ix/ixgbe_api.h

143

s32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data);

sys/dev/netif/ix/ixgbe_api.h

156

u8 queue);

sys/dev/netif/ix/ixgbe_api.h

161

u16 soft_id, u8 queue, bool cloud_mode);

sys/dev/netif/ix/ixgbe_api.h

169

u8 queue,

sys/dev/netif/ix/ixgbe_api.h

176

s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,

sys/dev/netif/ix/ixgbe_api.h

177

u8 *data);

sys/dev/netif/ix/ixgbe_api.h

178

s32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_api.h

179

u8 dev_addr, u8 *data);

sys/dev/netif/ix/ixgbe_api.h

180

s32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/netif/ix/ixgbe_api.h

181

s32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val);

sys/dev/netif/ix/ixgbe_api.h

182

s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,

sys/dev/netif/ix/ixgbe_api.h

183

u8 data);

sys/dev/netif/ix/ixgbe_api.h

184

void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue);

sys/dev/netif/ix/ixgbe_api.h

185

s32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_api.h

186

u8 dev_addr, u8 data);

sys/dev/netif/ix/ixgbe_api.h

187

s32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/netif/ix/ixgbe_api.h

188

s32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val);

sys/dev/netif/ix/ixgbe_api.h

189

s32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 eeprom_data);

sys/dev/netif/ix/ixgbe_api.h

190

s32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);

sys/dev/netif/ix/ixgbe_api.h

191

s32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr);

sys/dev/netif/ix/ixgbe_api.h

201

s32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value);

sys/dev/netif/ix/ixgbe_api.h

40

void ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map);

sys/dev/netif/ix/ixgbe_api.h

59

s32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr);

sys/dev/netif/ix/ixgbe_api.h

65

s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);

sys/dev/netif/ix/ixgbe_common.c

1086

bus->lan_id = (u8)bus->func;

sys/dev/netif/ix/ixgbe_common.c

1166

u8 i;

sys/dev/netif/ix/ixgbe_common.c

1368

u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;

sys/dev/netif/ix/ixgbe_common.c

1525

u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;

sys/dev/netif/ix/ixgbe_common.c

1984

u8 spi_stat_reg;

sys/dev/netif/ix/ixgbe_common.c

1997

spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);

sys/dev/netif/ix/ixgbe_common.c

2354

s32 ixgbe_validate_mac_addr(u8 *mac_addr)

sys/dev/netif/ix/ixgbe_common.c

2384

s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_common.c

2543

void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

2583

s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,

sys/dev/netif/ix/ixgbe_common.c

2586

u8 *addr;

sys/dev/netif/ix/ixgbe_common.c

2651

static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)

sys/dev/netif/ix/ixgbe_common.c

2688

void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)

sys/dev/netif/ix/ixgbe_common.c

2726

s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,

sys/dev/netif/ix/ixgbe_common.c

3586

s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)

sys/dev/netif/ix/ixgbe_common.c

3589

u8 i;

sys/dev/netif/ix/ixgbe_common.c

3616

san_mac_addr[i * 2] = (u8)(san_mac_data);

sys/dev/netif/ix/ixgbe_common.c

3617

san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);

sys/dev/netif/ix/ixgbe_common.c

3639

s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)

sys/dev/netif/ix/ixgbe_common.c

3643

u8 i;

sys/dev/netif/ix/ixgbe_common.c

3722

s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)

sys/dev/netif/ix/ixgbe_common.c

4478

u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)

sys/dev/netif/ix/ixgbe_common.c

4481

u8 sum = 0;

sys/dev/netif/ix/ixgbe_common.c

4491

return (u8) (0 - sum);

sys/dev/netif/ix/ixgbe_common.c

4680

s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,

sys/dev/netif/ix/ixgbe_common.c

4681

u8 build, u8 sub, u16 len,

sys/dev/netif/ix/ixgbe_common.c

4694

fw_cmd.port_num = (u8)hw->bus.func;

sys/dev/netif/ix/ixgbe_common.c

4702

fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,

sys/dev/netif/ix/ixgbe_common.c

5067

s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value)

sys/dev/netif/ix/ixgbe_common.c

5211

void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)

sys/dev/netif/ix/ixgbe_common.c

53

static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);

sys/dev/netif/ix/ixgbe_common.c

5463

u8 rs, eeprom_data;

sys/dev/netif/ix/ixgbe_common.c

642

s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,

sys/dev/netif/ix/ixgbe_common.c

737

pba_num[offset * 2] = (u8)(data >> 8);

sys/dev/netif/ix/ixgbe_common.c

738

pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);

sys/dev/netif/ix/ixgbe_common.c

977

s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)

sys/dev/netif/ix/ixgbe_common.c

989

mac_addr[i] = (u8)(rar_low >> (i*8));

sys/dev/netif/ix/ixgbe_common.c

992

mac_addr[i+4] = (u8)(rar_high >> (i*8));

sys/dev/netif/ix/ixgbe_common.h

100

s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,

sys/dev/netif/ix/ixgbe_common.h

104

s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,

sys/dev/netif/ix/ixgbe_common.h

107

s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,

sys/dev/netif/ix/ixgbe_common.h

120

s32 ixgbe_validate_mac_addr(u8 *mac_addr);

sys/dev/netif/ix/ixgbe_common.h

131

s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);

sys/dev/netif/ix/ixgbe_common.h

132

s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr);

sys/dev/netif/ix/ixgbe_common.h

137

s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);

sys/dev/netif/ix/ixgbe_common.h

161

s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,

sys/dev/netif/ix/ixgbe_common.h

162

u8 build, u8 ver, u16 len, const char *str);

sys/dev/netif/ix/ixgbe_common.h

163

u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);

sys/dev/netif/ix/ixgbe_common.h

175

s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value);

sys/dev/netif/ix/ixgbe_common.h

52

void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map);

sys/dev/netif/ix/ixgbe_common.h

61

s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,

sys/dev/netif/ix/ixgbe_common.h

70

s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);

sys/dev/netif/ix/ixgbe_dcb.c

107

u8 bw_percent = 0;

sys/dev/netif/ix/ixgbe_dcb.c

108

u8 i;

sys/dev/netif/ix/ixgbe_dcb.c

152

p->link_percent = (u8)link_percentage;

sys/dev/netif/ix/ixgbe_dcb.c

209

void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)

sys/dev/netif/ix/ixgbe_dcb.c

244

u8 *bwgid)

sys/dev/netif/ix/ixgbe_dcb.c

254

u8 *tsa)

sys/dev/netif/ix/ixgbe_dcb.c

263

u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)

sys/dev/netif/ix/ixgbe_dcb.c

266

u8 prio_mask = 1 << up;

sys/dev/netif/ix/ixgbe_dcb.c

267

u8 tc = cfg->num_tcs.pg_tcs;

sys/dev/netif/ix/ixgbe_dcb.c

287

u8 *map)

sys/dev/netif/ix/ixgbe_dcb.c

289

u8 up;

sys/dev/netif/ix/ixgbe_dcb.c

313

u8 i, j, bw = 0, bw_id;

sys/dev/netif/ix/ixgbe_dcb.c

314

u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];

sys/dev/netif/ix/ixgbe_dcb.c

397

u8 tc_count)

sys/dev/netif/ix/ixgbe_dcb.c

428

u8 tc_count)

sys/dev/netif/ix/ixgbe_dcb.c

461

u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };

sys/dev/netif/ix/ixgbe_dcb.c

462

u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };

sys/dev/netif/ix/ixgbe_dcb.c

463

u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };

sys/dev/netif/ix/ixgbe_dcb.c

504

u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];

sys/dev/netif/ix/ixgbe_dcb.c

505

u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];

sys/dev/netif/ix/ixgbe_dcb.c

52

s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,

sys/dev/netif/ix/ixgbe_dcb.c

546

u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];

sys/dev/netif/ix/ixgbe_dcb.c

547

u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];

sys/dev/netif/ix/ixgbe_dcb.c

548

u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };

sys/dev/netif/ix/ixgbe_dcb.c

591

u8 pfc_en;

sys/dev/netif/ix/ixgbe_dcb.c

592

u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };

sys/dev/netif/ix/ixgbe_dcb.c

656

u8 pfc_en;

sys/dev/netif/ix/ixgbe_dcb.c

657

u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];

sys/dev/netif/ix/ixgbe_dcb.c

658

u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];

sys/dev/netif/ix/ixgbe_dcb.c

659

u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };

sys/dev/netif/ix/ixgbe_dcb.c

705

s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)

sys/dev/netif/ix/ixgbe_dcb.c

729

u8 *bwg_id, u8 *tsa, u8 *map)

sys/dev/netif/ix/ixgbe_dcb.c

96

u32 max_frame_size, u8 direction)

sys/dev/netif/ix/ixgbe_dcb.h

106

u8 tc; /* Traffic class (TC) */

sys/dev/netif/ix/ixgbe_dcb.h

117

u8 pg_tcs;

sys/dev/netif/ix/ixgbe_dcb.h

118

u8 pfc_tcs;

sys/dev/netif/ix/ixgbe_dcb.h

125

u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */

sys/dev/netif/ix/ixgbe_dcb.h

142

s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int);

sys/dev/netif/ix/ixgbe_dcb.h

144

struct ixgbe_dcb_config *, u32, u8);

sys/dev/netif/ix/ixgbe_dcb.h

147

s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *);

sys/dev/netif/ix/ixgbe_dcb.h

152

s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);

sys/dev/netif/ix/ixgbe_dcb.h

153

s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8);

sys/dev/netif/ix/ixgbe_dcb.h

164

void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb.h

167

void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *);

sys/dev/netif/ix/ixgbe_dcb.h

168

void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *);

sys/dev/netif/ix/ixgbe_dcb.h

169

void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *);

sys/dev/netif/ix/ixgbe_dcb.h

170

u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);

sys/dev/netif/ix/ixgbe_dcb.h

173

s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb.h

71

u8 traffic_classes;

sys/dev/netif/ix/ixgbe_dcb.h

72

u8 pfc_traffic_classes;

sys/dev/netif/ix/ixgbe_dcb.h

83

u8 bwg_id; /* Bandwidth Group (BWG) ID */

sys/dev/netif/ix/ixgbe_dcb.h

84

u8 bwg_percent; /* % of BWG's bandwidth */

sys/dev/netif/ix/ixgbe_dcb.h

85

u8 link_percent; /* % of link bandwidth */

sys/dev/netif/ix/ixgbe_dcb.h

86

u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */

sys/dev/netif/ix/ixgbe_dcb_82598.c

121

u16 *max, u8 *tsa)

sys/dev/netif/ix/ixgbe_dcb_82598.c

126

u8 i = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

179

u16 *refill, u16 *max, u8 *bwg_id,

sys/dev/netif/ix/ixgbe_dcb_82598.c

180

u8 *tsa)

sys/dev/netif/ix/ixgbe_dcb_82598.c

183

u8 i;

sys/dev/netif/ix/ixgbe_dcb_82598.c

226

u16 *refill, u16 *max, u8 *bwg_id,

sys/dev/netif/ix/ixgbe_dcb_82598.c

227

u8 *tsa)

sys/dev/netif/ix/ixgbe_dcb_82598.c

230

u8 i;

sys/dev/netif/ix/ixgbe_dcb_82598.c

270

s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)

sys/dev/netif/ix/ixgbe_dcb_82598.c

273

u8 i;

sys/dev/netif/ix/ixgbe_dcb_82598.c

325

u8 i = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

326

u8 j = 0;

sys/dev/netif/ix/ixgbe_dcb_82598.c

359

u16 *refill, u16 *max, u8 *bwg_id,

sys/dev/netif/ix/ixgbe_dcb_82598.c

360

u8 *tsa)

sys/dev/netif/ix/ixgbe_dcb_82598.c

50

u8 tc_count)

sys/dev/netif/ix/ixgbe_dcb_82598.c

92

u8 tc_count)

sys/dev/netif/ix/ixgbe_dcb_82598.h

82

s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);

sys/dev/netif/ix/ixgbe_dcb_82598.h

87

struct ixgbe_hw_stats *, u8);

sys/dev/netif/ix/ixgbe_dcb_82598.h

89

struct ixgbe_hw_stats *, u8);

sys/dev/netif/ix/ixgbe_dcb_82598.h

93

u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82598.h

95

u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82598.h

96

s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82598.h

99

s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82599.c

122

u16 *max, u8 *bwg_id, u8 *tsa,

sys/dev/netif/ix/ixgbe_dcb_82599.c

123

u8 *map)

sys/dev/netif/ix/ixgbe_dcb_82599.c

128

u8 i = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

184

u16 *max, u8 *bwg_id, u8 *tsa)

sys/dev/netif/ix/ixgbe_dcb_82599.c

187

u8 i;

sys/dev/netif/ix/ixgbe_dcb_82599.c

233

u16 *max, u8 *bwg_id, u8 *tsa,

sys/dev/netif/ix/ixgbe_dcb_82599.c

234

u8 *map)

sys/dev/netif/ix/ixgbe_dcb_82599.c

237

u8 i;

sys/dev/netif/ix/ixgbe_dcb_82599.c

294

s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)

sys/dev/netif/ix/ixgbe_dcb_82599.c

297

u8 max_tc = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

385

u8 i = 0;

sys/dev/netif/ix/ixgbe_dcb_82599.c

386

u8 tc_count = 8;

sys/dev/netif/ix/ixgbe_dcb_82599.c

50

u8 tc_count)

sys/dev/netif/ix/ixgbe_dcb_82599.c

597

u16 *refill, u16 *max, u8 *bwg_id, u8 *tsa,

sys/dev/netif/ix/ixgbe_dcb_82599.c

598

u8 *map)

sys/dev/netif/ix/ixgbe_dcb_82599.c

91

u8 tc_count)

sys/dev/netif/ix/ixgbe_dcb_82599.h

130

s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82599.h

136

struct ixgbe_hw_stats *, u8);

sys/dev/netif/ix/ixgbe_dcb_82599.h

138

struct ixgbe_hw_stats *, u8);

sys/dev/netif/ix/ixgbe_dcb_82599.h

142

u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82599.h

144

u8 *, u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82599.h

145

s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *,

sys/dev/netif/ix/ixgbe_dcb_82599.h

146

u8 *, u8 *);

sys/dev/netif/ix/ixgbe_dcb_82599.h

152

s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *,

sys/dev/netif/ix/ixgbe_dcb_82599.h

153

u8 *, u8 *);

sys/dev/netif/ix/ixgbe_osdep_pf.c

64

u8 i;

sys/dev/netif/ix/ixgbe_phy.c

113

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_phy.c

119

u8 csum_byte;

sys/dev/netif/ix/ixgbe_phy.c

120

u8 high_bits;

sys/dev/netif/ix/ixgbe_phy.c

121

u8 low_bits;

sys/dev/netif/ix/ixgbe_phy.c

122

u8 reg_high;

sys/dev/netif/ix/ixgbe_phy.c

123

u8 csum;

sys/dev/netif/ix/ixgbe_phy.c

1306

u8 identifier = 0;

sys/dev/netif/ix/ixgbe_phy.c

1307

u8 comp_codes_1g = 0;

sys/dev/netif/ix/ixgbe_phy.c

1308

u8 comp_codes_10g = 0;

sys/dev/netif/ix/ixgbe_phy.c

1309

u8 oui_bytes[3] = {0, 0, 0};

sys/dev/netif/ix/ixgbe_phy.c

1310

u8 cable_tech = 0;

sys/dev/netif/ix/ixgbe_phy.c

1311

u8 cable_spec = 0;

sys/dev/netif/ix/ixgbe_phy.c

1585

u8 comp_codes_10g = 0;

sys/dev/netif/ix/ixgbe_phy.c

1586

u8 comp_codes_1g = 0;

sys/dev/netif/ix/ixgbe_phy.c

1649

u8 identifier = 0;

sys/dev/netif/ix/ixgbe_phy.c

1650

u8 comp_codes_1g = 0;

sys/dev/netif/ix/ixgbe_phy.c

1651

u8 comp_codes_10g = 0;

sys/dev/netif/ix/ixgbe_phy.c

1652

u8 oui_bytes[3] = {0, 0, 0};

sys/dev/netif/ix/ixgbe_phy.c

1654

u8 connector = 0;

sys/dev/netif/ix/ixgbe_phy.c

1655

u8 cable_length = 0;

sys/dev/netif/ix/ixgbe_phy.c

1656

u8 device_tech = 0;

sys/dev/netif/ix/ixgbe_phy.c

191

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_phy.c

1931

s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

1932

u8 *eeprom_data)

sys/dev/netif/ix/ixgbe_phy.c

1949

static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

1950

u8 *sff8472_data)

sys/dev/netif/ix/ixgbe_phy.c

1965

s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

1966

u8 eeprom_data)

sys/dev/netif/ix/ixgbe_phy.c

197

u8 reg_high;

sys/dev/netif/ix/ixgbe_phy.c

198

u8 csum;

sys/dev/netif/ix/ixgbe_phy.c

1981

static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)

sys/dev/netif/ix/ixgbe_phy.c

2001

static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

2002

u8 dev_addr, u8 *data, bool lock)

sys/dev/netif/ix/ixgbe_phy.c

2092

s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

2093

u8 dev_addr, u8 *data)

sys/dev/netif/ix/ixgbe_phy.c

2109

s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

2110

u8 dev_addr, u8 *data)

sys/dev/netif/ix/ixgbe_phy.c

2127

static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

2128

u8 dev_addr, u8 data, bool lock)

sys/dev/netif/ix/ixgbe_phy.c

2198

s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

2199

u8 dev_addr, u8 data)

sys/dev/netif/ix/ixgbe_phy.c

2215

s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

2216

u8 dev_addr, u8 data)

sys/dev/netif/ix/ixgbe_phy.c

2300

static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)

sys/dev/netif/ix/ixgbe_phy.c

2323

static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)

sys/dev/netif/ix/ixgbe_phy.c

41

static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);

sys/dev/netif/ix/ixgbe_phy.c

42

static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);

sys/dev/netif/ix/ixgbe_phy.c

50

static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.c

51

u8 *sff8472_data);

sys/dev/netif/ix/ixgbe_phy.c

60

static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)

sys/dev/netif/ix/ixgbe_phy.c

77

static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)

sys/dev/netif/ix/ixgbe_phy.c

95

static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)

sys/dev/netif/ix/ixgbe_phy.h

202

s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.h

203

u8 dev_addr, u8 *data);

sys/dev/netif/ix/ixgbe_phy.h

204

s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.h

205

u8 dev_addr, u8 *data);

sys/dev/netif/ix/ixgbe_phy.h

206

s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.h

207

u8 dev_addr, u8 data);

sys/dev/netif/ix/ixgbe_phy.h

208

s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.h

209

u8 dev_addr, u8 data);

sys/dev/netif/ix/ixgbe_phy.h

210

s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.h

211

u8 *eeprom_data);

sys/dev/netif/ix/ixgbe_phy.h

212

s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,

sys/dev/netif/ix/ixgbe_phy.h

213

u8 eeprom_data);

sys/dev/netif/ix/ixgbe_phy.h

215

s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_phy.h

217

s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_type.h

2498

(bool)(((u8 *)(Address))[0] & ((u8)0x01))

sys/dev/netif/ix/ixgbe_type.h

2502

((((u8 *)(Address))[0] == ((u8)0xff)) && \

sys/dev/netif/ix/ixgbe_type.h

2503

(((u8 *)(Address))[1] == ((u8)0xff)))

sys/dev/netif/ix/ixgbe_type.h

303

u8 nvm_major;

sys/dev/netif/ix/ixgbe_type.h

305

u8 nvm_id;

sys/dev/netif/ix/ixgbe_type.h

308

u8 oem_major;

sys/dev/netif/ix/ixgbe_type.h

309

u8 oem_minor;

sys/dev/netif/ix/ixgbe_type.h

313

u8 or_major;

sys/dev/netif/ix/ixgbe_type.h

3133

u8 cmd;

sys/dev/netif/ix/ixgbe_type.h

3134

u8 buf_len;

sys/dev/netif/ix/ixgbe_type.h

3136

u8 cmd_resv;

sys/dev/netif/ix/ixgbe_type.h

3137

u8 ret_status;

sys/dev/netif/ix/ixgbe_type.h

3139

u8 checksum;

sys/dev/netif/ix/ixgbe_type.h

3143

u8 cmd;

sys/dev/netif/ix/ixgbe_type.h

3144

u8 buf_lenh;

sys/dev/netif/ix/ixgbe_type.h

3145

u8 buf_lenl;

sys/dev/netif/ix/ixgbe_type.h

3146

u8 checksum;

sys/dev/netif/ix/ixgbe_type.h

315

u8 or_patch;

sys/dev/netif/ix/ixgbe_type.h

3150

u8 cmd;

sys/dev/netif/ix/ixgbe_type.h

3151

u8 buf_lenl;

sys/dev/netif/ix/ixgbe_type.h

3152

u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */

sys/dev/netif/ix/ixgbe_type.h

3153

u8 checksum;

sys/dev/netif/ix/ixgbe_type.h

3163

u8 port_num;

sys/dev/netif/ix/ixgbe_type.h

3164

u8 ver_sub;

sys/dev/netif/ix/ixgbe_type.h

3165

u8 ver_build;

sys/dev/netif/ix/ixgbe_type.h

3166

u8 ver_min;

sys/dev/netif/ix/ixgbe_type.h

3167

u8 ver_maj;

sys/dev/netif/ix/ixgbe_type.h

3168

u8 pad; /* end spacing to ensure length is mult. of dword */

sys/dev/netif/ix/ixgbe_type.h

3174

u8 port_num;

sys/dev/netif/ix/ixgbe_type.h

3175

u8 ver_sub;

sys/dev/netif/ix/ixgbe_type.h

3176

u8 ver_build;

sys/dev/netif/ix/ixgbe_type.h

3177

u8 ver_min;

sys/dev/netif/ix/ixgbe_type.h

3178

u8 ver_maj;

sys/dev/netif/ix/ixgbe_type.h

3203

u8 port_number;

sys/dev/netif/ix/ixgbe_type.h

3204

u8 pad2;

sys/dev/netif/ix/ixgbe_type.h

3210

u8 port_number;

sys/dev/netif/ix/ixgbe_type.h

3211

u8 command_type;

sys/dev/netif/ix/ixgbe_type.h

3217

u8 port_number;

sys/dev/netif/ix/ixgbe_type.h

3218

u8 command_type;

sys/dev/netif/ix/ixgbe_type.h

3232

u8 port_number;

sys/dev/netif/ix/ixgbe_type.h

3233

u8 pad;

sys/dev/netif/ix/ixgbe_type.h

3252

u8 cso; /* Checksum offset */

sys/dev/netif/ix/ixgbe_type.h

3253

u8 cmd; /* Descriptor control */

sys/dev/netif/ix/ixgbe_type.h

3259

u8 status; /* Descriptor status */

sys/dev/netif/ix/ixgbe_type.h

3260

u8 css; /* Checksum start */

sys/dev/netif/ix/ixgbe_type.h

3285

u8 status; /* Descriptor status */

sys/dev/netif/ix/ixgbe_type.h

3286

u8 errors; /* Descriptor Errors */

sys/dev/netif/ix/ixgbe_type.h

3544

u8 vm_pool;

sys/dev/netif/ix/ixgbe_type.h

3545

u8 flow_type;

sys/dev/netif/ix/ixgbe_type.h

3549

u8 inner_mac[6];

sys/dev/netif/ix/ixgbe_type.h

3563

u8 vm_pool;

sys/dev/netif/ix/ixgbe_type.h

3564

u8 flow_type;

sys/dev/netif/ix/ixgbe_type.h

3781

u8 lan_id;

sys/dev/netif/ix/ixgbe_type.h

3882

typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,

sys/dev/netif/ix/ixgbe_type.h

3905

s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);

sys/dev/netif/ix/ixgbe_type.h

3906

s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);

sys/dev/netif/ix/ixgbe_type.h

3907

s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *);

sys/dev/netif/ix/ixgbe_type.h

3914

s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);

sys/dev/netif/ix/ixgbe_type.h

3915

s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);

sys/dev/netif/ix/ixgbe_type.h

3948

s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);

sys/dev/netif/ix/ixgbe_type.h

3949

s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);

sys/dev/netif/ix/ixgbe_type.h

3951

s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);

sys/dev/netif/ix/ixgbe_type.h

3956

s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,

sys/dev/netif/ix/ixgbe_type.h

3958

s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,

sys/dev/netif/ix/ixgbe_type.h

3976

s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16,

sys/dev/netif/ix/ixgbe_type.h

3981

s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value);

sys/dev/netif/ix/ixgbe_type.h

3982

void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map);

sys/dev/netif/ix/ixgbe_type.h

4015

s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);

sys/dev/netif/ix/ixgbe_type.h

4016

s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);

sys/dev/netif/ix/ixgbe_type.h

4017

s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);

sys/dev/netif/ix/ixgbe_type.h

4018

s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);

sys/dev/netif/ix/ixgbe_type.h

4019

s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);

sys/dev/netif/ix/ixgbe_type.h

4025

s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,

sys/dev/netif/ix/ixgbe_type.h

4026

u8 *value);

sys/dev/netif/ix/ixgbe_type.h

4027

s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,

sys/dev/netif/ix/ixgbe_type.h

4028

u8 value);

sys/dev/netif/ix/ixgbe_type.h

4032

s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);

sys/dev/netif/ix/ixgbe_type.h

4033

s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_type.h

4035

s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);

sys/dev/netif/ix/ixgbe_type.h

4036

s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,

sys/dev/netif/ix/ixgbe_type.h

4042

u8 addr;

sys/dev/netif/ix/ixgbe_type.h

4059

u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];

sys/dev/netif/ix/ixgbe_type.h

4060

u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];

sys/dev/netif/ix/ixgbe_type.h

4061

u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];

sys/dev/netif/ix/ixgbe_type.h

4077

u8 san_mac_rar_index;

sys/dev/netif/ix/ixgbe_type.h

4084

u8 flags;

sys/dev/netif/ix/ixgbe_type.h

4088

u8 led_link_act;

sys/dev/netif/ix/ixgbe_type.h

4146

u8 IOMEM *hw_addr;

sys/dev/netif/ix/ixgbe_type.h

4161

u8 revision_id;

sys/dev/netif/ix/ixgbe_type.h

4290

u8 actions;

sys/dev/netif/ix/ixgbe_type.h

697

u8 fcoe_tc;

sys/dev/netif/ix/ixgbe_type.h

698

u8 num_tcs;

sys/dev/netif/ix/ixgbe_x550.c

140

static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)

sys/dev/netif/ix/ixgbe_x550.c

159

static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)

sys/dev/netif/ix/ixgbe_x550.c

182

u8 reg;

sys/dev/netif/ix/ixgbe_x550.c

255

u8 retry;

sys/dev/netif/ix/ixgbe_x550.c

3732

fw_cmd.port_number = (u8)hw->bus.lan_id;

sys/dev/netif/ix/ixgbe_x550.c

4222

static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)

sys/dev/netif/ix/ixgbe_x550.c

4601

s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,

sys/dev/netif/ix/ixgbe_x550.c

4602

u8 build, u8 sub, u16 len, const char *driver_ver)

sys/dev/netif/ix/ixgbe_x550.c

4617

fw_cmd.port_num = (u8)hw->bus.func;

sys/dev/netif/ix/ixgbe_x550.c

4624

fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,

sys/dev/netif/ix/ixgbe_x550.c

545

static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,

sys/dev/netif/ix/ixgbe_x550.c

561

ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,

sys/dev/netif/ix/ixgbe_x550.c

577

u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_x550.c

593

u8 addr, u16 reg, u16 val)

sys/dev/netif/ix/ixgbe_x550.h

69

s32 ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,

sys/dev/netif/ix/ixgbe_x550.h

70

u8 build, u8 ver, u16 len, const char *str);

sys/dev/raid/asr/osd_util.h

188

uCHAR u8[4];

sys/dev/raid/mpr/mpr_mapping.c

1146

u8 entry, enc_idx, phy_idx;

sys/dev/raid/mpr/mpr_mapping.c

1152

u8 add_code = MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED;

sys/dev/raid/mpr/mpr_mapping.c

120

memcpy(&config_page.Header, (u8 *) sc->dpm_pg0,

sys/dev/raid/mpr/mpr_mapping.c

122

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

1323

u8 entry, enc_idx, port_idx;

sys/dev/raid/mpr/mpr_mapping.c

1329

u8 add_code = MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED;

sys/dev/raid/mpr/mpr_mapping.c

140

memcpy(&config_page.Entry, (u8 *)dpm_entry,

sys/dev/raid/mpr/mpr_mapping.c

1493

u8 done_flag = 0, num_entries, m, i;

sys/dev/raid/mpr/mpr_mapping.c

1503

((u8 *) sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

1577

u8 enc_idx, missing_cnt, is_removed = 0;

sys/dev/raid/mpr/mpr_mapping.c

1587

u8 map_shift = MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT;

sys/dev/raid/mpr/mpr_mapping.c

1588

u8 hdr_sz = sizeof(MPI2_CONFIG_EXTENDED_PAGE_HEADER);

sys/dev/raid/mpr/mpr_mapping.c

1658

((u8 *) sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

1759

((u8 *)sc->dpm_pg0 + hdr_sz);

sys/dev/raid/mpr/mpr_mapping.c

1788

((u8 *)sc->dpm_pg0 + hdr_sz);

sys/dev/raid/mpr/mpr_mapping.c

1834

u8 enc_idx, missing_cnt, is_removed = 0;

sys/dev/raid/mpr/mpr_mapping.c

1844

u8 map_shift = MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT;

sys/dev/raid/mpr/mpr_mapping.c

1845

u8 hdr_sz = sizeof(MPI2_CONFIG_EXTENDED_PAGE_HEADER);

sys/dev/raid/mpr/mpr_mapping.c

1915

((u8 *) sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

195

memcpy(&config_page.Header, (u8 *)sc->dpm_pg0,

sys/dev/raid/mpr/mpr_mapping.c

197

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *) sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

2018

((u8 *)sc->dpm_pg0 + hdr_sz);

sys/dev/raid/mpr/mpr_mapping.c

2047

((u8 *)sc->dpm_pg0 + hdr_sz);

sys/dev/raid/mpr/mpr_mapping.c

207

memcpy(&config_page.Entry, (u8 *)dpm_entry,

sys/dev/raid/mpr/mpr_mapping.c

2097

memcpy(&config_page.Header, (u8 *)sc->dpm_pg0,

sys/dev/raid/mpr/mpr_mapping.c

2099

dpm_entry = (Mpi2DriverMap0Entry_t *) ((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

2107

memcpy(&config_page.Entry, (u8 *)dpm_entry,

sys/dev/raid/mpr/mpr_mapping.c

2155

sc->dpm_entry_used = kmalloc((sizeof(u8) * sc->max_dpm_entries),

sys/dev/raid/mpr/mpr_mapping.c

2160

sc->dpm_flush_entry = kmalloc((sizeof(u8) * sc->max_dpm_entries),

sys/dev/raid/mpr/mpr_mapping.c

2209

u8 missing_cnt, enc_idx;

sys/dev/raid/mpr/mpr_mapping.c

2404

u8 stop_device_checks = 0;

sys/dev/raid/mpr/mpr_mapping.c

264

static u8

sys/dev/raid/mpr/mpr_mapping.c

269

u8 enc_idx = 0;

sys/dev/raid/mpr/mpr_mapping.c

2743

u8 enc_idx, missing_count;

sys/dev/raid/mpr/mpr_mapping.c

2747

u8 map_shift = MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT;

sys/dev/raid/mpr/mpr_mapping.c

2748

u8 update_phy_bits = 0;

sys/dev/raid/mpr/mpr_mapping.c

2756

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

2803

(u8)(dpm_entry->MappingInformation &

sys/dev/raid/mpr/mpr_mapping.c

288

static u8

sys/dev/raid/mpr/mpr_mapping.c

2898

u8 i, num_entries;

sys/dev/raid/mpr/mpr_mapping.c

292

u8 enc_idx = 0;

sys/dev/raid/mpr/mpr_mapping.c

2949

u8 i, num_entries;

sys/dev/raid/mpr/mpr_mapping.c

313

static u8

sys/dev/raid/mpr/mpr_mapping.c

317

u8 high_missing_count = 0;

sys/dev/raid/mpr/mpr_mapping.c

318

u8 enc_idx, high_idx = MPR_ENCTABLE_BAD_IDX;

sys/dev/raid/mpr/mpr_mapping.c

344

u8 high_missing_count = 0;

sys/dev/raid/mpr/mpr_mapping.c

470

u8 high_missing_count = 0;

sys/dev/raid/mpr/mpr_mapping.c

545

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

578

dpm_entry = (Mpi2DriverMap0Entry_t *) ((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

618

dpm_entry = (Mpi2DriverMap0Entry_t *) ((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

649

u8 missing_cnt, reason = element->ReasonCode, update_dpm = 1;

sys/dev/raid/mpr/mpr_mapping.c

701

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

726

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

75

map_entry->TLR_bits = (u8)MPI2_SCSIIO_CONTROL_NO_TLR;

sys/dev/raid/mpr/mpr_mapping.c

834

dpm_entry = (Mpi2DriverMap0Entry_t *) ((u8 *)sc->dpm_pg0 +

sys/dev/raid/mpr/mpr_mapping.c

858

u8 entry;

sys/dev/raid/mpr/mpr_mapping.c

888

u8 entry;

sys/dev/raid/mpr/mpr_mapping.h

120

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD);

sys/dev/raid/mpr/mpr_sas.c

2236

u8 *response_bytes;

sys/dev/raid/mpr/mpr_sas.c

2239

u8 scsi_state = mpi_reply->SCSIState;

sys/dev/raid/mpr/mpr_sas.c

2240

u8 scsi_status = mpi_reply->SCSIStatus;

sys/dev/raid/mpr/mpr_sas.c

2280

response_bytes = (u8 *)&response_info;

sys/dev/raid/mpr/mpr_sas.c

2296

static u8

sys/dev/raid/mpr/mpr_sas.c

2300

u8 status = MPI2_SCSI_STATUS_GOOD;

sys/dev/raid/mpr/mpr_sas.c

2471

static u8

sys/dev/raid/mpr/mpr_sas.c

2476

u8 scsi_status = MPI2_SCSI_STATUS_GOOD;

sys/dev/raid/mpr/mpr_sas.c

2496

u8 *TLR_bits, TLR_on, *scsi_cdb;

sys/dev/raid/mpr/mpr_sas.c

2707

(u8)MPI2_SCSIIO_CONTROL_NO_TLR;

sys/dev/raid/mpr/mpr_sas.c

2769

*TLR_bits = (u8)MPI2_SCSIIO_CONTROL_NO_TLR;

sys/dev/raid/mpr/mpr_sas.c

2770

TLR_on = (u8)MPI2_SCSIIO_CONTROL_TLR_ON;

sys/dev/raid/mpr/mpr_sas_lsi.c

1033

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD)

sys/dev/raid/mpr/mpr_sas_lsi.c

1040

u8 buffer[MPT2SAS_MN_LEN + MPT2SAS_SN_LEN];

sys/dev/raid/mpr/mpr_sas_lsi.c

1042

u8 sas_status;

sys/dev/raid/mpr/mpr_sas_lsi.c

1084

buffer[i] = ((u8 *)ata_identify.model_number)[i + 1];

sys/dev/raid/mpr/mpr_sas_lsi.c

1085

buffer[i + 1] = ((u8 *)ata_identify.model_number)[i];

sys/dev/raid/mpr/mpr_sas_lsi.c

1090

((u8 *)ata_identify.serial_number)[i + 1];

sys/dev/raid/mpr/mpr_sas_lsi.c

1092

((u8 *)ata_identify.serial_number)[i];

sys/dev/raid/mpr/mpr_sas_lsi.c

116

static int mprsas_add_device(struct mpr_softc *sc, u16 handle, u8 linkrate);

sys/dev/raid/mpr/mpr_sas_lsi.c

118

u8 linkrate);

sys/dev/raid/mpr/mpr_sas_lsi.c

124

u64 *sas_address, u16 handle, u32 device_info, u8 *is_SATA_SSD);

sys/dev/raid/mpr/mpr_sas_lsi.c

1266

mprsas_add_pcie_device(struct mpr_softc *sc, u16 handle, u8 linkrate)

sys/dev/raid/mpr/mpr_sas_lsi.c

278

u8 foreign_config, reason;

sys/dev/raid/mpr/mpr_sas_lsi.c

799

mprsas_add_device(struct mpr_softc *sc, u16 handle, u8 linkrate)

sys/dev/raid/mpr/mpr_sas_lsi.c

811

u8 is_SATA_SSD = 0;

sys/dev/raid/mpr/mpr_sas_lsi.c

92

u8 wwid[8];

sys/dev/raid/mpr/mprvar.h

121

u8 missing_count;

sys/dev/raid/mpr/mprvar.h

122

u8 init_complete;

sys/dev/raid/mpr/mprvar.h

123

u8 TLR_bits;

sys/dev/raid/mpr/mprvar.h

124

u8 reserved2;

sys/dev/raid/mpr/mprvar.h

149

u8 missing_count;

sys/dev/raid/mpr/mprvar.h

150

u8 removal_flag;

sys/dev/raid/mpr/mprvar.h

151

u8 skip_search;

sys/dev/raid/mpr/mprvar.h

152

u8 init_complete;

sys/dev/raid/mps/mps_mapping.c

1040

u8 done_flag = 0, num_entries, m, i;

sys/dev/raid/mps/mps_mapping.c

1050

((u8 *) sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

1117

u8 enc_idx, missing_cnt, is_removed = 0;

sys/dev/raid/mps/mps_mapping.c

1127

u8 map_shift = MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT;

sys/dev/raid/mps/mps_mapping.c

1128

u8 hdr_sz = sizeof(MPI2_CONFIG_EXTENDED_PAGE_HEADER);

sys/dev/raid/mps/mps_mapping.c

1187

((u8 *) sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

119

memcpy(&config_page.Header, (u8 *) sc->dpm_pg0,

sys/dev/raid/mps/mps_mapping.c

121

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

1281

((u8 *)sc->dpm_pg0 + hdr_sz);

sys/dev/raid/mps/mps_mapping.c

1302

((u8 *)sc->dpm_pg0 + hdr_sz);

sys/dev/raid/mps/mps_mapping.c

1353

memcpy(&config_page.Header, (u8 *)sc->dpm_pg0,

sys/dev/raid/mps/mps_mapping.c

1355

dpm_entry = (Mpi2DriverMap0Entry_t *) ((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

1363

memcpy(&config_page.Entry, (u8 *)dpm_entry,

sys/dev/raid/mps/mps_mapping.c

137

memcpy(&config_page.Entry, (u8 *)dpm_entry,

sys/dev/raid/mps/mps_mapping.c

1408

sc->dpm_entry_used = kmalloc((sizeof(u8) * sc->max_dpm_entries),

sys/dev/raid/mps/mps_mapping.c

1413

sc->dpm_flush_entry = kmalloc((sizeof(u8) * sc->max_dpm_entries),

sys/dev/raid/mps/mps_mapping.c

1463

u8 missing_cnt, enc_idx;

sys/dev/raid/mps/mps_mapping.c

178

memcpy(&config_page.Header, (u8 *)sc->dpm_pg0,

sys/dev/raid/mps/mps_mapping.c

180

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *) sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

1901

u8 enc_idx, missing_count;

sys/dev/raid/mps/mps_mapping.c

1905

u8 map_shift = MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT;

sys/dev/raid/mps/mps_mapping.c

1906

u8 update_phy_bits = 0;

sys/dev/raid/mps/mps_mapping.c

191

memcpy(&config_page.Entry, (u8 *)dpm_entry,

sys/dev/raid/mps/mps_mapping.c

1914

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

1952

(u8)(dpm_entry->MappingInformation &

sys/dev/raid/mps/mps_mapping.c

2039

u8 i, num_entries;

sys/dev/raid/mps/mps_mapping.c

2096

u8 match = 0;

sys/dev/raid/mps/mps_mapping.c

2153

u8 log_full_error = 0;

sys/dev/raid/mps/mps_mapping.c

244

static u8

sys/dev/raid/mps/mps_mapping.c

249

u8 enc_idx = 0;

sys/dev/raid/mps/mps_mapping.c

268

static u8

sys/dev/raid/mps/mps_mapping.c

272

u8 enc_idx = 0;

sys/dev/raid/mps/mps_mapping.c

293

static u8

sys/dev/raid/mps/mps_mapping.c

297

u8 high_missing_count = 0;

sys/dev/raid/mps/mps_mapping.c

298

u8 enc_idx, high_idx = MPS_ENCTABLE_BAD_IDX;

sys/dev/raid/mps/mps_mapping.c

324

u8 high_missing_count = 0;

sys/dev/raid/mps/mps_mapping.c

449

u8 high_missing_count = 0;

sys/dev/raid/mps/mps_mapping.c

512

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

562

u8 missing_cnt, reason = element->ReasonCode;

sys/dev/raid/mps/mps_mapping.c

597

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

615

dpm_entry = (Mpi2DriverMap0Entry_t *)((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

687

u8 entry;

sys/dev/raid/mps/mps_mapping.c

723

(Mpi2DriverMap0Entry_t *) ((u8 *)sc->dpm_pg0 +

sys/dev/raid/mps/mps_mapping.c

74

map_entry->TLR_bits = (u8)MPI2_SCSIIO_CONTROL_NO_TLR;

sys/dev/raid/mps/mps_mapping.c

887

u8 entry, enc_idx, phy_idx;

sys/dev/raid/mps/mps_mapping.c

893

u8 add_code = MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED;

sys/dev/raid/mps/mps_sas.c

1791

u8 *TLR_bits, TLR_on;

sys/dev/raid/mps/mps_sas.c

1977

(u8)MPI2_SCSIIO_CONTROL_NO_TLR;

sys/dev/raid/mps/mps_sas.c

2037

*TLR_bits = (u8)MPI2_SCSIIO_CONTROL_NO_TLR;

sys/dev/raid/mps/mps_sas.c

2038

TLR_on = (u8)MPI2_SCSIIO_CONTROL_TLR_ON;

sys/dev/raid/mps/mps_sas_lsi.c

114

static int mpssas_add_device(struct mps_softc *sc, u16 handle, u8 linkrate);

sys/dev/raid/mps/mps_sas_lsi.c

267

u8 foreign_config;

sys/dev/raid/mps/mps_sas_lsi.c

580

mpssas_add_device(struct mps_softc *sc, u16 handle, u8 linkrate){

sys/dev/raid/mps/mps_sas_lsi.c

693

u8 buffer[MPT2SAS_MN_LEN + MPT2SAS_SN_LEN];

sys/dev/raid/mps/mps_sas_lsi.c

695

u8 sas_status;

sys/dev/raid/mps/mps_sas_lsi.c

720

buffer[i] = ((u8 *)ata_identify.model_number)[i + 1];

sys/dev/raid/mps/mps_sas_lsi.c

721

buffer[i + 1] = ((u8 *)ata_identify.model_number)[i];

sys/dev/raid/mps/mps_sas_lsi.c

726

((u8 *)ata_identify.serial_number)[i + 1];

sys/dev/raid/mps/mps_sas_lsi.c

728

((u8 *)ata_identify.serial_number)[i];

sys/dev/raid/mps/mps_sas_lsi.c

90

u8 wwid[8];

sys/dev/raid/mps/mpsvar.h

141

u8 reserved1;

sys/dev/raid/mps/mpsvar.h

142

u8 channel;

sys/dev/raid/mps/mpsvar.h

144

u8 missing_count;

sys/dev/raid/mps/mpsvar.h

145

u8 init_complete;

sys/dev/raid/mps/mpsvar.h

146

u8 TLR_bits;

sys/dev/raid/mps/mpsvar.h

147

u8 reserved2;

sys/dev/raid/mps/mpsvar.h

172

u8 missing_count;

sys/dev/raid/mps/mpsvar.h

173

u8 removal_flag;

sys/dev/raid/mps/mpsvar.h

174

u8 skip_search;

sys/dev/raid/mps/mpsvar.h

175

u8 init_complete;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1107

u8 direction;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1162

io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1166

(u8 __iomem *)((uintptr_t)ena_dev->mem_bar +

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1202

u8 idx;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1211

idx = (u8)rss->rss_ind_tbl[i].cq_idx;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

1950

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2279

const u8 *key, u16 key_len, u32 init_val)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

2334

u8 *key)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

495

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

527

static int ena_com_comp_status_to_errno(u8 comp_status)

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

799

u8 direction;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

96

u8 comp_status;

sys/dev/virtual/amazon/ena/ena-com/ena_com.c

97

u8 cmd_opcode;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

1093

static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

1096

u8 *buf;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

123

u8 __iomem *pbuf_dev_addr; /* LLQ address */

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

124

u8 *virt_addr;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

178

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

179

u8 cdesc_entry_size_in_bytes;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

184

u8 *base_buffer;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

192

u8 *curr_bounce_buf;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

202

u8 __iomem *header_addr;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

221

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

222

u8 desc_entry_size;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

223

u8 dma_addr_bits;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

232

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

244

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

287

u8 phase;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

330

u8 *debug_area_virt_addr;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

347

u8 __iomem *reg_bar;

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

687

const u8 *key, u16 key_len, u32 init_val);

sys/dev/virtual/amazon/ena/ena-com/ena_com.h

717

u8 *key);

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

108

u8 *header_src,

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

113

u8 *bounce_buffer = pkt_ctrl->curr_bounce_buf;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

140

u8 *bounce_buffer;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

595

u8 expected_phase, cdesc_phase;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.c

80

u8 *bounce_buffer)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

165

u8 numa_node)

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

60

u8 meta_valid;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

61

u8 tso_enable;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

62

u8 l3_csum_enable;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

63

u8 l4_csum_enable;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

64

u8 l4_csum_partial;

sys/dev/virtual/amazon/ena/ena-com/ena_eth_com.h

65

u8 df; /* Don't fragment */

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

100

u8 mic[IEEE80211_WEP_MICLEN]);

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

351

u8 mic[IEEE80211_WEP_MICLEN];

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

352

u8 mic0[IEEE80211_WEP_MICLEN];

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

457

static __inline u8 Lo8(u16 val)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

462

static __inline u8 Hi8(u16 val)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

477

static __inline u16 Mk16(u8 hi, u8 lo)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

530

static void tkip_mixing_phase1(u16 *TTAK, const u8 *TK, const u8 *TA, u32 IV32)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

555

static void tkip_mixing_phase2(u8 *WEPSeed, const u8 *TK, const u16 *TTAK,

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

602

wep_encrypt(u8 *key, struct mbuf *m0, u_int off, size_t data_len,

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

607

u8 S[256];

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

608

u8 *pos;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

610

#define S_SWAP(a,b) do { u8 t = S[a]; S[a] = S[b]; S[b] = t; } while(0)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

663

wep_decrypt(u8 *key, struct mbuf *m, u_int off, size_t data_len)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

666

u8 S[256];

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

667

u8 *pos, icv[4];

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

758

static __inline u32 get_le32_split(u8 b0, u8 b1, u8 b2, u8 b3)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

763

static __inline u32 get_le32(const u8 *p)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

769

static __inline void put_le32(u8 *p, u32 v)

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

815

michael_mic(struct tkip_ctx *ctx, const u8 *key,

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

817

u8 mic[IEEE80211_WEP_MICLEN])

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

90

u8 tx_rc4key[16]; /* XXX for test module; make locals? */

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

94

u8 rx_rc4key[16]; /* XXX for test module; make locals? */

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

974

u8 tid;

sys/netproto/802_11/wlan_tkip/ieee80211_crypto_tkip.c

98

static void michael_mic(struct tkip_ctx *, const u8 *key,

usr.bin/hexdump/display.c

140

bcopy(bp, &u8, sizeof(u8));

usr.bin/hexdump/display.c

141

(void)printf(pr->fmt, u8);

usr.bin/hexdump/display.c

62

u_int64_t u8;