sys/dev/misc/coremctl/coremctl.c

263

dimm_ch0 = CSR_READ_4(sc, MCH_CORE_DIMM_CH0);

sys/dev/misc/coremctl/coremctl.c

264

dimm_ch1 = CSR_READ_4(sc, MCH_CORE_DIMM_CH1);

sys/dev/misc/coremctl/coremctl.c

281

ptm_ctl = CSR_READ_4(sc, MCH_CORE_DDR_PTM_CTL0);

sys/dev/misc/coremctl/coremctl.c

369

*val = CSR_READ_4(sc, reg);

sys/dev/misc/ecc/ecc_e3.c

216

CSR_READ_4(sc, MCH_E3_ERRLOG0_C0));

sys/dev/misc/ecc/ecc_e3.c

218

CSR_READ_4(sc, MCH_E3_ERRLOG0_C1));

sys/dev/misc/ecc/ecc_e3.c

221

dimm_ch0 = CSR_READ_4(sc, MCH_CORE_DIMM_CH0);

sys/dev/misc/ecc/ecc_e3.c

222

dimm_ch1 = CSR_READ_4(sc, MCH_CORE_DIMM_CH1);

sys/dev/misc/ecc/ecc_e3.c

431

err0 = CSR_READ_4(sc, chan->chan_errlog0);

sys/dev/netif/age/if_age.c

1359

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

1706

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

1733

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

1864

status = CSR_READ_4(sc, AGE_INTR_STATUS);

sys/dev/netif/age/if_age.c

197

v = CSR_READ_4(sc, AGE_MDIO);

sys/dev/netif/age/if_age.c

2211

if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/netif/age/if_age.c

2218

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/netif/age/if_age.c

2227

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/netif/age/if_age.c

229

v = CSR_READ_4(sc, AGE_MDIO);

sys/dev/netif/age/if_age.c

2334

reg = CSR_READ_4(sc, AGE_MASTER_CFG);

sys/dev/netif/age/if_age.c

2376

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/netif/age/if_age.c

2396

reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);

sys/dev/netif/age/if_age.c

2403

reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);

sys/dev/netif/age/if_age.c

2494

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2551

CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));

sys/dev/netif/age/if_age.c

2555

CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);

sys/dev/netif/age/if_age.c

2557

CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);

sys/dev/netif/age/if_age.c

2559

if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)

sys/dev/netif/age/if_age.c

2601

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2607

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/netif/age/if_age.c

2613

if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &

sys/dev/netif/age/if_age.c

2628

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2634

reg = CSR_READ_4(sc, AGE_DMA_CFG);

sys/dev/netif/age/if_age.c

2640

if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &

sys/dev/netif/age/if_age.c

2794

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

280

reg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

2810

rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);

sys/dev/netif/age/if_age.c

282

CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |

sys/dev/netif/age/if_age.c

377

reg = CSR_READ_4(sc, AGE_SPI_CTRL);

sys/dev/netif/age/if_age.c

468

ea[0] = CSR_READ_4(sc, AGE_PAR0);

sys/dev/netif/age/if_age.c

469

ea[1] = CSR_READ_4(sc, AGE_PAR1);

sys/dev/netif/age/if_age.c

577

sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>

sys/dev/netif/age/if_age.c

599

CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),

sys/dev/netif/age/if_age.c

600

CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));

sys/dev/netif/alc/if_alc.c

1019

val = CSR_READ_4(sc, ALC_LPI_CTL);

sys/dev/netif/alc/if_alc.c

1068

gphy = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/netif/alc/if_alc.c

1123

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/netif/alc/if_alc.c

1207

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/netif/alc/if_alc.c

1245

val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);

sys/dev/netif/alc/if_alc.c

1251

CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);

sys/dev/netif/alc/if_alc.c

1253

CSR_READ_4(sc, ALC_PCIE_PHYMISC) |

sys/dev/netif/alc/if_alc.c

1257

val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);

sys/dev/netif/alc/if_alc.c

1289

val = CSR_READ_4(sc, ALC_PDLL_TRNS1);

sys/dev/netif/alc/if_alc.c

1292

val = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

1324

ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER);

sys/dev/netif/alc/if_alc.c

1426

sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>

sys/dev/netif/alc/if_alc.c

1438

CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,

sys/dev/netif/alc/if_alc.c

1439

CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);

sys/dev/netif/alc/if_alc.c

275

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/netif/alc/if_alc.c

2894

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

2943

CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/netif/alc/if_alc.c

2949

CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/netif/alc/if_alc.c

2978

*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);

sys/dev/netif/alc/if_alc.c

2984

*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);

sys/dev/netif/alc/if_alc.c

302

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/netif/alc/if_alc.c

3077

status = CSR_READ_4(sc, ALC_INTR_STATUS);

sys/dev/netif/alc/if_alc.c

3136

prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);

sys/dev/netif/alc/if_alc.c

340

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/netif/alc/if_alc.c

3443

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/netif/alc/if_alc.c

3448

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/netif/alc/if_alc.c

3459

reg = CSR_READ_4(sc, ALC_MISC2);

sys/dev/netif/alc/if_alc.c

3489

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/netif/alc/if_alc.c

3498

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

3505

if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)

sys/dev/netif/alc/if_alc.c

3514

if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/netif/alc/if_alc.c

3521

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/netif/alc/if_alc.c

3534

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

3544

reg = CSR_READ_4(sc, ALC_MISC3);

sys/dev/netif/alc/if_alc.c

3548

reg = CSR_READ_4(sc, ALC_MISC);

sys/dev/netif/alc/if_alc.c

3559

CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |

sys/dev/netif/alc/if_alc.c

3618

CSR_READ_4(sc, ALC_WOL_CFG);

sys/dev/netif/alc/if_alc.c

366

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/netif/alc/if_alc.c

3698

reg = CSR_READ_4(sc, ALC_MASTER_CFG);

sys/dev/netif/alc/if_alc.c

3826

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/netif/alc/if_alc.c

3842

reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);

sys/dev/netif/alc/if_alc.c

3980

reg = CSR_READ_4(sc, ALC_DMA_CFG);

sys/dev/netif/alc/if_alc.c

4031

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

4037

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/netif/alc/if_alc.c

4060

cfg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/netif/alc/if_alc.c

4068

cfg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/netif/alc/if_alc.c

4080

reg = CSR_READ_4(sc, ALC_RXQ_CFG);

sys/dev/netif/alc/if_alc.c

4093

reg = CSR_READ_4(sc, ALC_TXQ_CFG);

sys/dev/netif/alc/if_alc.c

4100

reg = CSR_READ_4(sc, ALC_IDLE_STATUS);

sys/dev/netif/alc/if_alc.c

417

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

4207

reg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

4227

rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);

sys/dev/netif/alc/if_alc.c

461

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/netif/alc/if_alc.c

492

v = CSR_READ_4(sc, ALC_MDIO);

sys/dev/netif/alc/if_alc.c

674

opt = CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/netif/alc/if_alc.c

675

if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&

sys/dev/netif/alc/if_alc.c

676

(CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {

sys/dev/netif/alc/if_alc.c

688

CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/netif/alc/if_alc.c

713

CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);

sys/dev/netif/alc/if_alc.c

715

CSR_READ_4(sc, ALC_WOL_CFG);

sys/dev/netif/alc/if_alc.c

717

CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |

sys/dev/netif/alc/if_alc.c

721

if ((CSR_READ_4(sc, ALC_TWSI_CFG) &

sys/dev/netif/alc/if_alc.c

739

CSR_READ_4(sc, ALC_OPT_CFG);

sys/dev/netif/alc/if_alc.c

776

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/netif/alc/if_alc.c

785

reg = CSR_READ_4(sc, ALC_SLD);

sys/dev/netif/alc/if_alc.c

798

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/netif/alc/if_alc.c

802

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/netif/alc/if_alc.c

813

reg = CSR_READ_4(sc, ALC_EEPROM_LD);

sys/dev/netif/alc/if_alc.c

831

ea[0] = CSR_READ_4(sc, ALC_PAR0);

sys/dev/netif/alc/if_alc.c

832

ea[1] = CSR_READ_4(sc, ALC_PAR1);

sys/dev/netif/alc/if_alc.c

848

pmcfg = CSR_READ_4(sc, ALC_PM_CFG);

sys/dev/netif/alc/if_alc.c

987

val = CSR_READ_4(sc, ALC_GPHY_CFG);

sys/dev/netif/ale/if_ale.c

1397

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/netif/ale/if_ale.c

1419

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

1430

reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);

sys/dev/netif/ale/if_ale.c

1816

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

1849

CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/netif/ale/if_ale.c

1854

CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/netif/ale/if_ale.c

1874

*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);

sys/dev/netif/ale/if_ale.c

1879

*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);

sys/dev/netif/ale/if_ale.c

1971

status = CSR_READ_4(sc, ALE_INTR_STATUS);

sys/dev/netif/ale/if_ale.c

202

v = CSR_READ_4(sc, ALE_MDIO);

sys/dev/netif/ale/if_ale.c

2281

CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);

sys/dev/netif/ale/if_ale.c

2286

if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)

sys/dev/netif/ale/if_ale.c

2293

if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)

sys/dev/netif/ale/if_ale.c

2340

CSR_READ_4(sc, ALE_WOL_CFG);

sys/dev/netif/ale/if_ale.c

238

v = CSR_READ_4(sc, ALE_MDIO);

sys/dev/netif/ale/if_ale.c

2397

reg = CSR_READ_4(sc, ALE_MASTER_CFG);

sys/dev/netif/ale/if_ale.c

2461

reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/netif/ale/if_ale.c

2570

reg = CSR_READ_4(sc, ALE_TXQ_CFG);

sys/dev/netif/ale/if_ale.c

2573

reg = CSR_READ_4(sc, ALE_RXQ_CFG);

sys/dev/netif/ale/if_ale.c

2576

reg = CSR_READ_4(sc, ALE_DMA_CFG);

sys/dev/netif/ale/if_ale.c

2607

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

2614

reg = CSR_READ_4(sc, ALE_IDLE_STATUS);

sys/dev/netif/ale/if_ale.c

2678

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

2696

rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

290

reg = CSR_READ_4(sc, ALE_MAC_CFG);

sys/dev/netif/ale/if_ale.c

357

reg = CSR_READ_4(sc, ALE_SPI_CTRL);

sys/dev/netif/ale/if_ale.c

369

CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |

sys/dev/netif/ale/if_ale.c

373

reg = CSR_READ_4(sc, ALE_TWSI_CTRL);

sys/dev/netif/ale/if_ale.c

386

ea[0] = CSR_READ_4(sc, ALE_PAR0);

sys/dev/netif/ale/if_ale.c

387

ea[1] = CSR_READ_4(sc, ALE_PAR1);

sys/dev/netif/ale/if_ale.c

519

if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {

sys/dev/netif/ale/if_ale.c

548

sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>

sys/dev/netif/ale/if_ale.c

561

txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);

sys/dev/netif/ale/if_ale.c

562

rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);

sys/dev/netif/bfe/if_bfe.c

1002

*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;

sys/dev/netif/bfe/if_bfe.c

1052

*val++ += CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

1055

*val++ += CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

1064

chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;

sys/dev/netif/bfe/if_bfe.c

1106

status = CSR_READ_4(sc, BFE_DMARX_STAT);

sys/dev/netif/bfe/if_bfe.c

1159

istat = CSR_READ_4(sc, BFE_ISTAT);

sys/dev/netif/bfe/if_bfe.c

1160

imask = CSR_READ_4(sc, BFE_IMASK);

sys/dev/netif/bfe/if_bfe.c

1169

CSR_READ_4(sc, BFE_ISTAT);

sys/dev/netif/bfe/if_bfe.c

1177

flag = CSR_READ_4(sc, BFE_DMATX_STAT);

sys/dev/netif/bfe/if_bfe.c

1181

flag = CSR_READ_4(sc, BFE_DMARX_STAT);

sys/dev/netif/bfe/if_bfe.c

655

val = CSR_READ_4(sc, BFE_SBINTVEC);

sys/dev/netif/bfe/if_bfe.c

659

val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);

sys/dev/netif/bfe/if_bfe.c

673

CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

675

CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfe.c

699

CSR_READ_4(sc, BFE_IMASK);

sys/dev/netif/bfe/if_bfe.c

718

val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);

sys/dev/netif/bfe/if_bfe.c

726

if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)

sys/dev/netif/bfe/if_bfe.c

745

val = CSR_READ_4(sc, BFE_DEVCTRL);

sys/dev/netif/bfe/if_bfe.c

748

else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {

sys/dev/netif/bfe/if_bfe.c

793

if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)

sys/dev/netif/bfe/if_bfe.c

805

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/netif/bfe/if_bfe.c

822

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/netif/bfe/if_bfe.c

826

if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)

sys/dev/netif/bfe/if_bfe.c

828

val = CSR_READ_4(sc, BFE_SBIMSTATE);

sys/dev/netif/bfe/if_bfe.c

834

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/netif/bfe/if_bfe.c

839

CSR_READ_4(sc, BFE_SBTMSLOW);

sys/dev/netif/bfe/if_bfe.c

870

val = CSR_READ_4(sc, BFE_RXCONF);

sys/dev/netif/bfe/if_bfe.c

961

ptr[i/2] = CSR_READ_4(sc, 4096 + i);

sys/dev/netif/bfe/if_bfe.c

971

uint32_t val = CSR_READ_4(sc, reg);

sys/dev/netif/bfe/if_bfereg.h

419

CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)

sys/dev/netif/bfe/if_bfereg.h

422

CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)

sys/dev/netif/bge/if_bge.c

1349

clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;

sys/dev/netif/bge/if_bge.c

1429

CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */

sys/dev/netif/bge/if_bge.c

1494

if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)

sys/dev/netif/bge/if_bge.c

1511

if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)

sys/dev/netif/bge/if_bge.c

1634

(CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);

sys/dev/netif/bge/if_bge.c

1754

if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))

sys/dev/netif/bge/if_bge.c

1899

val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);

sys/dev/netif/bge/if_bge.c

2141

misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;

sys/dev/netif/bge/if_bge.c

2762

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;

sys/dev/netif/bge/if_bge.c

2778

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &

sys/dev/netif/bge/if_bge.c

2823

CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==

sys/dev/netif/bge/if_bge.c

2839

status = CSR_READ_4(sc, BGE_VCPU_STATUS);

sys/dev/netif/bge/if_bge.c

2842

ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);

sys/dev/netif/bge/if_bge.c

2953

val = CSR_READ_4(sc, BGE_MARB_MODE);

sys/dev/netif/bge/if_bge.c

2963

val = CSR_READ_4(sc, BGE_MAC_MODE);

sys/dev/netif/bge/if_bge.c

2972

val = CSR_READ_4(sc, BGE_VCPU_STATUS);

sys/dev/netif/bge/if_bge.c

3013

serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);

sys/dev/netif/bge/if_bge.c

3025

v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);

sys/dev/netif/bge/if_bge.c

3461

*s = CSR_READ_4(sc, BGE_RX_STATS + i);

sys/dev/netif/bge/if_bge.c

3481

CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))

sys/dev/netif/bge/if_bge.c

3823

mode = CSR_READ_4(sc, BGE_TX_MODE);

sys/dev/netif/bge/if_bge.c

3831

mode = CSR_READ_4(sc, BGE_RX_MODE);

sys/dev/netif/bge/if_bge.c

3848

CSR_READ_4(sc, BGE_MSI_MODE));

sys/dev/netif/bge/if_bge.c

3914

sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);

sys/dev/netif/bge/if_bge.c

3985

if (CSR_READ_4(sc, BGE_MAC_STS) &

sys/dev/netif/bge/if_bge.c

3994

if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)

sys/dev/netif/bge/if_bge.c

4810

CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);

sys/dev/netif/bge/if_bge.c

4822

CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);

sys/dev/netif/bge/if_bge.c

4834

CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);

sys/dev/netif/bge/if_bge.c

4846

CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);

sys/dev/netif/bge/if_bge.c

4858

CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);

sys/dev/netif/bge/if_bge.c

4870

CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);

sys/dev/netif/bge/if_bge.c

4882

CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);

sys/dev/netif/bge/if_bge.c

4894

CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);

sys/dev/netif/bge/if_bge.c

5057

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/netif/bge/if_bge.c

5068

status = CSR_READ_4(sc, BGE_MAC_STS);

sys/dev/netif/bge/if_bge.c

5080

msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);

sys/dev/netif/bge/if_bge.c

5150

CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);

sys/dev/netif/bge/if_bge.c

5153

if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &

sys/dev/netif/bge/if_bge.c

5243

CSR_READ_4(sc, BGE_RX_CPU_EVENT) |

sys/dev/netif/bge/if_bge.c

541

CSR_READ_4(sc, off);

sys/dev/netif/bge/if_bge.c

553

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)

sys/dev/netif/bge/if_bge.c

561

access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);

sys/dev/netif/bge/if_bge.c

568

if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {

sys/dev/netif/bge/if_bge.c

580

byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);

sys/dev/netif/bge/if_bge.c

589

CSR_READ_4(sc, BGE_NVRAM_SWARB);

sys/dev/netif/bge/if_bge.c

645

if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)

sys/dev/netif/bge/if_bge.c

655

byte = CSR_READ_4(sc, BGE_EE_DATA);

sys/dev/netif/bge/if_bge.c

708

val = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/netif/bge/if_bge.c

711

val = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/netif/bge/if_bge.c

763

if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {

sys/dev/netif/bge/if_bge.c

765

CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */

sys/dev/netif/bge/if_bge.c

829

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &

sys/dev/netif/bge/if_bgevar.h

102

val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \

sys/dev/netif/bge/if_bgevar.h

81

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

sys/dev/netif/bge/if_bgevar.h

84

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

sys/dev/netif/bnx/if_bnx.c

1121

mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);

sys/dev/netif/bnx/if_bnx.c

1128

val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);

sys/dev/netif/bnx/if_bnx.c

1136

val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);

sys/dev/netif/bnx/if_bnx.c

1140

mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);

sys/dev/netif/bnx/if_bnx.c

1147

val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);

sys/dev/netif/bnx/if_bnx.c

1155

val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);

sys/dev/netif/bnx/if_bnx.c

1197

mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &

sys/dev/netif/bnx/if_bnx.c

1276

if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)

sys/dev/netif/bnx/if_bnx.c

1293

if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)

sys/dev/netif/bnx/if_bnx.c

1516

val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &

sys/dev/netif/bnx/if_bnx.c

1542

if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))

sys/dev/netif/bnx/if_bnx.c

1653

dmactl = CSR_READ_4(sc, dmactl_reg);

sys/dev/netif/bnx/if_bnx.c

1679

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |

sys/dev/netif/bnx/if_bnx.c

1696

CSR_READ_4(sc, ctrl_reg) |

sys/dev/netif/bnx/if_bnx.c

1714

val |= CSR_READ_4(sc, BGE_RDMA_MODE) &

sys/dev/netif/bnx/if_bnx.c

1739

if (CSR_READ_4(sc, BGE_RDMA_LENGTH + (i << 2)) > thresh)

sys/dev/netif/bnx/if_bnx.c

1752

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |

sys/dev/netif/bnx/if_bnx.c

2271

if (CSR_READ_4(sc, BGE_SGDIG_STS) &

sys/dev/netif/bnx/if_bnx.c

2277

if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &

sys/dev/netif/bnx/if_bnx.c

2581

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;

sys/dev/netif/bnx/if_bnx.c

2587

if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)

sys/dev/netif/bnx/if_bnx.c

2623

CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==

sys/dev/netif/bnx/if_bnx.c

2710

val = CSR_READ_4(sc, BGE_MAC_MODE);

sys/dev/netif/bnx/if_bnx.c

2745

serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);

sys/dev/netif/bnx/if_bnx.c

2759

v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);

sys/dev/netif/bnx/if_bnx.c

2953

val = CSR_READ_4(sc, BGE_FLOW_ATTN);

sys/dev/netif/bnx/if_bnx.c

2960

val = CSR_READ_4(sc, BGE_MSI_STATUS);

sys/dev/netif/bnx/if_bnx.c

2967

val = CSR_READ_4(sc, BGE_RDMA_STATUS);

sys/dev/netif/bnx/if_bnx.c

2974

val = CSR_READ_4(sc, BGE_WDMA_STATUS);

sys/dev/netif/bnx/if_bnx.c

3350

*s = CSR_READ_4(sc, BGE_RX_STATS + i);

sys/dev/netif/bnx/if_bnx.c

3360

val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);

sys/dev/netif/bnx/if_bnx.c

3367

CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) &

sys/dev/netif/bnx/if_bnx.c

3663

mode = CSR_READ_4(sc, BGE_TX_MODE);

sys/dev/netif/bnx/if_bnx.c

3668

mode |= CSR_READ_4(sc, BGE_TX_MODE) &

sys/dev/netif/bnx/if_bnx.c

3705

CSR_READ_4(sc, BGE_MSI_MODE));

sys/dev/netif/bnx/if_bnx.c

3817

if (CSR_READ_4(sc, BGE_MAC_STS) &

sys/dev/netif/bnx/if_bnx.c

3826

if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)

sys/dev/netif/bnx/if_bnx.c

440

if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)

sys/dev/netif/bnx/if_bnx.c

450

byte = CSR_READ_4(sc, BGE_EE_DATA);

sys/dev/netif/bnx/if_bnx.c

503

val = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/netif/bnx/if_bnx.c

506

val = CSR_READ_4(sc, BGE_MI_COMM);

sys/dev/netif/bnx/if_bnx.c

5078

if ((CSR_READ_4(sc, reg) & bit) == 0)

sys/dev/netif/bnx/if_bnx.c

5089

status = CSR_READ_4(sc, BGE_MAC_STS);

sys/dev/netif/bnx/if_bnx.c

5101

msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);

sys/dev/netif/bnx/if_bnx.c

554

if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {

sys/dev/netif/bnx/if_bnx.c

556

CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */

sys/dev/netif/bnx/if_bnx.c

617

mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &

sys/dev/netif/bnx/if_bnxvar.h

102

val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \

sys/dev/netif/bnx/if_bnxvar.h

81

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

sys/dev/netif/bnx/if_bnxvar.h

84

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

sys/dev/netif/dc/if_dc.c

1357

if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {

sys/dev/netif/dc/if_dc.c

1362

isr = CSR_READ_4(sc, DC_ISR);

sys/dev/netif/dc/if_dc.c

1384

watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);

sys/dev/netif/dc/if_dc.c

1425

watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);

sys/dev/netif/dc/if_dc.c

1507

if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))

sys/dev/netif/dc/if_dc.c

2065

*(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0);

sys/dev/netif/dc/if_dc.c

2066

*(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1);

sys/dev/netif/dc/if_dc.c

2731

r = CSR_READ_4(sc, DC_10BTSTAT);

sys/dev/netif/dc/if_dc.c

2745

r = CSR_READ_4(sc, DC_ISR);

sys/dev/netif/dc/if_dc.c

2816

isr = CSR_READ_4(sc, DC_ISR);

sys/dev/netif/dc/if_dc.c

2865

status = CSR_READ_4(sc, DC_ISR);

sys/dev/netif/dc/if_dc.c

2875

u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED);

sys/dev/netif/dc/if_dc.c

2943

if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0)

sys/dev/netif/dc/if_dc.c

2948

if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)

sys/dev/netif/dc/if_dc.c

2956

while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&

sys/dev/netif/dc/if_dc.c

328

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/dc/if_dc.c

331

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/dc/if_dc.c

342

CSR_READ_4(sc, DC_BUSCTL);

sys/dev/netif/dc/if_dc.c

378

if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {

sys/dev/netif/dc/if_dc.c

494

r = CSR_READ_4(sc, DC_SIO);

sys/dev/netif/dc/if_dc.c

516

*dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff;

sys/dev/netif/dc/if_dc.c

519

*dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8;

sys/dev/netif/dc/if_dc.c

557

if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)

sys/dev/netif/dc/if_dc.c

627

CSR_READ_4(sc, DC_SIO);

sys/dev/netif/dc/if_dc.c

630

if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)

sys/dev/netif/dc/if_dc.c

826

rval = CSR_READ_4(sc, DC_PN_MII);

sys/dev/netif/dc/if_dc.c

865

rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;

sys/dev/netif/dc/if_dc.c

875

phy_reg = CSR_READ_4(sc, DC_NETCFG);

sys/dev/netif/dc/if_dc.c

905

if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))

sys/dev/netif/dc/if_dc.c

950

phy_reg = CSR_READ_4(sc, DC_NETCFG);

sys/dev/netif/et/if_et.c

1068

intrs = CSR_READ_4(sc, ET_INTR_STATUS);

sys/dev/netif/et/if_et.c

1279

if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {

sys/dev/netif/et/if_et.c

1348

pktfilt = CSR_READ_4(sc, ET_PKTFILT);

sys/dev/netif/et/if_et.c

1349

rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL);

sys/dev/netif/et/if_et.c

1771

if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) {

sys/dev/netif/et/if_et.c

1792

val = CSR_READ_4(sc, ET_MAC_CFG1);

sys/dev/netif/et/if_et.c

1806

val = CSR_READ_4(sc, ET_MAC_CFG1);

sys/dev/netif/et/if_et.c

2025

tx_done = CSR_READ_4(sc, ET_TX_DONE_POS);

sys/dev/netif/et/if_et.c

2225

cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);

sys/dev/netif/et/if_et.c

2231

ctrl = CSR_READ_4(sc, ET_MAC_CTRL);

sys/dev/netif/et/if_et.c

453

val = CSR_READ_4(sc, ET_MII_IND);

sys/dev/netif/et/if_et.c

467

val = CSR_READ_4(sc, ET_MII_STAT);

sys/dev/netif/et/if_et.c

496

val = CSR_READ_4(sc, ET_MII_IND);

sys/dev/netif/fxp/if_fxp.c

2022

while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0

sys/dev/netif/fxp/if_fxp.c

2042

while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&

sys/dev/netif/iwi/if_iwi.c

1639

hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);

sys/dev/netif/iwi/if_iwi.c

1681

hw = CSR_READ_4(sc, txq->csr_ridx);

sys/dev/netif/iwi/if_iwi.c

1733

if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff) {

sys/dev/netif/iwi/if_iwi.c

2154

if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)

sys/dev/netif/iwi/if_iwi.c

2161

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/netif/iwi/if_iwi.c

2175

tmp = CSR_READ_4(sc, IWI_CSR_CTL);

sys/dev/netif/iwi/if_iwi.c

2182

if (CSR_READ_4(sc, IWI_CSR_CTL) & IWI_CTL_CLOCK_READY)

sys/dev/netif/iwi/if_iwi.c

2192

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/netif/iwi/if_iwi.c

2197

tmp = CSR_READ_4(sc, IWI_CSR_CTL);

sys/dev/netif/iwi/if_iwi.c

2414

CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST) |

sys/dev/netif/iwi/if_iwi.c

2417

if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)

sys/dev/netif/iwi/if_iwi.c

2430

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/netif/iwi/if_iwi.c

2530

sentinel = CSR_READ_4(sc, IWI_CSR_AUTOINC_ADDR);

sys/dev/netif/iwi/if_iwi.c

2533

tmp = CSR_READ_4(sc, IWI_CSR_RST);

sys/dev/netif/iwi/if_iwi.c

2564

tmp = CSR_READ_4(sc, IWI_CSR_CTL);

sys/dev/netif/iwi/if_iwi.c

268

return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA);

sys/dev/netif/iwi/if_iwi.c

3338

return (CSR_READ_4(sc, IWI_CSR_IO) & IWI_IO_RADIO_ENABLED) == 0;

sys/dev/netif/iwi/if_iwi.c

3400

size = min(CSR_READ_4(sc, IWI_CSR_TABLE0_SIZE), 128 - 1);

sys/dev/netif/iwi/if_iwi.c

3546

txrate = CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE);

sys/dev/netif/iwi/if_iwi.c

995

iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE));

sys/dev/netif/jme/if_jme.c

1554

gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;

sys/dev/netif/jme/if_jme.c

1555

pmcs = CSR_READ_4(sc, JME_PMCS);

sys/dev/netif/jme/if_jme.c

1984

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

2028

rxmac = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

2030

txmac = CSR_READ_4(sc, JME_TXMAC);

sys/dev/netif/jme/if_jme.c

2032

txpause = CSR_READ_4(sc, JME_TXPFC);

sys/dev/netif/jme/if_jme.c

2047

CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &

sys/dev/netif/jme/if_jme.c

2053

CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |

sys/dev/netif/jme/if_jme.c

2060

gp1 = CSR_READ_4(sc, JME_GPREG1);

sys/dev/netif/jme/if_jme.c

2120

status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);

sys/dev/netif/jme/if_jme.c

2127

status = CSR_READ_4(sc, JME_INTR_STATUS);

sys/dev/netif/jme/if_jme.c

2604

val = CSR_READ_4(sc, JME_GPREG1);

sys/dev/netif/jme/if_jme.c

2607

CSR_READ_4(sc, JME_GHC);

sys/dev/netif/jme/if_jme.c

2612

CSR_READ_4(sc, JME_GHC);

sys/dev/netif/jme/if_jme.c

2621

val = CSR_READ_4(sc, JME_GPREG1);

sys/dev/netif/jme/if_jme.c

2624

CSR_READ_4(sc, JME_GHC);

sys/dev/netif/jme/if_jme.c

2629

val = CSR_READ_4(sc, JME_GPREG1);

sys/dev/netif/jme/if_jme.c

2632

CSR_READ_4(sc, JME_GHC);

sys/dev/netif/jme/if_jme.c

2635

val = CSR_READ_4(sc, JME_TXCSR);

sys/dev/netif/jme/if_jme.c

2637

val = CSR_READ_4(sc, JME_RXCSR);

sys/dev/netif/jme/if_jme.c

2640

CSR_READ_4(sc, JME_TXCSR);

sys/dev/netif/jme/if_jme.c

2641

CSR_READ_4(sc, JME_RXCSR);

sys/dev/netif/jme/if_jme.c

2646

val = CSR_READ_4(sc, JME_GPREG1);

sys/dev/netif/jme/if_jme.c

2649

CSR_READ_4(sc, JME_GHC);

sys/dev/netif/jme/if_jme.c

2799

reg = CSR_READ_4(sc, JME_PMCS);

sys/dev/netif/jme/if_jme.c

2808

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

2816

reg = CSR_READ_4(sc, JME_GPREG0);

sys/dev/netif/jme/if_jme.c

2918

CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);

sys/dev/netif/jme/if_jme.c

2966

reg = CSR_READ_4(sc, JME_TXCSR);

sys/dev/netif/jme/if_jme.c

2973

if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)

sys/dev/netif/jme/if_jme.c

2986

reg = CSR_READ_4(sc, JME_RXCSR);

sys/dev/netif/jme/if_jme.c

2993

if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)

sys/dev/netif/jme/if_jme.c

301

if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)

sys/dev/netif/jme/if_jme.c

3107

reg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

3125

rxcfg = CSR_READ_4(sc, JME_RXMAC);

sys/dev/netif/jme/if_jme.c

3327

status = CSR_READ_4(sc, JME_INTR_STATUS);

sys/dev/netif/jme/if_jme.c

337

if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)

sys/dev/netif/jme/if_jme.c

3861

status = CSR_READ_4(sc, JME_INTR_STATUS);

sys/dev/netif/jme/if_jme.c

4018

val = CSR_READ_4(sc, JME_PHYPWR);

sys/dev/netif/jme/if_jme.c

4042

val = CSR_READ_4(sc, JME_PHYPWR);

sys/dev/netif/jme/if_jme.c

564

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/netif/jme/if_jme.c

579

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/netif/jme/if_jme.c

589

reg = CSR_READ_4(sc, JME_SMBINTF);

sys/dev/netif/jme/if_jme.c

645

par0 = CSR_READ_4(sc, JME_PAR0);

sys/dev/netif/jme/if_jme.c

646

par1 = CSR_READ_4(sc, JME_PAR1);

sys/dev/netif/jme/if_jme.c

824

reg = CSR_READ_4(sc, JME_CHIPMODE);

sys/dev/netif/jme/if_jme.c

890

reg = CSR_READ_4(sc, JME_SMBCSR);

sys/dev/netif/jme/if_jme.c

907

sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &

sys/dev/netif/lge/if_lge.c

1039

status = CSR_READ_4(sc, LGE_ISR);

sys/dev/netif/lge/if_lge.c

199

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/lge/if_lge.c

202

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/lge/if_lge.c

205

CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | (x))

sys/dev/netif/lge/if_lge.c

208

CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~(x))

sys/dev/netif/lge/if_lge.c

223

if ((CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ) == 0)

sys/dev/netif/lge/if_lge.c

232

val = CSR_READ_4(sc, LGE_EEDATA);

sys/dev/netif/lge/if_lge.c

273

if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)

sys/dev/netif/lge/if_lge.c

282

return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);

sys/dev/netif/lge/if_lge.c

295

if ((CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY) == 0)

sys/dev/netif/lge/if_lge.c

387

if ((CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST) == 0)

sys/dev/netif/lge/if_lge.c

531

if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)

sys/dev/netif/lge/if_lge.c

652

CSR_READ_4(sc, LGE_ISR);

sys/dev/netif/lge/if_lge.c

997

IFNET_STAT_INC(ifp, collisions, CSR_READ_4(sc, LGE_STATSVAL));

sys/dev/netif/lge/if_lge.c

999

IFNET_STAT_INC(ifp, collisions, CSR_READ_4(sc, LGE_STATSVAL));

sys/dev/netif/mii_layer/dcphy.c

238

mode = CSR_READ_4(dc_sc, DC_NETCFG);

sys/dev/netif/mii_layer/dcphy.c

304

reg = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/netif/mii_layer/dcphy.c

350

reg = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/netif/mii_layer/dcphy.c

354

if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) {

sys/dev/netif/mii_layer/dcphy.c

356

tstat = CSR_READ_4(dc_sc, DC_10BTSTAT);

sys/dev/netif/mii_layer/dcphy.c

408

if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)

sys/dev/netif/mii_layer/dcphy.c

412

if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)

sys/dev/netif/mii_layer/dcphy.c

68

CSR_READ_4(sc, reg) | x)

sys/dev/netif/mii_layer/dcphy.c

72

CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/mii_layer/pnphy.c

265

reg = CSR_READ_4(dc_sc, DC_ISR);

sys/dev/netif/mii_layer/pnphy.c

270

if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL)

sys/dev/netif/mii_layer/pnphy.c

274

if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX)

sys/dev/netif/mii_layer/pnphy.c

67

CSR_READ_4(sc, reg) | x)

sys/dev/netif/mii_layer/pnphy.c

71

CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/msk/if_msk.c

1069

val = CSR_READ_4(sc, B2_GP_IO);

sys/dev/netif/msk/if_msk.c

1072

CSR_READ_4(sc, B2_GP_IO);

sys/dev/netif/msk/if_msk.c

1268

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/netif/msk/if_msk.c

1270

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

1809

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

1811

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/netif/msk/if_msk.c

2727

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

2729

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/netif/msk/if_msk.c

3038

status = CSR_READ_4(sc, B0_HWE_ISRC);

sys/dev/netif/msk/if_msk.c

3104

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/netif/msk/if_msk.c

3253

status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);

sys/dev/netif/msk/if_msk.c

3280

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

3286

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

3484

reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));

sys/dev/netif/msk/if_msk.c

3583

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/netif/msk/if_msk.c

3585

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

3671

CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));

sys/dev/netif/msk/if_msk.c

3701

CSR_READ_4(sc, B0_HWE_IMSK);

sys/dev/netif/msk/if_msk.c

3703

CSR_READ_4(sc, B0_IMSK);

sys/dev/netif/msk/if_msk.c

3714

val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));

sys/dev/netif/msk/if_msk.c

3719

val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));

sys/dev/netif/msk/if_mskreg.h

2145

CSR_READ_4((sc_if)->msk_softc, (reg))

sys/dev/netif/my/if_my.c

1164

if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {

sys/dev/netif/my/if_my.c

1185

if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {

sys/dev/netif/my/if_my.c

1187

(CSR_READ_4(sc, MY_TSR) & MY_NCRMask));

sys/dev/netif/my/if_my.c

1228

status = CSR_READ_4(sc, MY_ISR);

sys/dev/netif/my/if_my.c

137

#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)

sys/dev/netif/my/if_my.c

138

#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/my/if_my.c

169

miir = CSR_READ_4(sc, MY_MANAGEMENT);

sys/dev/netif/my/if_my.c

232

miir = CSR_READ_4(sc, MY_MANAGEMENT);

sys/dev/netif/my/if_my.c

334

rxfilt = CSR_READ_4(sc, MY_TCRRCR);

sys/dev/netif/my/if_my.c

705

if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {

sys/dev/netif/my/if_my.c

710

if (!(CSR_READ_4(sc, MY_TCRRCR) &

sys/dev/netif/my/if_my.c

740

if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))

sys/dev/netif/nge/if_nge.c

1376

if (CSR_READ_4(sc, NGE_TBI_BMSR)

sys/dev/netif/nge/if_nge.c

1436

status = CSR_READ_4(sc, NGE_ISR);

sys/dev/netif/nge/if_nge.c

1500

CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)

sys/dev/netif/nge/if_nge.c

1505

status = CSR_READ_4(sc, NGE_ISR);

sys/dev/netif/nge/if_nge.c

1551

CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)

sys/dev/netif/nge/if_nge.c

1897

CSR_READ_4(sc, NGE_TBI_ANAR)

sys/dev/netif/nge/if_nge.c

1920

CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)

sys/dev/netif/nge/if_nge.c

1950

if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)

sys/dev/netif/nge/if_nge.c

1952

if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)

sys/dev/netif/nge/if_nge.c

1954

if (!(CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)) {

sys/dev/netif/nge/if_nge.c

1963

if (CSR_READ_4(sc, NGE_TBI_ANLPAR)

sys/dev/netif/nge/if_nge.c

1966

}else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)

sys/dev/netif/nge/if_nge.c

232

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/nge/if_nge.c

235

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/nge/if_nge.c

238

CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))

sys/dev/netif/nge/if_nge.c

241

CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))

sys/dev/netif/nge/if_nge.c

249

CSR_READ_4(sc, NGE_CSR);

sys/dev/netif/nge/if_nge.c

332

if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)

sys/dev/netif/nge/if_nge.c

445

ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;

sys/dev/netif/nge/if_nge.c

467

if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)

sys/dev/netif/nge/if_nge.c

569

status = CSR_READ_4(sc, NGE_TBI_ANLPAR);

sys/dev/netif/nge/if_nge.c

637

filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);

sys/dev/netif/nge/if_nge.c

674

if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)

sys/dev/netif/nge/if_nge.c

860

if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {

sys/dev/netif/nge/if_nge.c

885

CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)

sys/dev/netif/pcn/if_pcn.c

203

return(CSR_READ_4(sc, PCN_IO32_RDP));

sys/dev/netif/pcn/if_pcn.c

225

return(CSR_READ_4(sc, PCN_IO32_BDP));

sys/dev/netif/pcn/if_pcn.c

363

CSR_READ_4(sc, PCN_IO32_RESET);

sys/dev/netif/pcn/if_pcn.c

573

*(uint32_t *)eaddr = CSR_READ_4(sc, PCN_IO32_APROM00);

sys/dev/netif/pcn/if_pcn.c

919

while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) {

sys/dev/netif/re/if_re.c

2201

CSR_READ_4(sc, RE_TIMERINT); /* flush */

sys/dev/netif/re/if_re.c

2582

return CSR_READ_4(sc, RE_ISR0_8125);

sys/dev/netif/re/if_re.c

746

(CSR_READ_4(sc, RE_TXCFG) & 0xFCF00000), sc->re_type,

sys/dev/netif/re/re.c

26789

if ((CSR_READ_4(sc, 0xF8)&0x80000000)==0)

sys/dev/netif/re/re.c

30852

if (!(CSR_READ_4(sc, RE_OCPAR) & OCPAR_Flag))

sys/dev/netif/re/re.c

30871

CSR_WRITE_4(sc, 0xD0, CSR_READ_4(sc, 0xD0) & ~0x00020000);

sys/dev/netif/re/re.c

30880

if ((CSR_READ_4(sc, RE_PHYAR)&PHYAR_Flag)==0)

sys/dev/netif/re/re.c

30885

CSR_WRITE_4(sc, 0xD0, CSR_READ_4(sc, 0xD0) | 0x00020000);

sys/dev/netif/re/re.c

30904

if (!(CSR_READ_4(sc, RE_OCPAR) & OCPAR_Flag))

sys/dev/netif/re/re.c

30914

if (CSR_READ_4(sc, RE_OCPAR) & OCPAR_Flag)

sys/dev/netif/re/re.c

30918

RegData = CSR_READ_4(sc, RE_OCPDR) & OCPDR_Data_Mask;

sys/dev/netif/re/re.c

30931

CSR_WRITE_4(sc, 0xD0, CSR_READ_4(sc, 0xD0) & ~0x00020000);

sys/dev/netif/re/re.c

30939

TmpUlong = CSR_READ_4(sc, RE_PHYAR);

sys/dev/netif/re/re.c

30947

CSR_WRITE_4(sc, 0xD0, CSR_READ_4(sc, 0xD0) | 0x00020000);

sys/dev/netif/re/re.c

30965

if ((CSR_READ_4(sc, RE_EPHYAR)&PHYAR_Flag)==0)

sys/dev/netif/re/re.c

30982

TmpUlong = CSR_READ_4(sc, RE_EPHYAR);

sys/dev/netif/re/re.c

31065

temp = CSR_READ_4(sc, RE_EFUSEAR);

sys/dev/netif/re/re.c

31072

efuse_data = (u_int8_t)(CSR_READ_4(sc, RE_EFUSEAR) & EFUSE_Data_Mask);

sys/dev/netif/re/re.c

31082

temp = CSR_READ_4(sc, RE_EFUSEAR);

sys/dev/netif/re/re.c

31089

temp = CSR_READ_4(sc, RE_EFUSEAR);

sys/dev/netif/re/re.c

31108

temp = CSR_READ_4(sc, RE_EFUSEAR);

sys/dev/netif/re/re.c

31115

temp = CSR_READ_4(sc, RE_EFUSEAR);

sys/dev/netif/re/re.c

31155

WriteDone = CSR_READ_4(sc, RE_CSIAR);

sys/dev/netif/re/re.c

31185

ReadDone = CSR_READ_4(sc, RE_CSIAR);

sys/dev/netif/re/re.c

31296

TmpUlong = CSR_READ_4(sc, RE_PHYOCPACCESS);

sys/dev/netif/re/re.c

31354

TmpUlong = CSR_READ_4(sc, RE_PHYOCPACCESS);

sys/dev/netif/re/re.c

31412

TmpUlong = CSR_READ_4(sc, RE_MCUACCESS);

sys/dev/netif/re/re.c

31434

if (CSR_READ_4(sc, RE_OCPAR) & OCPAR_Flag)

sys/dev/netif/re/re.c

31443

value1 = CSR_READ_4(sc, RE_OCPDR) & mask;

sys/dev/netif/re/re.c

31506

if (!(CSR_READ_4(sc, RE_OCPAR) & OCPAR_Flag))

sys/dev/netif/re/re.c

31684

if (!(CSR_READ_4(sc, RE_ERIAR) & ERIAR_Flag))

sys/dev/netif/re/re.c

31893

if (CSR_READ_4(sc, RE_RXCFG) & RE_RXCFG_RX_9356SEL)

sys/dev/netif/re/re.c

3621

if (CSR_READ_4(sc, RE_TXCFG) & BIT_11)

sys/dev/netif/re/re.c

3682

CSR_WRITE_4(sc, RE_MCUACCESS, (0xE05E << 16) | (CSR_READ_4(sc, RE_MCUACCESS) & 0xFFFE));

sys/dev/netif/re/re.c

3965

*(u_int32_t *)&eaddr[0] = CSR_READ_4(sc, RE_BACKUP_ADDR0_8125);

sys/dev/netif/re/re.c

4006

switch(CSR_READ_4(sc, RE_TXCFG) & 0xFCF00000) {

sys/dev/netif/re/re.c

4779

sc->re_8169_MacVersion = (CSR_READ_4(sc, RE_TXCFG)&0x7c800000)>>25; /* Get bit 26~30 */

sys/dev/netif/re/re.c

4780

sc->re_8169_MacVersion |= ((CSR_READ_4(sc, RE_TXCFG)&0x00800000)!=0 ? 1:0); /* Get bit 23 */

sys/dev/netif/re/re.c

5711

macver = CSR_READ_4(sc, RE_TXCFG) & 0xFC800000;

sys/dev/netif/re/re.c

6260

CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) |BIT_7);

sys/dev/netif/re/re.c

6416

CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);

sys/dev/netif/re/re.c

6503

CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);

sys/dev/netif/re/re.c

6643

CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);

sys/dev/netif/re/re.c

6832

CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);

sys/dev/netif/re/re.c

7002

CSR_WRITE_4(sc, RE_TXCFG, CSR_READ_4(sc, RE_TXCFG) | BIT_7);

sys/dev/netif/re/re.c

7262

macver = CSR_READ_4(sc, RE_TXCFG) & 0xFC800000;

sys/dev/netif/re/re.c

7524

CSR_WRITE_4(sc, RE_RXCFG, CSR_READ_4(sc, RE_RXCFG) | (BIT_22 | BIT_23));

sys/dev/netif/re/re.c

7526

CSR_WRITE_4(sc, RE_RXCFG, CSR_READ_4(sc, RE_RXCFG) & ~(BIT_22 | BIT_23));

sys/dev/netif/re/re.c

7629

CSR_WRITE_4(sc, RE_RXCFG, CSR_READ_4(sc, RE_RXCFG)& ~0x3F);

sys/dev/netif/re/re.c

7678

while (!(CSR_READ_4(sc,RE_TXCFG) & BIT_11)) DELAY(100);

sys/dev/netif/re/re.c

7938

CSR_WRITE_4(sc, RE_RXCFG, CSR_READ_4(sc, RE_RXCFG) &

sys/dev/netif/re/re.c

8536

if ((CSR_READ_4(sc, RE_ISR0_8125) & RE_INTRS) == 0) {

sys/dev/netif/re/re.c

8659

status = CSR_READ_4(sc, RE_ISR0_8125);

sys/dev/netif/re/re.c

8686

if (CSR_READ_4(sc, RE_ISR0_8125) & RE_INTRS) {

sys/dev/netif/re/re.c

8728

rxfilt = CSR_READ_4(sc, RE_RXCFG);

sys/dev/netif/re/re.c

8748

rxfilt = CSR_READ_4(sc, RE_RXCFG);

sys/dev/netif/re/re.c

875

if (CSR_READ_4(sc,RE_ERIAR) & ERIAR_Flag)

sys/dev/netif/re/re.c

8791

rxfilt = CSR_READ_4(sc, RE_RXCFG);

sys/dev/netif/re/re.c

884

value1 = CSR_READ_4(sc,RE_ERIDR) & mask;

sys/dev/netif/re/re.c

9019

CSR_WRITE_4(sc, RE_RXCFG, CSR_READ_4(sc, RE_RXCFG) | RE_RXCFG_RX_ALLPHYS);

sys/dev/netif/re/re.c

9039

CSR_WRITE_4(sc, RE_TXCFG, (CSR_READ_4(sc, RE_TXCFG) & ~BIT_19) | BIT_25);

sys/dev/netif/re/re.c

9046

CSR_WRITE_4(sc, RE_TXCFG, (CSR_READ_4(sc, RE_TXCFG) & ~BIT_19) | RE_TXCFG_IFG);

sys/dev/netif/re/re.c

9059

CSR_WRITE_4(sc, RE_TXCFG, (CSR_READ_4(sc, RE_TXCFG) | (BIT_24 | BIT_25)) & ~BIT_19);

sys/dev/netif/re/re.c

9061

CSR_WRITE_4(sc, RE_TXCFG, (CSR_READ_4(sc, RE_TXCFG) | BIT_25) & ~(BIT_19 | BIT_24));

sys/dev/netif/re/re.c

938

if (!(CSR_READ_4(sc,RE_ERIAR) & ERIAR_Flag))

sys/dev/netif/re/re.c

9492

msr = CSR_READ_4(sc, RE_PHY_STATUS);

sys/dev/netif/rl/if_rl.c

1122

txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));

sys/dev/netif/rl/if_rl.c

1432

rxcfg = CSR_READ_4(sc, RL_RXCFG);

sys/dev/netif/rl/if_rl.c

651

rxfilt = CSR_READ_4(sc, RL_RXCFG);

sys/dev/netif/sf/if_sf.c

223

val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);

sys/dev/netif/sf/if_sf.c

225

val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));

sys/dev/netif/sis/if_sis.c

1102

if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {

sys/dev/netif/sis/if_sis.c

1530

status = CSR_READ_4(sc, SIS_ISR);

sys/dev/netif/sis/if_sis.c

1597

status = CSR_READ_4(sc, SIS_ISR);

sys/dev/netif/sis/if_sis.c

1855

if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN)

sys/dev/netif/sis/if_sis.c

205

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/sis/if_sis.c

208

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/sis/if_sis.c

211

CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)

sys/dev/netif/sis/if_sis.c

214

CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)

sys/dev/netif/sis/if_sis.c

237

CSR_READ_4(sc, SIS_CSR);

sys/dev/netif/sis/if_sis.c

320

if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)

sys/dev/netif/sis/if_sis.c

420

filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/netif/sis/if_sis.c

421

csrsave = CSR_READ_4(sc, SIS_CSR);

sys/dev/netif/sis/if_sis.c

523

ack = CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA;

sys/dev/netif/sis/if_sis.c

545

if (CSR_READ_4(sc, SIS_EECTL) & SIS_MII_DATA)

sys/dev/netif/sis/if_sis.c

628

if (!CSR_READ_4(sc, NS_BMSR))

sys/dev/netif/sis/if_sis.c

630

return CSR_READ_4(sc, NS_BMCR + (reg * 4));

sys/dev/netif/sis/if_sis.c

649

if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))

sys/dev/netif/sis/if_sis.c

658

val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;

sys/dev/netif/sis/if_sis.c

702

if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))

sys/dev/netif/sis/if_sis.c

786

filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);

sys/dev/netif/sis/if_sis.c

826

ctl = CSR_READ_4(sc, SIS_RXFILT_CTL) & SIS_RXFILTCTL_ENABLE;

sys/dev/netif/sis/if_sis.c

873

if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))

sys/dev/netif/sk/if_sk.c

2201

status = CSR_READ_4(sc, SK_ISSR);

sys/dev/netif/sk/if_sk.c

2261

status = CSR_READ_4(sc, SK_ISSR);

sys/dev/netif/sk/if_sk.c

2442

CSR_READ_4(sc_if->sk_softc, SK_CSR)));

sys/dev/netif/sk/if_sk.c

2727

CSR_READ_4(sc, SK_ISSR);

sys/dev/netif/sk/if_sk.c

2793

val = CSR_READ_4(sc, sc_if->sk_tx_bmu);

sys/dev/netif/sk/if_sk.c

309

return CSR_READ_4(sc, reg);

sys/dev/netif/ste/if_ste.c

1285

if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))

sys/dev/netif/ste/if_ste.c

169

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)

sys/dev/netif/ste/if_ste.c

172

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)

sys/dev/netif/ste/if_ste.c

418

if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))

sys/dev/netif/ste/if_ste.c

469

if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))

sys/dev/netif/stge/if_stge.c

1090

if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)

sys/dev/netif/stge/if_stge.c

1331

v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

1337

ac = CSR_READ_4(sc, STGE_AsicCtrl);

sys/dev/netif/stge/if_stge.c

1342

if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)

sys/dev/netif/stge/if_stge.c

1357

txstat = CSR_READ_4(sc, STGE_TxStatus);

sys/dev/netif/stge/if_stge.c

1379

(CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |

sys/dev/netif/stge/if_stge.c

1790

CSR_READ_4(sc,STGE_OctetRcvOk);

sys/dev/netif/stge/if_stge.c

1792

IFNET_STAT_INC(ifp, ipackets, CSR_READ_4(sc, STGE_FramesRcvdOk));

sys/dev/netif/stge/if_stge.c

1796

CSR_READ_4(sc, STGE_OctetXmtdOk);

sys/dev/netif/stge/if_stge.c

1798

IFNET_STAT_INC(ifp, opackets, CSR_READ_4(sc, STGE_FramesXmtdOk));

sys/dev/netif/stge/if_stge.c

1801

CSR_READ_4(sc, STGE_LateCollisions) +

sys/dev/netif/stge/if_stge.c

1802

CSR_READ_4(sc, STGE_MultiColFrames) +

sys/dev/netif/stge/if_stge.c

1803

CSR_READ_4(sc, STGE_SingleColFrames));

sys/dev/netif/stge/if_stge.c

1823

ac = CSR_READ_4(sc, STGE_AsicCtrl);

sys/dev/netif/stge/if_stge.c

1852

if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)

sys/dev/netif/stge/if_stge.c

1861

ac = CSR_READ_4(sc, STGE_AsicCtrl);

sys/dev/netif/stge/if_stge.c

2041

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2086

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2128

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2177

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2185

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2199

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2207

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2221

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2228

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2242

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

2249

v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;

sys/dev/netif/stge/if_stge.c

677

if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)

sys/dev/netif/ti/if_ti.c

1033

intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);

sys/dev/netif/ti/if_ti.c

1068

if ((CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS) == 0) {

sys/dev/netif/ti/if_ti.c

1072

if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {

sys/dev/netif/ti/if_ti.c

1112

if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {

sys/dev/netif/ti/if_ti.c

1121

switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {

sys/dev/netif/ti/if_ti.c

1151

cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;

sys/dev/netif/ti/if_ti.c

1159

if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {

sys/dev/netif/ti/if_ti.c

1175

CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,

sys/dev/netif/ti/if_ti.c

1773

if ((CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE) == 0)

sys/dev/netif/ti/if_ti.c

1914

prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);

sys/dev/netif/ti/if_ti.c

2136

media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);

sys/dev/netif/ti/if_ti.c

2146

media = CSR_READ_4(sc, TI_GCR_LINK_STAT);

sys/dev/netif/ti/if_ti.c

263

ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;

sys/dev/netif/ti/if_ti.c

288

CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/netif/ti/if_ti.c

297

CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/netif/ti/if_ti.c

305

CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/netif/ti/if_ti.c

316

CSR_READ_4(sc, TI_MISC_LOCAL_CTL));

sys/dev/netif/ti/if_ti.c

327

if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)

sys/dev/netif/ti/if_tireg.h

1034

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))

sys/dev/netif/ti/if_tireg.h

1036

CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))

sys/dev/netif/tl/if_tl.c

1007

cmd = CSR_READ_4(sc, TL_HOSTCMD);

sys/dev/netif/tl/if_tl.c

1548

cmd = CSR_READ_4(sc, TL_HOSTCMD);

sys/dev/netif/tl/if_tl.c

1567

(unsigned int)CSR_READ_4(sc, TL_CH_PARM));

sys/dev/netif/tl/if_tl.c

1694

*p++ = CSR_READ_4(sc, TL_DIO_DATA);

sys/dev/netif/tl/if_tl.c

1695

*p++ = CSR_READ_4(sc, TL_DIO_DATA);

sys/dev/netif/tl/if_tl.c

1696

*p++ = CSR_READ_4(sc, TL_DIO_DATA);

sys/dev/netif/tl/if_tl.c

1697

*p++ = CSR_READ_4(sc, TL_DIO_DATA);

sys/dev/netif/tl/if_tl.c

1698

*p++ = CSR_READ_4(sc, TL_DIO_DATA);

sys/dev/netif/tl/if_tl.c

1888

cmd = CSR_READ_4(sc, TL_HOSTCMD);

sys/dev/netif/tl/if_tl.c

377

return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3)));

sys/dev/netif/tl/if_tlreg.h

507

CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x))

sys/dev/netif/tl/if_tlreg.h

509

CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x))

sys/dev/netif/tx/if_tx.c

1031

if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {

sys/dev/netif/tx/if_tx.c

1107

CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));

sys/dev/netif/tx/if_tx.c

1239

status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);

sys/dev/netif/tx/if_tx.c

1249

status = CSR_READ_4(sc, INTSTAT);

sys/dev/netif/tx/if_tx.c

1320

if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)

sys/dev/netif/tx/if_tx.c

1325

if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)

sys/dev/netif/tx/if_tx.c

1551

if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;

sys/dev/netif/tx/if_tx.c

1555

return (CSR_READ_4(sc, MIIDATA));

sys/dev/netif/tx/if_tx.c

1567

if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;

sys/dev/netif/tx/if_tx.c

666

while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {

sys/dev/netif/tx/if_tx.c

678

if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)

sys/dev/netif/vge/if_vge.c

1506

status = CSR_READ_4(sc, VGE_ISR);

sys/dev/netif/vge/if_vge.c

1565

status = CSR_READ_4(sc, VGE_ISR);

sys/dev/netif/vge/if_vgevar.h

155

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/vge/if_vgevar.h

162

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/vr/if_vr.c

226

CSR_READ_4(sc, reg) | (x))

sys/dev/netif/vr/if_vr.c

230

CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/vr/if_vr.c

323

ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;

sys/dev/netif/vr/if_vr.c

345

if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)

sys/dev/netif/wb/if_wb.c

1038

if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)

sys/dev/netif/wb/if_wb.c

1130

status = CSR_READ_4(sc, WB_ISR);

sys/dev/netif/wb/if_wb.c

214

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))

sys/dev/netif/wb/if_wb.c

217

CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))

sys/dev/netif/wb/if_wb.c

220

CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) | (x))

sys/dev/netif/wb/if_wb.c

223

CSR_WRITE_4(sc, WB_SIO, CSR_READ_4(sc, WB_SIO) & ~(x))

sys/dev/netif/wb/if_wb.c

276

if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)

sys/dev/netif/wb/if_wb.c

390

ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;

sys/dev/netif/wb/if_wb.c

416

if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)

sys/dev/netif/wb/if_wb.c

538

rxfilt = CSR_READ_4(sc, WB_NETCFG);

sys/dev/netif/wb/if_wb.c

585

if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON | WB_NETCFG_RX_ON)) {

sys/dev/netif/wb/if_wb.c

591

if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&

sys/dev/netif/wb/if_wb.c

592

(CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))

sys/dev/netif/wb/if_wb.c

632

if ((CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET) == 0)

sys/dev/netif/xl/if_xl.c

2054

if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||

sys/dev/netif/xl/if_xl.c

2055

CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {

sys/dev/netif/xl/if_xl.c

2094

if (CSR_READ_4(sc, XL_DOWNLIST_PTR))

sys/dev/netif/xl/if_xl.c

2111

if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||

sys/dev/netif/xl/if_xl.c

2112

!CSR_READ_4(sc, XL_DOWNLIST_PTR)) {

sys/dev/netif/xl/if_xl.c

2588

if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))

sys/dev/netif/xl/if_xl.c

2980

icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;

sys/dev/netif/xl/if_xl.c

821

icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);

sys/dev/netif/xl/if_xl.c

847

icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);

sys/dev/powermng/memtemp/memtemp_core.c

191

dimm_ch = CSR_READ_4(sc, dimm_ch_reg);

sys/dev/powermng/memtemp/memtemp_core.c

266

val = CSR_READ_4(dimm_sc->dimm_parent, dimm_sc->dimm_reg);

sys/dev/video/cxm/cxm.c

1346

status = CSR_READ_4(sc, CXM_REG_DMA_STATUS) & 0x0000000f;

sys/dev/video/cxm/cxm.c

1405

= CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

2032

status = CSR_READ_4(sc, CXM_REG_IRQ_STATUS);

sys/dev/video/cxm/cxm.c

354

flags = CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

368

= CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

399

CSR_READ_4(sc, mailbox + offsetof(struct cxm_mailbox, flags));

sys/dev/video/cxm/cxm.c

468

flags = CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

483

result = CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

489

= CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

529

flags = CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

544

result = CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

550

= CSR_READ_4(sc,

sys/dev/video/cxm/cxm.c

595

CSR_READ_4(sc, CXM_REG_IRQ_MASK);

sys/dev/video/cxm/cxm.c

615

CSR_READ_4(sc, CXM_REG_IRQ_STATUS);

sys/dev/video/cxm/cxm.c

730

CSR_READ_4(sc, CXM_REG_SPU) & CXM_MASK_SPU_ENABLE);

sys/dev/video/cxm/cxm.c

737

CSR_READ_4(sc, CXM_REG_VPU)

sys/dev/video/cxm/cxm.c

748

if (CSR_READ_4(sc, mailbox + i) == 0x12345678

sys/dev/video/cxm/cxm.c

749

&& CSR_READ_4(sc, mailbox + i + 4) == 0x34567812

sys/dev/video/cxm/cxm.c

750

&& CSR_READ_4(sc, mailbox + i + 8) == 0x56781234

sys/dev/video/cxm/cxm.c

751

&& CSR_READ_4(sc, mailbox + i + 12) == 0x78123456)

sys/dev/video/cxm/cxm.c

763

if (CSR_READ_4(sc, mailbox + i) == 0x12345678

sys/dev/video/cxm/cxm.c

764

&& CSR_READ_4(sc, mailbox + i + 4) == 0x34567812

sys/dev/video/cxm/cxm.c

765

&& CSR_READ_4(sc, mailbox + i + 8) == 0x56781234

sys/dev/video/cxm/cxm.c

766

&& CSR_READ_4(sc, mailbox + i + 12) == 0x78123456)

sys/dev/video/cxm/cxm_i2c.c

292

CSR_READ_4(sc, CXM_REG_I2C_SETSDA);

sys/dev/video/cxm/cxm_i2c.c

344

CSR_READ_4(sc, CXM_REG_I2C_SETSCL);

sys/dev/video/cxm/cxm_i2c.c

365

CSR_READ_4(sc, CXM_REG_I2C_SETSDA);