CSR_READ_2
linkcfg = CSR_READ_2(sc, sc->alc_expcap +
cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP);
ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL);
burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL);
prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX);
CSR_READ_2(sc, ALC_GPHY_CFG);
CSR_READ_2(sc, ALC_GPHY_CFG);
prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
idx = CSR_READ_2(sc_if->msk_softc, ridx);
idx = CSR_READ_2(sc, STAT_PUT_IDX);
return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
CSR_READ_2((sc_if)->msk_softc, (reg))
CSR_READ_2((sc), GMAC_REG((port), (reg)))
data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
return(CSR_READ_2(sc, PCN_IO16_RDP));
return(CSR_READ_2(sc, PCN_IO16_BDP));
CSR_READ_2(sc, PCN_IO16_RESET);
*(uint16_t *)(eaddr + 4) = CSR_READ_2(sc, PCN_IO32_APROM01);
return CSR_READ_2(sc, RE_ISR);
if ((CSR_READ_2(sc, RE_IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == (BIT_0 | BIT_1 | BIT_8))
if (CSR_READ_2(sc, 0xD2) & BIT_9)
if (CSR_READ_2(sc, 0xD2) & BIT_9)
if (CSR_READ_2(sc, 0xD2) & BIT_9)
if (CSR_READ_2(sc, 0xD2) & BIT_9)
if (CSR_READ_2(sc, 0xD2) & BIT_9)
if (CSR_READ_2(sc, 0xD2) & BIT_9)
*(u_int16_t *)&eaddr[4] = CSR_READ_2(sc, RE_BACKUP_ADDR4_8125);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) & ~RL_RxChkSum);
CSR_WRITE_2 (sc, RE_CPlusCmd,CSR_READ_2(sc, RE_CPlusCmd) |RL_RxChkSum);
CSR_WRITE_2(sc, 0xE0, CSR_READ_2(sc, 0xE0) & ~0xDF9C);
CSR_WRITE_2(sc, 0xE0, CSR_READ_2(sc, 0xE0) & ~0xDF9C);
CSR_WRITE_2(sc, 0xE0, CSR_READ_2(sc, 0xE0) & ~0xDF9C);
data16 = CSR_READ_2(sc, RE_CPlusCmd);
CSR_WRITE_2(sc, 0x1880, CSR_READ_2(sc, 0x1880) & ~(BIT_4 | BIT_5));
data16 = CSR_READ_2(sc, RE_CPlusCmd);
if ((CSR_READ_2(sc, RE_ISR) & RE_INTRS) == 0) {
status = CSR_READ_2(sc, RE_ISR);
if (CSR_READ_2(sc, RE_ISR) & RE_INTRS) {
limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
status = CSR_READ_2(sc, RL_ISR);
status = CSR_READ_2(sc, RL_ISR);
ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
rval = CSR_READ_2(sc, rl8139_reg);
cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) %
((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
CSR_READ_2(sc, SK_LINK_CTRL)));
return CSR_READ_2(sc, reg);
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
word = CSR_READ_2(sc, STE_EEPROM_DATA);
if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
status = CSR_READ_2(sc, STE_ISR_ACK);
status = CSR_READ_2(sc, STGE_IntStatus);
status = CSR_READ_2(sc, STGE_IntStatusAck);
status = CSR_READ_2(sc, STGE_IntStatus);
IFNET_STAT_INC(ifp, ierrors, CSR_READ_2(sc, STGE_FramesLostRxErrors));
CSR_READ_2(sc, STGE_FramesAbortXSColls) +
CSR_READ_2(sc, STGE_FramesWEXDeferal));
CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
mode = CSR_READ_2(sc, STGE_ReceiveMode);
mode = CSR_READ_2(sc, STGE_ReceiveMode);
if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
*data = CSR_READ_2(sc, STGE_EepromData);
v = CSR_READ_2(sc, STGE_StationAddress0);
v = CSR_READ_2(sc, STGE_StationAddress1);
v = CSR_READ_2(sc, STGE_StationAddress2);
ints = CSR_READ_2(sc, TL_HOST_INT);
return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)));
f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3));
word = CSR_READ_2(sc, VGE_EERDDAT);
rval = CSR_READ_2(sc, VGE_MIIDATA);
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
status = CSR_READ_2(sc, VR_ISR);
CSR_READ_2(sc, reg) | (x))
CSR_READ_2(sc, reg) & ~(x))
frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
fid = CSR_READ_2(sc, WI_RX_FID);
fid = CSR_READ_2(sc, WI_TX_CMP_FID);
fid = CSR_READ_2(sc, WI_ALLOC_FID);
fid = CSR_READ_2(sc, WI_INFO_FID);
if (!(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
s = CSR_READ_2(sc, WI_EVENT_STAT);
s = CSR_READ_2(sc, WI_STATUS);
status = CSR_READ_2(sc, WI_OFF0);
if (CSR_READ_2(sc, WI_EVENT_STAT) & WI_EV_ALLOC)
*idp = CSR_READ_2(sc, WI_ALLOC_FID);
status = CSR_READ_2(sc, WI_EVENT_STAT);
(CSR_READ_2(sc, WI_COMMAND) & WI_CMD_BUSY))
reg = CSR_READ_2(sc, WI_HFA384X_SWSUPPORT0_OFF);
sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
status = CSR_READ_2(sc, XL_STATUS);
while(((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS) &&
status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
word = CSR_READ_2(sc, XL_W0_EE_DATA);
mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,