sys/dev/drm/amd/display/dc/core/dc.c

1429

dc->hwss.set_drr(&pipe_ctx, 1,

sys/dev/drm/amd/display/dc/core/dc.c

206

dc->hwss.set_drr(&pipe,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1339

if (pipe_ctx->stream_res.tg->funcs->set_drr)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1340

pipe_ctx->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1720

pipe_ctx[i]->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2902

.set_drr = set_drr,

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

2228

.set_drr =

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1171

.set_drr = dce120_timing_generator_set_drr,

sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c

206

.set_drr = dce110_timing_generator_set_drr,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2460

pipe_ctx[i]->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2741

.set_drr = set_drr,

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

712

if (pipe_ctx->stream_res.tg->funcs->set_drr)

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

713

pipe_ctx->stream_res.tg->funcs->set_drr(

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c

1401

.set_drr = optc1_set_drr,

sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h

190

void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

185

void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes,