sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

476

void pp_rv_set_display_requirement(struct pp_smu *pp,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

498

void pp_rv_set_wm_ranges(struct pp_smu *pp,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

552

void pp_rv_set_pme_wa_enable(struct pp_smu *pp)

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

569

funcs->pp_smu.dm = ctx;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1401

struct pp_smu_funcs_rv *pp = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/calcs/dcn_calcs.c

1459

pp->set_wm_ranges(&pp->pp_smu, &ranges);

sys/dev/drm/amd/display/dc/core/dc.c

1386

struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/core/dc.c

1393

if (!pp_smu || !pp_smu->set_display_count)

sys/dev/drm/amd/display/dc/core/dc.c

1407

pp_smu->set_display_count(&pp_smu->pp_smu, display_count);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

579

struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

634

if (pp_smu->set_display_requirement)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

635

pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

653

if (pp_smu->set_display_requirement)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

654

pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1006

if (num_audio >= 1 && pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1008

pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1023

struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1044

if (pp_smu != NULL && pp_smu->set_pme_wa_enable != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1046

pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

994

struct pp_smu_funcs_rv *pp_smu = core_dc->res_pool->pp_smu;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1350

pool->base.pp_smu = dcn10_pp_smu_create(ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

860

struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

862

if (!pp_smu)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

863

return pp_smu;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

865

dm_pp_get_funcs_rv(ctx, pp_smu);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

866

return pp_smu;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

960

kfree(pool->base.pp_smu);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

103

void (*set_display_count)(struct pp_smu *pp, int count);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

106

void (*set_wm_ranges)(struct pp_smu *pp,

sys/dev/drm/amd/display/dc/dm_pp_smu.h

112

void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int khz);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

118

void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

123

void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

128

void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int khz);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

131

void (*set_pme_wa_enable)(struct pp_smu *pp);

sys/dev/drm/amd/display/dc/dm_pp_smu.h

137

void (*set_display_requirement)(struct pp_smu *pp,

sys/dev/drm/amd/display/dc/dm_pp_smu.h

142

struct pp_smu ctx;

sys/dev/drm/amd/display/dc/dm_pp_smu.h

98

struct pp_smu pp_smu;

sys/dev/drm/amd/display/dc/inc/core_types.h

147

struct pp_smu_funcs_rv *pp_smu;