sys/dev/drm/amd/display/dc/core/dc_link_hwss.c

83

&pipes[i].pll_settings);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

191

struct pll_settings *pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

204

pll_settings->adjusted_pix_clk,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

223

pll_settings->adjusted_pix_clk)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

225

pll_settings->adjusted_pix_clk

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

226

: pll_settings->adjusted_pix_clk -

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

231

pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

232

pll_settings->reference_divider = ref_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

233

pll_settings->feedback_divider = feedback_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

234

pll_settings->fract_feedback_divider = fract_feedback_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

235

pll_settings->pix_clk_post_divider = post_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

236

pll_settings->calculated_pix_clk =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

238

pll_settings->vco_freq =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

247

struct pll_settings *pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

260

tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

275

pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

289

struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

297

if (pll_settings->adjusted_pix_clk == 0) {

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

304

if (pll_settings->pix_clk_post_divider) {

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

305

min_post_divider = pll_settings->pix_clk_post_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

306

max_post_divider = pll_settings->pix_clk_post_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

309

if (min_post_divider * pll_settings->adjusted_pix_clk <

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

312

pll_settings->adjusted_pix_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

314

pll_settings->adjusted_pix_clk) <

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

320

if (max_post_divider * pll_settings->adjusted_pix_clk

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

323

pll_settings->adjusted_pix_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

332

if (pll_settings->reference_divider) {

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

333

min_ref_divider = pll_settings->reference_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

334

max_ref_divider = pll_settings->reference_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

377

pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

393

struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

444

pll_settings->actual_pix_clk = actual_pix_clk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

445

pll_settings->adjusted_pix_clk =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

447

pll_settings->reference_divider =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

449

pll_settings->pix_clk_post_divider =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

471

struct pll_settings *pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

482

pll_settings->use_external_clk = (field > 1);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

493

pll_settings->adjusted_pix_clk);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

496

pll_settings->ss_percentage = ss_data->percentage;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

500

if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

505

pll_settings->actual_pix_clk =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

507

pll_settings->adjusted_pix_clk =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

511

pll_settings->adjusted_pix_clk = 100000;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

520

pll_settings);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

526

pll_settings);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

533

struct pll_settings *pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

555

pll_settings->actual_pix_clk = actualPixelClockInKHz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

556

pll_settings->adjusted_pix_clk = actualPixelClockInKHz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

557

pll_settings->calculated_pix_clk = pix_clk_params->requested_pix_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

563

struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

569

if (pix_clk_params == NULL || pll_settings == NULL

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

576

memset(pll_settings, 0, sizeof(*pll_settings));

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

580

pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

581

pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

582

pll_settings->actual_pix_clk =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

588

pll_settings, pix_clk_params);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

596

struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

601

if (pix_clk_params == NULL || pll_settings == NULL

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

608

memset(pll_settings, 0, sizeof(*pll_settings));

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

612

pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

613

pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

614

pll_settings->actual_pix_clk =

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

620

pll_settings, pix_clk_params);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

642

const struct pll_settings *pll_settings,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

659

if (pll_settings == NULL)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

667

pll_settings->fract_feedback_divider, 1000000);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

668

fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

690

pll_settings->reference_freq * 1000,

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

691

pll_settings->reference_divider * ss_data->modulation_freq_hz);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

708

enum signal_type signal, struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

717

pll_settings->calculated_pix_clk);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

722

if (ss_data != NULL && pll_settings->ss_percentage != 0) {

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

723

if (calculate_ss(pll_settings, ss_data, &d_s_data)) {

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

839

struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

856

bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

860

bp_pc_params.reference_divider = pll_settings->reference_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

861

bp_pc_params.feedback_divider = pll_settings->feedback_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

863

pll_settings->fract_feedback_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

865

pll_settings->pix_clk_post_divider;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

867

pll_settings->use_external_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

883

pll_settings))

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

898

struct pll_settings *pll_settings)

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

907

unsigned clock_kHz = pll_settings->actual_pix_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

930

bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

936

pll_settings->use_external_clk;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

938

!pll_settings->use_external_clk;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1208

pipe_ctx->pll_settings.feedback_divider;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1218

pipe_ctx->pll_settings.ss_percentage;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1327

&pipe_ctx->pll_settings)) {

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

817

&pipe_ctx->pll_settings);

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

661

&pipe_ctx->pll_settings)) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1021

&pipe_ctx->pll_settings);

sys/dev/drm/amd/display/dc/inc/clock_source.h

164

struct pixel_clk_params *, struct pll_settings *);

sys/dev/drm/amd/display/dc/inc/clock_source.h

168

struct pll_settings *);

sys/dev/drm/amd/display/dc/inc/core_types.h

224

struct pll_settings pll_settings;