games/boggle/boggle/bog.c

498

int prevch, previndex, *pi, *qi, st;

games/boggle/boggle/bog.c

541

pi = wordpath;

games/boggle/boggle/bog.c

542

while (pi < qi && *pi != -1)

games/boggle/boggle/bog.c

543

*pi++ = -1;

include/printf.h

115

int __printf_out(struct __printf_io *io, const struct printf_info *pi, const void *ptr, int len);

lib/libc/stdio/xprintf.c

157

__printf_out(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf.c

162

if ((!pi->left) && pi->width > len)

lib/libc/stdio/xprintf.c

163

ret += __printf_pad(io, pi->width - len, pi->pad == '0');

lib/libc/stdio/xprintf.c

165

if (pi->left && pi->width > len)

lib/libc/stdio/xprintf.c

166

ret += __printf_pad(io, pi->width - len, pi->pad == '0');

lib/libc/stdio/xprintf.c

174

__printf_arginfo_pct(const struct printf_info *pi __unused, size_t n __unused,

lib/libc/stdio/xprintf.c

183

const struct printf_info *pi __unused,

lib/libc/stdio/xprintf.c

193

__printf_arginfo_n(const struct printf_info *pi __unused, size_t n, int *argt)

lib/libc/stdio/xprintf.c

207

__printf_render_n(FILE *io __unused, const struct printf_info *pi,

lib/libc/stdio/xprintf.c

211

if (pi->is_char)

lib/libc/stdio/xprintf.c

212

**((signed char **)arg[0]) = (signed char)pi->sofar;

lib/libc/stdio/xprintf.c

213

else if (pi->is_short)

lib/libc/stdio/xprintf.c

214

**((short **)arg[0]) = (short)pi->sofar;

lib/libc/stdio/xprintf.c

215

else if (pi->is_long)

lib/libc/stdio/xprintf.c

216

**((long **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

217

else if (pi->is_long_double)

lib/libc/stdio/xprintf.c

218

**((long long **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

219

else if (pi->is_intmax)

lib/libc/stdio/xprintf.c

220

**((intmax_t **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

221

else if (pi->is_ptrdiff)

lib/libc/stdio/xprintf.c

222

**((ptrdiff_t **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

223

else if (pi->is_quad)

lib/libc/stdio/xprintf.c

224

**((quad_t **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

225

else if (pi->is_size)

lib/libc/stdio/xprintf.c

226

**((size_t **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

228

**((int **)arg[0]) = pi->sofar;

lib/libc/stdio/xprintf.c

269

struct printf_info *pi, *pil;

lib/libc/stdio/xprintf.c

288

for (pi = pia; ; pi++) {

lib/libc/stdio/xprintf.c

289

memset(pi, 0, sizeof *pi);

lib/libc/stdio/xprintf.c

290

pil = pi;

lib/libc/stdio/xprintf.c

293

pil = pi + 1;

lib/libc/stdio/xprintf.c

294

pi->prec = -1;

lib/libc/stdio/xprintf.c

295

pi->pad = ' ';

lib/libc/stdio/xprintf.c

296

pi->begin = pi->end = fmt;

lib/libc/stdio/xprintf.c

298

pi->end = ++fmt;

lib/libc/stdio/xprintf.c

303

pi->spec = *fmt;

lib/libc/stdio/xprintf.c

304

switch (pi->spec) {

lib/libc/stdio/xprintf.c

311

if (pi->showsign == 0)

lib/libc/stdio/xprintf.c

312

pi->showsign = ' ';

lib/libc/stdio/xprintf.c

316

pi->alt = 1;

lib/libc/stdio/xprintf.c

320

pi->prec = 0;

lib/libc/stdio/xprintf.c

324

pi->get_prec = nextarg;

lib/libc/stdio/xprintf.c

329

pi->prec *= 10;

lib/libc/stdio/xprintf.c

330

pi->prec += to_digit(*fmt);

lib/libc/stdio/xprintf.c

335

pi->left = 1;

lib/libc/stdio/xprintf.c

339

pi->showsign = '+';

lib/libc/stdio/xprintf.c

344

pi->get_width = nextarg;

lib/libc/stdio/xprintf.c

351

pi->group = 1;

lib/libc/stdio/xprintf.c

360

pi->pad = '0';

lib/libc/stdio/xprintf.c

378

pi->width = n;

lib/libc/stdio/xprintf.c

384

pi->spec += ('a' - 'A');

lib/libc/stdio/xprintf.c

385

pi->is_intmax = 0;

lib/libc/stdio/xprintf.c

386

if (pi->is_long_double || pi->is_quad) {

lib/libc/stdio/xprintf.c

387

pi->is_long = 0;

lib/libc/stdio/xprintf.c

388

pi->is_long_double = 1;

lib/libc/stdio/xprintf.c

390

pi->is_long = 1;

lib/libc/stdio/xprintf.c

391

pi->is_long_double = 0;

lib/libc/stdio/xprintf.c

396

pi->is_intmax = 1;

lib/libc/stdio/xprintf.c

400

pi->is_long = 0;

lib/libc/stdio/xprintf.c

401

pi->is_quad = 1;

lib/libc/stdio/xprintf.c

405

pi->is_long_double = 1;

lib/libc/stdio/xprintf.c

412

pi->is_char = 1;

lib/libc/stdio/xprintf.c

414

pi->is_short = 1;

lib/libc/stdio/xprintf.c

421

pi->is_long_double = 1;

lib/libc/stdio/xprintf.c

422

pi->is_quad = 0;

lib/libc/stdio/xprintf.c

424

pi->is_quad = 0;

lib/libc/stdio/xprintf.c

425

pi->is_long = 1;

lib/libc/stdio/xprintf.c

429

pi->is_ptrdiff = 1;

lib/libc/stdio/xprintf.c

433

pi->is_size = 1;

lib/libc/stdio/xprintf.c

440

if (printf_tbl[pi->spec].arginfo == NULL)

lib/libc/stdio/xprintf.c

441

errx(1, "arginfo[%c] = NULL", pi->spec);

lib/libc/stdio/xprintf.c

442

ch = printf_tbl[pi->spec].arginfo(

lib/libc/stdio/xprintf.c

443

pi, __PRINTFMAXARG, &argt[nextarg]);

lib/libc/stdio/xprintf.c

445

pi->arg[0] = &args[nextarg];

lib/libc/stdio/xprintf.c

447

pi->arg[1] = &args[nextarg + 1];

lib/libc/stdio/xprintf.c

517

for (pi = pia; pi < pil; pi++) {

lib/libc/stdio/xprintf.c

519

fprintf(stderr, "pi %p", pi);

lib/libc/stdio/xprintf.c

520

fprintf(stderr, " spec '%c'", pi->spec);

lib/libc/stdio/xprintf.c

522

((uintptr_t)pi->arg[0] - (uintptr_t)args) / sizeof args[0]);

lib/libc/stdio/xprintf.c

523

if (pi->width) fprintf(stderr, " width %d", pi->width);

lib/libc/stdio/xprintf.c

524

if (pi->pad) fprintf(stderr, " pad 0x%x", pi->pad);

lib/libc/stdio/xprintf.c

525

if (pi->left) fprintf(stderr, " left");

lib/libc/stdio/xprintf.c

526

if (pi->showsign) fprintf(stderr, " showsign");

lib/libc/stdio/xprintf.c

527

if (pi->prec != -1) fprintf(stderr, " prec %d", pi->prec);

lib/libc/stdio/xprintf.c

528

if (pi->is_char) fprintf(stderr, " char");

lib/libc/stdio/xprintf.c

529

if (pi->is_short) fprintf(stderr, " short");

lib/libc/stdio/xprintf.c

530

if (pi->is_long) fprintf(stderr, " long");

lib/libc/stdio/xprintf.c

531

if (pi->is_long_double) fprintf(stderr, " long_double");

lib/libc/stdio/xprintf.c

533

fprintf(stderr, "\t\"%.*s\"\n", pi->end - pi->begin, pi->begin);

lib/libc/stdio/xprintf.c

535

if (pi->get_width) {

lib/libc/stdio/xprintf.c

536

pi->width = args[pi->get_width].intarg;

lib/libc/stdio/xprintf.c

543

if (pi->width < 0) {

lib/libc/stdio/xprintf.c

544

pi->left = 1;

lib/libc/stdio/xprintf.c

545

pi->width = -pi->width;

lib/libc/stdio/xprintf.c

548

if (pi->get_prec)

lib/libc/stdio/xprintf.c

549

pi->prec = args[pi->get_prec].intarg;

lib/libc/stdio/xprintf.c

550

ret += __printf_puts(&io, pi->begin, pi->end - pi->begin);

lib/libc/stdio/xprintf.c

551

if (printf_tbl[pi->spec].gnurender != NULL) {

lib/libc/stdio/xprintf.c

553

pi->sofar = ret;

lib/libc/stdio/xprintf.c

554

ret += printf_tbl[pi->spec].gnurender(

lib/libc/stdio/xprintf.c

555

fp, pi, (const void *)pi->arg);

lib/libc/stdio/xprintf.c

556

} else if (printf_tbl[pi->spec].render != NULL) {

lib/libc/stdio/xprintf.c

557

pi->sofar = ret;

lib/libc/stdio/xprintf.c

558

n = printf_tbl[pi->spec].render(

lib/libc/stdio/xprintf.c

559

&io, pi, (const void *)pi->arg);

lib/libc/stdio/xprintf.c

564

} else if (pi->begin == pi->end)

lib/libc/stdio/xprintf_errno.c

42

__printf_arginfo_errno(const struct printf_info *pi __unused, size_t n,

lib/libc/stdio/xprintf_errno.c

53

const struct printf_info *pi __unused,

lib/libc/stdio/xprintf_errno.c

64

return (__printf_out(io, pi, p, strlen(p)));

lib/libc/stdio/xprintf_errno.c

67

ret += __printf_out(io, pi, buf, strlen(buf));

lib/libc/stdio/xprintf_float.c

122

__printf_arginfo_float(const struct printf_info *pi, size_t n, int *argt)

lib/libc/stdio/xprintf_float.c

126

if (pi->is_long_double)

lib/libc/stdio/xprintf_float.c

147

__printf_render_float(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_float.c

179

prec = pi->prec;

lib/libc/stdio/xprintf_float.c

181

sign = pi->showsign;

lib/libc/stdio/xprintf_float.c

187

if (pi->alt)

lib/libc/stdio/xprintf_float.c

192

switch(pi->spec) {

lib/libc/stdio/xprintf_float.c

195

if (pi->spec == 'a') {

lib/libc/stdio/xprintf_float.c

206

if (pi->is_long_double) {

lib/libc/stdio/xprintf_float.c

224

expchar = pi->spec;

lib/libc/stdio/xprintf_float.c

236

expchar = pi->spec - ('g' - 'e');

lib/libc/stdio/xprintf_float.c

241

assert(pi->spec == 'f');

lib/libc/stdio/xprintf_float.c

246

if (pi->is_long_double) {

lib/libc/stdio/xprintf_float.c

264

cp = (pi->spec >= 'a') ? "nan" : "NAN";

lib/libc/stdio/xprintf_float.c

267

cp = (pi->spec >= 'a') ? "inf" : "INF";

lib/libc/stdio/xprintf_float.c

274

if (pi->spec == 'g' || pi->spec == 'G') {

lib/libc/stdio/xprintf_float.c

278

if (pi->alt)

lib/libc/stdio/xprintf_float.c

289

if (!pi->alt)

lib/libc/stdio/xprintf_float.c

296

if (prec > 1 || pi->alt)

lib/libc/stdio/xprintf_float.c

305

if (prec || pi->alt)

lib/libc/stdio/xprintf_float.c

350

if (pi->pad != '0' && pi->left == 0)

lib/libc/stdio/xprintf_float.c

351

ret += __printf_pad(io, pi->width - realsz, 0);

lib/libc/stdio/xprintf_float.c

363

if (pi->pad == '0' && pi->left == 0)

lib/libc/stdio/xprintf_float.c

364

ret += __printf_pad(io, pi->width - realsz, 1);

lib/libc/stdio/xprintf_float.c

376

if (prec || pi->alt)

lib/libc/stdio/xprintf_float.c

400

if (prec || pi->alt)

lib/libc/stdio/xprintf_float.c

405

if (prec > 1 || pi->alt) {

lib/libc/stdio/xprintf_float.c

418

if (pi->left)

lib/libc/stdio/xprintf_float.c

419

ret += __printf_pad(io, pi->width - realsz, 0);

lib/libc/stdio/xprintf_hexdump.c

39

__printf_arginfo_hexdump(const struct printf_info *pi __unused,

lib/libc/stdio/xprintf_hexdump.c

50

__printf_render_hexdump(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_hexdump.c

58

if (pi->width > 0 && pi->width < 16)

lib/libc/stdio/xprintf_hexdump.c

59

l = pi->width;

lib/libc/stdio/xprintf_hexdump.c

69

if (pi->showsign)

lib/libc/stdio/xprintf_hexdump.c

73

if (pi->alt) {

lib/libc/stdio/xprintf_int.c

233

__printf_arginfo_int(const struct printf_info *pi, size_t n, int *argt)

lib/libc/stdio/xprintf_int.c

237

if (pi->is_ptrdiff)

lib/libc/stdio/xprintf_int.c

239

else if (pi->is_size)

lib/libc/stdio/xprintf_int.c

241

else if (pi->is_long)

lib/libc/stdio/xprintf_int.c

243

else if (pi->is_intmax)

lib/libc/stdio/xprintf_int.c

245

else if (pi->is_quad)

lib/libc/stdio/xprintf_int.c

247

else if (pi->is_long_double)

lib/libc/stdio/xprintf_int.c

249

else if (pi->is_short)

lib/libc/stdio/xprintf_int.c

251

else if (pi->is_char)

lib/libc/stdio/xprintf_int.c

257

__printf_render_int(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_int.c

277

if (pi->group) {

lib/libc/stdio/xprintf_int.c

287

switch(pi->spec) {

lib/libc/stdio/xprintf_int.c

311

fprintf(stderr, "pi->spec = '%c'\n", pi->spec);

lib/libc/stdio/xprintf_int.c

317

ns = pi->showsign;

lib/libc/stdio/xprintf_int.c

319

if (pi->is_long_double || pi->is_quad || pi->is_intmax ||

lib/libc/stdio/xprintf_int.c

320

pi->is_size || pi->is_ptrdiff) {

lib/libc/stdio/xprintf_int.c

327

} else if (pi->is_long) {

lib/libc/stdio/xprintf_int.c

334

} else if (pi->is_short) {

lib/libc/stdio/xprintf_int.c

341

} else if (pi->is_char) {

lib/libc/stdio/xprintf_int.c

372

if (pi->prec == 0 && !(pi->alt && rdx == 8))

lib/libc/stdio/xprintf_int.c

374

} else if (pi->alt) {

lib/libc/stdio/xprintf_int.c

378

if (pi->spec == 'x')

lib/libc/stdio/xprintf_int.c

394

if (pi->prec > (pe - p))

lib/libc/stdio/xprintf_int.c

395

zext = pi->prec - (pe - p);

lib/libc/stdio/xprintf_int.c

396

else if (pi->prec != -1)

lib/libc/stdio/xprintf_int.c

398

else if (pi->pad == '0' && pi->width > l && !pi->left)

lib/libc/stdio/xprintf_int.c

399

zext = pi->width - l;

lib/libc/stdio/xprintf_int.c

417

if (pi->width > (pe - p) && !pi->left) {

lib/libc/stdio/xprintf_int.c

418

l = pi->width - (pe - p);

lib/libc/stdio/xprintf_int.c

427

if (!pi->left && pi->width > l)

lib/libc/stdio/xprintf_int.c

428

ret += __printf_pad(io, pi->width - l, 0);

lib/libc/stdio/xprintf_int.c

438

if (pi->width > ret && pi->left)

lib/libc/stdio/xprintf_int.c

439

ret += __printf_pad(io, pi->width - ret, 0);

lib/libc/stdio/xprintf_int.c

447

__printf_arginfo_ptr(const struct printf_info *pi __unused, size_t n, int *argt)

lib/libc/stdio/xprintf_int.c

456

__printf_render_ptr(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_int.c

471

p2 = *pi;

lib/libc/stdio/xprintf_quote.c

100

ret += __printf_out(io, pi, "\"", 1);

lib/libc/stdio/xprintf_quote.c

42

__printf_arginfo_quote(const struct printf_info *pi __unused, size_t n,

lib/libc/stdio/xprintf_quote.c

53

const struct printf_info *pi __unused,

lib/libc/stdio/xprintf_quote.c

62

return (__printf_out(io, pi, "\"(null)\"", 8));

lib/libc/stdio/xprintf_quote.c

64

return (__printf_out(io, pi, "\"\"", 2));

lib/libc/stdio/xprintf_quote.c

70

return (__printf_out(io, pi, str, strlen(str)));

lib/libc/stdio/xprintf_quote.c

72

ret = __printf_out(io, pi, "\"", 1);

lib/libc/stdio/xprintf_quote.c

94

ret += __printf_out(io, pi, t, p - t);

lib/libc/stdio/xprintf_quote.c

95

ret += __printf_out(io, pi, o, strlen(o));

lib/libc/stdio/xprintf_quote.c

99

ret += __printf_out(io, pi, t, p - t);

lib/libc/stdio/xprintf_str.c

110

__printf_arginfo_str(const struct printf_info *pi, size_t n, int *argt)

lib/libc/stdio/xprintf_str.c

114

if (pi->is_long || pi->spec == 'C')

lib/libc/stdio/xprintf_str.c

122

__printf_render_str(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_str.c

130

if (pi->is_long || pi->spec == 'S') {

lib/libc/stdio/xprintf_str.c

133

return (__printf_out(io, pi, "(null)", 6));

lib/libc/stdio/xprintf_str.c

134

convbuf = __wcsconv(wcp, pi->prec);

lib/libc/stdio/xprintf_str.c

137

l = __printf_out(io, pi, convbuf, strlen(convbuf));

lib/libc/stdio/xprintf_str.c

143

return (__printf_out(io, pi, "(null)", 6));

lib/libc/stdio/xprintf_str.c

145

if (pi->prec >= 0 && pi->prec < l)

lib/libc/stdio/xprintf_str.c

146

l = pi->prec;

lib/libc/stdio/xprintf_str.c

147

return (__printf_out(io, pi, p, l));

lib/libc/stdio/xprintf_str.c

153

__printf_arginfo_chr(const struct printf_info *pi, size_t n, int *argt)

lib/libc/stdio/xprintf_str.c

157

if (pi->is_long || pi->spec == 'C')

lib/libc/stdio/xprintf_str.c

165

__printf_render_chr(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_str.c

176

if (pi->is_long || pi->spec == 'C') {

lib/libc/stdio/xprintf_str.c

183

return (__printf_out(io, pi, buf, mbseqlen));

lib/libc/stdio/xprintf_str.c

187

i = __printf_out(io, pi, &c, 1);

lib/libc/stdio/xprintf_time.c

111

if (pi->is_long || pi->is_long_double) {

lib/libc/stdio/xprintf_time.c

112

if (pi->prec >= 0)

lib/libc/stdio/xprintf_time.c

113

prec = pi->prec;

lib/libc/stdio/xprintf_time.c

118

return(__printf_out(io, pi, buf, p - buf));

lib/libc/stdio/xprintf_time.c

46

__printf_arginfo_time(const struct printf_info *pi __unused, size_t n,

lib/libc/stdio/xprintf_time.c

60

__printf_render_time(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_time.c

72

if (pi->is_long) {

lib/libc/stdio/xprintf_time.c

77

} else if (pi->is_long_double) {

lib/libc/stdio/xprintf_time.c

88

if (pi->alt) {

lib/libc/stdio/xprintf_vis.c

41

__printf_arginfo_vis(const struct printf_info *pi __unused, size_t n,

lib/libc/stdio/xprintf_vis.c

51

__printf_render_vis(struct __printf_io *io, const struct printf_info *pi,

lib/libc/stdio/xprintf_vis.c

61

return (__printf_out(io, pi, "(null)", 6));

lib/libc/stdio/xprintf_vis.c

62

if (pi->prec >= 0)

lib/libc/stdio/xprintf_vis.c

63

l = pi->prec;

lib/libc/stdio/xprintf_vis.c

69

if (pi->showsign)

lib/libc/stdio/xprintf_vis.c

71

else if (pi->pad == '0')

lib/libc/stdio/xprintf_vis.c

73

else if (pi->alt)

lib/libc/stdio/xprintf_vis.c

77

ret += __printf_out(io, pi, buf, ret);

lib/libc/stdlib/qsort.c

51

TYPE *pi = (TYPE *) (parmi); \

lib/libc/stdlib/qsort.c

54

TYPE t = *pi; \

lib/libc/stdlib/qsort.c

55

*pi++ = *pj; \

sbin/ffsinfo/ffsinfo.c

567

struct ufs1_dinode *pi;

sbin/ffsinfo/ffsinfo.c

571

pi=(struct ufs1_dinode *)(void *)ablk;

sbin/ffsinfo/ffsinfo.c

585

return (&(pi[inumber % INOPB(&sblock)]));

sbin/growfs/growfs.c

1834

struct ufs1_dinode *pi;

sbin/growfs/growfs.c

1838

pi=(struct ufs1_dinode *)(void *)ablk;

sbin/growfs/growfs.c

1853

return (&(pi[inumber % INOPB(&sblock)]));

sbin/hammer/cmd_info.c

116

libhammer_pfsinfo_t pi, pi_first;

sbin/hammer/cmd_info.c

220

for (pi = pi_first; pi != NULL; pi = libhammer_get_next_pfs(pi)) {

sbin/hammer/cmd_info.c

222

pi->pfs_id, (pi->ismaster ? "MASTER" : "SLAVE"));

sbin/hammer/cmd_info.c

224

snprintf(buf, 6, "%d", pi->snapcount);

sbin/hammer/cmd_info.c

225

printf(" %6s", (pi->head.error && pi->snapcount == 0) ? "-" : buf);

sbin/hammer/cmd_info.c

226

if (pi->pfs_id == HAMMER_ROOT_PFSID)

sbin/newfs_msdos/mkfs_msdos.c

920

struct partinfo pi;

sbin/newfs_msdos/mkfs_msdos.c

931

if (ioctl(fd, DIOCGPART, &pi) == -1) {

sbin/newfs_msdos/mkfs_msdos.c

936

ms = pi.media_size;

sbin/newfs_msdos/mkfs_msdos.c

943

ms = pi.media_size;

sbin/newfs_msdos/mkfs_msdos.c

949

if (ioctl(fd, DIOCGPART, &pi) == - 1)

sbin/newfs_msdos/mkfs_msdos.c

951

dlp.d_secsize = pi.media_blksize;

sbin/newfs_msdos/mkfs_msdos.c

952

dlp.d_nsectors = pi.d_secpertrack;

sbin/newfs_msdos/mkfs_msdos.c

953

dlp.d_ntracks = pi.d_nheads;

stand/boot/common/bootstrap.h

163

void pnp_addident(struct pnpinfo *pi, char *ident);

stand/boot/common/bootstrap.h

165

void pnp_freeinfo(struct pnpinfo *pi);

stand/boot/common/bootstrap.h

166

void pnp_addinfo(struct pnpinfo *pi);

stand/boot/common/isapnp.c

159

isapnp_scan_resdata(struct pnpinfo *pi)

stand/boot/common/isapnp.c

176

pnp_addident(pi, pnp_eisaformat(resinfo));

stand/boot/common/isapnp.c

205

if (pi->pi_desc == NULL) {

stand/boot/common/isapnp.c

206

pi->pi_desc = (char *)str;

stand/boot/common/isapnp.c

230

struct pnpinfo *pi;

stand/boot/common/isapnp.c

248

pi = pnp_allocinfo();

stand/boot/common/isapnp.c

250

pnp_addident(pi, pnp_eisaformat(cardid));

stand/boot/common/isapnp.c

252

if (isapnp_scan_resdata(pi)) {

stand/boot/common/isapnp.c

253

pnp_freeinfo(pi); /* error getting data, ignore */

stand/boot/common/isapnp.c

255

pnp_addinfo(pi);

stand/boot/common/pnp.c

102

pnp_addident(struct pnpinfo *pi, char *ident)

stand/boot/common/pnp.c

106

STAILQ_FOREACH(id, &pi->pi_ident, id_link)

stand/boot/common/pnp.c

112

STAILQ_INSERT_TAIL(&pi->pi_ident, id, id_link);

stand/boot/common/pnp.c

121

struct pnpinfo *pi;

stand/boot/common/pnp.c

123

pi = malloc(sizeof(struct pnpinfo));

stand/boot/common/pnp.c

124

bzero(pi, sizeof(struct pnpinfo));

stand/boot/common/pnp.c

125

STAILQ_INIT(&pi->pi_ident);

stand/boot/common/pnp.c

126

return(pi);

stand/boot/common/pnp.c

133

pnp_freeinfo(struct pnpinfo *pi)

stand/boot/common/pnp.c

137

while (!STAILQ_EMPTY(&pi->pi_ident)) {

stand/boot/common/pnp.c

138

id = STAILQ_FIRST(&pi->pi_ident);

stand/boot/common/pnp.c

139

STAILQ_REMOVE_HEAD(&pi->pi_ident, id_link);

stand/boot/common/pnp.c

143

if (pi->pi_desc)

stand/boot/common/pnp.c

144

free(pi->pi_desc);

stand/boot/common/pnp.c

145

if (pi->pi_module)

stand/boot/common/pnp.c

146

free(pi->pi_module);

stand/boot/common/pnp.c

147

if (pi->pi_argv)

stand/boot/common/pnp.c

148

free(pi->pi_argv);

stand/boot/common/pnp.c

149

free(pi);

stand/boot/common/pnp.c

156

pnp_addinfo(struct pnpinfo *pi)

stand/boot/common/pnp.c

158

STAILQ_INSERT_TAIL(&pnp_devices, pi, pi_link);

stand/boot/common/pnp.c

33

struct pnpinfo *pi;

stand/boot/common/pnp.c

70

STAILQ_FOREACH(pi, &pnp_devices, pi_link) {

stand/boot/common/pnp.c

71

pager_output(STAILQ_FIRST(&pi->pi_ident)->id_ident); /* first ident should be canonical */

stand/boot/common/pnp.c

72

if (pi->pi_desc != NULL) {

stand/boot/common/pnp.c

74

pager_output(pi->pi_desc);

stand/boot/common/pnp.c

89

struct pnpinfo *pi;

stand/boot/common/pnp.c

92

pi = STAILQ_FIRST(&pnp_devices);

stand/boot/common/pnp.c

94

pnp_freeinfo(pi);

stand/boot/pc32/libi386/biospci.c

272

struct pnpinfo *pi;

stand/boot/pc32/libi386/biospci.c

289

pi = pnp_allocinfo();

stand/boot/pc32/libi386/biospci.c

290

pi->pi_desc = strdup(desc);

stand/boot/pc32/libi386/biospci.c

292

pnp_addident(pi, desc);

stand/boot/pc32/libi386/biospci.c

293

pnp_addinfo(pi);

stand/boot/pc32/libi386/biospnp.c

160

struct pnpinfo *pi;

stand/boot/pc32/libi386/biospnp.c

175

pi = pnp_allocinfo();

stand/boot/pc32/libi386/biospnp.c

176

pnp_addident(pi, pnp_eisaformat(devNodeBuffer->dn_id));

stand/boot/pc32/libi386/biospnp.c

177

biospnp_scanresdata(pi, devNodeBuffer);

stand/boot/pc32/libi386/biospnp.c

178

pnp_addinfo(pi);

stand/boot/pc32/libi386/biospnp.c

188

biospnp_scanresdata(struct pnpinfo *pi, struct pnp_devNode *dn)

stand/boot/pc32/libi386/biospnp.c

207

pnp_addident(pi, pnp_eisaformat(p + i));

stand/boot/pc32/libi386/biospnp.c

224

if (pi->pi_desc == NULL) {

stand/boot/pc32/libi386/biospnp.c

225

pi->pi_desc = str;

stand/boot/pc32/libi386/biospnp.c

88

static void biospnp_scanresdata(struct pnpinfo *pi, struct pnp_devNode *dn);

sys/dev/disk/ahci/ahci.c

112

pi = ahci_read(sc, AHCI_REG_PI);

sys/dev/disk/ahci/ahci.c

173

ahci_write(sc, AHCI_REG_PI, pi);

sys/dev/disk/ahci/ahci.c

199

pleft = pi;

sys/dev/disk/ahci/ahci.c

203

if ((pi & (1 << i)) == 0)

sys/dev/disk/ahci/ahci.c

93

u_int32_t pi, pleft;

sys/dev/disk/ahci/ahci_attach.c

225

u_int32_t pi, reg;

sys/dev/disk/ahci/ahci_attach.c

482

pi = ahci_read(sc, AHCI_REG_PI);

sys/dev/disk/ahci/ahci_attach.c

484

device_get_nameunit(sc->sc_dev), pi);

sys/dev/disk/ahci/ahci_attach.c

502

if ((pi & (1 << i)) == 0) {

sys/dev/disk/isp/isp.c

1972

vp_port_info_t pi, *pdst;

sys/dev/disk/isp/isp.c

1986

ISP_MEMZERO(&pi, sizeof (pi));

sys/dev/disk/isp/isp.c

1989

pi.vp_port_options = ICB2400_VPOPT_ENABLED;

sys/dev/disk/isp/isp.c

1991

pi.vp_port_options |= ICB2400_VPOPT_INI_ENABLE;

sys/dev/disk/isp/isp.c

1994

pi.vp_port_options |= ICB2400_VPOPT_TGT_DISABLE;

sys/dev/disk/isp/isp.c

1996

MAKE_NODE_NAME_FROM_WWN(pi.vp_port_portname, fcp2->isp_wwpn);

sys/dev/disk/isp/isp.c

1997

MAKE_NODE_NAME_FROM_WWN(pi.vp_port_nodename, fcp2->isp_wwnn);

sys/dev/disk/isp/isp.c

2002

isp_put_vp_port_info(isp, &pi, pdst);

sys/dev/disk/isp/isp_freebsd.c

3722

struct isp_spi *pi = arg;

sys/dev/disk/isp/isp_freebsd.c

3723

isp_target_thread(cam_sim_softc(pi->sim), cam_sim_bus(pi->sim));

sys/dev/drm/amd/amdgpu/ci_dpm.c

1072

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1075

if (pi->fan_ctrl_is_in_default_mode) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1078

pi->fan_ctrl_default_mode = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1081

pi->t_min = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1082

pi->fan_ctrl_is_in_default_mode = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1096

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1105

if (!pi->fan_table_start) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1160

pi->fan_table_start,

sys/dev/drm/amd/amdgpu/ci_dpm.c

1163

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1175

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1178

if (pi->caps_od_fuzzy_fan_control_support) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1197

pi->fan_is_controlled_by_smc = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1205

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1209

pi->fan_is_controlled_by_smc = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1251

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1256

if (pi->fan_is_controlled_by_smc)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1305

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1307

if (pi->fan_is_controlled_by_smc)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1368

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1371

if (!pi->fan_ctrl_is_in_default_mode) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1373

tmp |= pi->fan_ctrl_default_mode << CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1377

tmp |= pi->t_min << CG_FDO_CTRL2__TMIN__SHIFT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1379

pi->fan_ctrl_is_in_default_mode = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1437

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1440

pi->soft_regs_start + reg_offset,

sys/dev/drm/amd/amdgpu/ci_dpm.c

1441

value, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1447

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1450

pi->soft_regs_start + reg_offset,

sys/dev/drm/amd/amdgpu/ci_dpm.c

1451

value, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1456

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1457

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1459

if (pi->caps_fps) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1472

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1476

if (pi->caps_sclk_throttle_low_notification) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1477

low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1480

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

1483

sizeof(u32), pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1492

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1497

pi->vddc_leakage.count = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1498

pi->vddci_leakage.count = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1506

pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1507

pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1508

pi->vddc_leakage.count++;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1518

pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1519

pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1520

pi->vddc_leakage.count++;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1523

pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1524

pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1525

pi->vddci_leakage.count++;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1534

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1569

if (pi->thermal_protection)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1585

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1588

if (!(pi->active_auto_throttle_sources & (1 << source))) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1589

pi->active_auto_throttle_sources |= 1 << source;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1590

ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1593

if (pi->active_auto_throttle_sources & (1 << source)) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1594

pi->active_auto_throttle_sources &= ~(1 << source);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1595

ci_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1608

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1611

if (!pi->need_update_smu7_dpm_table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1614

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

1615

(pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1621

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

1622

(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1628

pi->need_update_smu7_dpm_table = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1634

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1638

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1644

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1663

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1669

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1681

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1706

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1717

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1720

if (!pi->need_update_smu7_dpm_table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

1723

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

1724

(pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1730

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

1731

(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1742

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1755

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1787

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1799

if (pi->caps_automatic_dc_transition) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1832

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1834

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1846

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1848

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1860

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1862

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1874

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1876

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

1950

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1957

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1961

pi->dpm_table_start = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1966

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1970

pi->soft_regs_start = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1975

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1979

pi->mc_reg_table_start = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1984

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1988

pi->fan_table_start = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

1993

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1997

pi->arb_table_start = tmp;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2004

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2006

pi->clock_registers.cg_spll_func_cntl =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2008

pi->clock_registers.cg_spll_func_cntl_2 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2010

pi->clock_registers.cg_spll_func_cntl_3 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2012

pi->clock_registers.cg_spll_func_cntl_4 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2014

pi->clock_registers.cg_spll_spread_spectrum =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2016

pi->clock_registers.cg_spll_spread_spectrum_2 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2018

pi->clock_registers.dll_cntl = RREG32(mmDLL_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2019

pi->clock_registers.mclk_pwrmgt_cntl = RREG32(mmMCLK_PWRMGT_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2020

pi->clock_registers.mpll_ad_func_cntl = RREG32(mmMPLL_AD_FUNC_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2021

pi->clock_registers.mpll_dq_func_cntl = RREG32(mmMPLL_DQ_FUNC_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2022

pi->clock_registers.mpll_func_cntl = RREG32(mmMPLL_FUNC_CNTL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2023

pi->clock_registers.mpll_func_cntl_1 = RREG32(mmMPLL_FUNC_CNTL_1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2024

pi->clock_registers.mpll_func_cntl_2 = RREG32(mmMPLL_FUNC_CNTL_2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2025

pi->clock_registers.mpll_ss1 = RREG32(mmMPLL_SS1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2026

pi->clock_registers.mpll_ss2 = RREG32(mmMPLL_SS2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2031

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2033

pi->low_sclk_interrupt_t = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2097

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2100

if (pi->caps_sclk_ds) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2108

if (pi->caps_sclk_ds) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2153

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2157

if (pi->caps_sclk_ss_support) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2275

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2278

if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2281

&pi->vddc_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2284

} else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2287

&pi->vddc_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2292

if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2294

&pi->vddc_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2296

if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2299

&pi->vddci_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2302

} else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2305

&pi->vddci_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2310

if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2312

&pi->vddci_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2314

if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2317

&pi->mvdd_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2320

} else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2323

&pi->mvdd_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2328

if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2330

&pi->mvdd_voltage_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2360

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2363

table->VddcLevelCount = pi->vddc_voltage_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2366

&pi->vddc_voltage_table.entries[count],

sys/dev/drm/amd/amdgpu/ci_dpm.c

2369

if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2371

pi->vddc_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2384

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2386

table->VddciLevelCount = pi->vddci_voltage_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2389

&pi->vddci_voltage_table.entries[count],

sys/dev/drm/amd/amdgpu/ci_dpm.c

2392

if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2394

pi->vddci_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2406

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2409

table->MvddLevelCount = pi->mvdd_voltage_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2412

&pi->mvdd_voltage_table.entries[count],

sys/dev/drm/amd/amdgpu/ci_dpm.c

2415

if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2417

pi->mvdd_voltage_table.entries[count].smio_low;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2449

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2452

if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2455

voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2554

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2558

ret = amdgpu_ci_read_smc_sram_dword(adev, pi->arb_table_start,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2559

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2566

return amdgpu_ci_write_smc_sram_dword(adev, pi->arb_table_start,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2567

tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2684

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2691

for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2692

for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2694

pi->dpm_table.sclk_table.dpm_levels[i].value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2695

pi->dpm_table.mclk_table.dpm_levels[j].value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2704

pi->arb_table_start,

sys/dev/drm/amd/amdgpu/ci_dpm.c

2707

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2714

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2716

if (pi->need_update_smu7_dpm_table == 0)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2726

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2732

pi->smc_state_table.GraphicsBootLevel = level;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2740

pi->smc_state_table.MemoryBootLevel = level;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2765

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2766

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2779

pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2780

pi->dpm_level_enable_mask.pcie_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2930

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2931

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2932

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2933

u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2934

u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2935

u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2936

u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2937

u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2938

u32 mpll_ss1 = pi->clock_registers.mpll_ss1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2939

u32 mpll_ss2 = pi->clock_registers.mpll_ss2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2966

if (pi->caps_mclk_ss_support) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3020

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3050

if (pi->vddc_phase_shed_control)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3061

memory_level->ActivityLevel = (u16)pi->mclk_activity_target;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3071

if (pi->mclk_stutter_mode_threshold &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

3072

(memory_clock <= pi->mclk_stutter_mode_threshold) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

3073

(!pi->uvd_enabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

3078

if (pi->mclk_strobe_mode_threshold &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

3079

(memory_clock <= pi->mclk_strobe_mode_threshold))

sys/dev/drm/amd/amdgpu/ci_dpm.c

3085

if (pi->mclk_edc_enable_threshold &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

3086

(memory_clock > pi->mclk_edc_enable_threshold))

sys/dev/drm/amd/amdgpu/ci_dpm.c

3089

if (pi->mclk_edc_wr_enable_threshold &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

3090

(memory_clock > pi->mclk_edc_wr_enable_threshold))

sys/dev/drm/amd/amdgpu/ci_dpm.c

3100

dll_state_on = pi->dll_default_on;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3134

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3137

u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3138

u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3139

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3140

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3145

if (pi->acpi_vddc)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3146

table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3148

table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3150

table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3172

table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3173

table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3174

table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3175

table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3194

if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3195

if (pi->acpi_vddci)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3197

cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3200

cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);

sys/dev/drm/amd/amdgpu/ci_dpm.c

321

struct ci_power_info *pi = adev->pm.dpm.priv;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3219

cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3221

cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3223

cpu_to_be32(pi->clock_registers.mpll_func_cntl);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3225

cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3227

cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3228

table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3229

table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

323

return pi;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3237

cpu_to_be16((u16)pi->mclk_activity_target);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3251

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3252

struct ci_ulv_parm *ulv = &pi->ulv;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3269

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3276

pi->ulv.supported = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3280

if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3294

state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3307

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3309

u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3310

u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3311

u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3312

u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3331

if (pi->caps_sclk_ss_support) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

335

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3364

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3382

if (pi->vddc_phase_shed_control)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3398

if (pi->caps_sclk_ds)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3421

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3422

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3423

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

3427

SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3435

(u16)pi->activity_target[i],

sys/dev/drm/amd/amdgpu/ci_dpm.c

3436

&pi->smc_state_table.GraphicsLevel[i]);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3440

pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3442

pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3445

pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3447

pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3448

pi->dpm_level_enable_mask.sclk_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

345

pi->powertune_defaults = &defaults_bonaire_xt;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3453

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3468

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3469

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3470

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

3474

SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3484

&pi->smc_state_table.MemoryLevel[i]);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3491

pi->smc_state_table.MemoryLevel[1].MinVddc =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3492

pi->smc_state_table.MemoryLevel[0].MinVddc;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3493

pi->smc_state_table.MemoryLevel[1].MinVddcPhases =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3494

pi->smc_state_table.MemoryLevel[0].MinVddcPhases;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3497

pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3499

pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3500

pi->dpm_level_enable_mask.mclk_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3503

pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3508

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

351

pi->powertune_defaults = &defaults_saturn_xt;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3536

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3538

if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3541

if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3542

pi->pcie_gen_powersaving = pi->pcie_gen_performance;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3543

pi->pcie_lane_powersaving = pi->pcie_lane_performance;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3544

} else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3545

pi->pcie_gen_performance = pi->pcie_gen_powersaving;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3546

pi->pcie_lane_performance = pi->pcie_lane_powersaving;

sys/dev/drm/amd/amdgpu/ci_dpm.c

355

pi->powertune_defaults = &defaults_hawaii_xt;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3550

&pi->dpm_table.pcie_speed_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3554

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3555

pi->pcie_gen_powersaving.min,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3556

pi->pcie_lane_powersaving.max);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3558

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3559

pi->pcie_gen_powersaving.min,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3560

pi->pcie_lane_powersaving.min);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3561

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3562

pi->pcie_gen_performance.min,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3563

pi->pcie_lane_performance.min);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3564

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3565

pi->pcie_gen_powersaving.min,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3566

pi->pcie_lane_powersaving.max);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3567

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3568

pi->pcie_gen_performance.min,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3569

pi->pcie_lane_performance.max);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3570

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3571

pi->pcie_gen_powersaving.max,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3572

pi->pcie_lane_powersaving.max);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3573

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3574

pi->pcie_gen_performance.max,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3575

pi->pcie_lane_performance.max);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3577

pi->dpm_table.pcie_speed_table.count = 6;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3584

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

359

pi->powertune_defaults = &defaults_hawaii_pro;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3602

memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));

sys/dev/drm/amd/amdgpu/ci_dpm.c

3605

&pi->dpm_table.sclk_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3608

&pi->dpm_table.mclk_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3611

&pi->dpm_table.vddc_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3614

&pi->dpm_table.vddci_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3617

&pi->dpm_table.mvdd_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3620

pi->dpm_table.sclk_table.count = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3623

(pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=

sys/dev/drm/amd/amdgpu/ci_dpm.c

3625

pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3627

pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3629

pi->dpm_table.sclk_table.count++;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3633

pi->dpm_table.mclk_table.count = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3636

(pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=

sys/dev/drm/amd/amdgpu/ci_dpm.c

3638

pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3640

pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3642

pi->dpm_table.mclk_table.count++;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3647

pi->dpm_table.vddc_table.dpm_levels[i].value =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3649

pi->dpm_table.vddc_table.dpm_levels[i].param1 =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3651

pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3653

pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3658

pi->dpm_table.vddci_table.dpm_levels[i].value =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3660

pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3662

pi->dpm_table.vddci_table.count = allowed_mclk_table->count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3668

pi->dpm_table.mvdd_table.dpm_levels[i].value =

sys/dev/drm/amd/amdgpu/ci_dpm.c

3670

pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3672

pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3678

memcpy(&(pi->golden_dpm_table), &(pi->dpm_table),

sys/dev/drm/amd/amdgpu/ci_dpm.c

369

pi->powertune_defaults = &defaults_bonaire_xt;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3702

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3703

struct ci_ulv_parm *ulv = &pi->ulv;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3705

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3712

if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)

sys/dev/drm/amd/amdgpu/ci_dpm.c

3727

ret = ci_populate_ulv_state(adev, &pi->smc_state_table.Ulv);

sys/dev/drm/amd/amdgpu/ci_dpm.c

373

pi->dte_tj_offset = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

375

pi->caps_power_containment = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

376

pi->caps_cac = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

377

pi->caps_sq_ramping = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3774

ret = ci_find_boot_level(&pi->dpm_table.sclk_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3775

pi->vbios_boot_state.sclk_bootup_value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3776

(u32 *)&pi->smc_state_table.GraphicsBootLevel);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3778

ret = ci_find_boot_level(&pi->dpm_table.mclk_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3779

pi->vbios_boot_state.mclk_bootup_value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

378

pi->caps_db_ramping = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3780

(u32 *)&pi->smc_state_table.MemoryBootLevel);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3782

table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3783

table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3784

table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

379

pi->caps_td_ramping = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

380

pi->caps_tcp_ramping = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3801

table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *

sys/dev/drm/amd/amdgpu/ci_dpm.c

3803

table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *

sys/dev/drm/amd/amdgpu/ci_dpm.c

3811

table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3813

if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)

sys/dev/drm/amd/amdgpu/ci_dpm.c

382

if (pi->caps_power_containment) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

383

pi->caps_cac = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3837

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

3841

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

385

pi->enable_bapm_feature = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3867

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3868

struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

387

pi->enable_bapm_feature = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

388

pi->enable_tdc_limit_feature = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

389

pi->enable_pkg_pwr_tracking_feature = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3898

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3910

&pi->dpm_table.sclk_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3915

&pi->dpm_table.mclk_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

3962

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3967

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3968

if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3971

pi->dpm_level_enable_mask.sclk_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3977

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3978

if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3981

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

3988

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3989

if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

3992

pi->dpm_level_enable_mask.pcie_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

400

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4005

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4007

struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4009

struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

401

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4013

pi->need_update_smu7_dpm_table = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

402

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4021

pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4025

pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

403

u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4034

pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4038

pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4044

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4048

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4051

if (!pi->need_update_smu7_dpm_table)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4054

if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4057

if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4060

if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4066

if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4077

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4087

pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4091

pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4093

if (!pi->caps_uvd_dpm)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4100

pi->dpm_level_enable_mask.uvd_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4102

if (pi->last_mclk_dpm_enable_mask & 0x1) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4103

pi->uvd_enabled = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4104

pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4107

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4110

if (pi->uvd_enabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4111

pi->uvd_enabled = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4112

pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4115

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4126

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4136

pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4139

pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4141

if (!pi->caps_vce_dpm)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4148

pi->dpm_level_enable_mask.vce_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4159

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4169

pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4172

pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4174

if (!pi->caps_samu_dpm)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4181

pi->dpm_level_enable_mask.samu_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4190

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4200

pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4203

pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4205

if (!pi->caps_acp_dpm)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4212

pi->dpm_level_enable_mask.acp_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4223

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4229

if (pi->caps_uvd_dpm ||

sys/dev/drm/amd/amdgpu/ci_dpm.c

4231

pi->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4233

pi->smc_state_table.UvdBootLevel =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4238

tmp |= (pi->smc_state_table.UvdBootLevel << DPM_TABLE_475__UvdBootLevel__SHIFT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4269

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4275

pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4278

tmp |= (pi->smc_state_table.VceBootLevel << DPM_TABLE_475__VceBootLevel__SHIFT);

sys/dev/drm/amd/amdgpu/ci_dpm.c

429

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4299

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

430

u8 *vid = pi->smc_powertune_table.VddCVid;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4303

pi->smc_state_table.AcpBootLevel = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4307

tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4318

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4325

pi->dpm_level_enable_mask.sclk_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4326

ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4327

pi->dpm_level_enable_mask.mclk_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4328

ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4329

pi->last_mclk_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

433

if (pi->vddc_voltage_table.count > 8)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4330

pi->dpm_level_enable_mask.mclk_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4331

if (pi->uvd_enabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4332

if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4333

pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4335

pi->dpm_level_enable_mask.pcie_dpm_enable_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

4336

ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4357

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

436

for (i = 0; i < pi->vddc_voltage_table.count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4362

if ((!pi->pcie_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

4363

pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4365

tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.c

437

vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4382

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

4383

pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4385

tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4402

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

4403

pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4405

tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4423

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

4424

pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4426

pi->dpm_level_enable_mask.sclk_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4439

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

444

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4440

pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4442

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

445

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4455

if ((!pi->pcie_dpm_key_disabled) &&

sys/dev/drm/amd/amdgpu/ci_dpm.c

4456

pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4458

pi->dpm_level_enable_mask.pcie_dpm_enable_mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

447

pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4472

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

448

pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;

sys/dev/drm/amd/amdgpu/ci_dpm.c

449

pi->smc_powertune_table.SviLoadLineTrimVddC = 3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

450

pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

457

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

458

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/amd/amdgpu/ci_dpm.c

462

pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);

sys/dev/drm/amd/amdgpu/ci_dpm.c

463

pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =

sys/dev/drm/amd/amdgpu/ci_dpm.c

465

pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;

sys/dev/drm/amd/amdgpu/ci_dpm.c

472

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

473

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4775

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4777

struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

480

(u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,

sys/dev/drm/amd/amdgpu/ci_dpm.c

481

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4835

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4838

for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4839

if (pi->mc_reg_table.valid_flag & (1 << j)) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4842

mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4843

mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);

sys/dev/drm/amd/amdgpu/ci_dpm.c

485

pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

4871

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4874

for(i = 0; i < pi->mc_reg_table.num_entries; i++) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

4875

if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4879

if ((i == pi->mc_reg_table.num_entries) && (i > 0))

sys/dev/drm/amd/amdgpu/ci_dpm.c

4882

ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],

sys/dev/drm/amd/amdgpu/ci_dpm.c

4883

mc_reg_table_data, pi->mc_reg_table.last,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4884

pi->mc_reg_table.valid_flag);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4890

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4893

for (i = 0; i < pi->dpm_table.mclk_table.count; i++)

sys/dev/drm/amd/amdgpu/ci_dpm.c

4895

pi->dpm_table.mclk_table.dpm_levels[i].value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4901

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4904

memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4906

ret = ci_populate_mc_reg_addresses(adev, &pi->smc_mc_reg_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4909

ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4912

pi->mc_reg_table_start,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4913

(u8 *)&pi->smc_mc_reg_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4915

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

492

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4920

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4922

if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))

sys/dev/drm/amd/amdgpu/ci_dpm.c

4925

memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4927

ci_convert_mc_reg_table_to_smc(adev, &pi->smc_mc_reg_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4930

pi->mc_reg_table_start +

sys/dev/drm/amd/amdgpu/ci_dpm.c

4932

(u8 *)&pi->smc_mc_reg_table.data[0],

sys/dev/drm/amd/amdgpu/ci_dpm.c

4934

pi->dpm_table.mclk_table.count,

sys/dev/drm/amd/amdgpu/ci_dpm.c

4935

pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

499

pi->smc_powertune_table.FuzzyFan_PwmSetDelta =

sys/dev/drm/amd/amdgpu/ci_dpm.c

5001

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5006

if (pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5009

current_link_speed = pi->force_pcie_gen;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5011

pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5012

pi->pspp_notify_required = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5019

pi->force_pcie_gen = AMDGPU_PCIE_GEN2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5027

pi->force_pcie_gen = ci_get_current_pcie_speed(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5032

pi->pspp_notify_required = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5040

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5045

if (pi->pspp_notify_required) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5065

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

507

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

508

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5086

pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5087

pi->max_vddc_in_pp_table =

sys/dev/drm/amd/amdgpu/ci_dpm.c

509

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5090

pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5091

pi->max_vddci_in_pp_table =

sys/dev/drm/amd/amdgpu/ci_dpm.c

5108

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5109

struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5122

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5123

struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5243

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5245

pi->current_rps = *rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5246

pi->current_ps = *new_ps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5247

pi->current_rps.ps_priv = &pi->current_ps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5248

adev->pm.dpm.current_ps = &pi->current_rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5255

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5257

pi->requested_rps = *rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5258

pi->requested_ps = *new_ps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5259

pi->requested_rps.ps_priv = &pi->requested_ps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5260

adev->pm.dpm.requested_ps = &pi->requested_rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5266

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5272

ci_apply_state_adjust_rules(adev, &pi->requested_rps);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5280

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5281

struct amdgpu_ps *new_ps = &pi->requested_rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5296

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5300

if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5308

if (pi->caps_dynamic_ac_timing) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

531

pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5311

pi->caps_dynamic_ac_timing = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5313

if (pi->dynamic_ss)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5315

if (pi->thermal_protection)

sys/dev/drm/amd/amdgpu/ci_dpm.c

532

pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5345

if (pi->caps_dynamic_ac_timing) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

539

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

540

u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

541

u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5419

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5434

if (pi->thermal_protection)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5456

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5457

struct amdgpu_ps *new_ps = &pi->requested_rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5458

struct amdgpu_ps *old_ps = &pi->current_rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5462

if (pi->pcie_performance_request)

sys/dev/drm/amd/amdgpu/ci_dpm.c

548

pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);

sys/dev/drm/amd/amdgpu/ci_dpm.c

549

pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5491

if (pi->caps_dynamic_ac_timing) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

5513

if (pi->pcie_performance_request)

sys/dev/drm/amd/amdgpu/ci_dpm.c

556

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

557

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/amd/amdgpu/ci_dpm.c

558

SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5583

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5595

pi->sys_pcie_mask,

sys/dev/drm/amd/amdgpu/ci_dpm.c

5596

pi->vbios_boot_state.pcie_gen_bootup_value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

5599

pi->vbios_boot_state.pcie_lane_bootup_value,

sys/dev/drm/amd/amdgpu/ci_dpm.c

5603

pi->acpi_pcie_gen = pl->pcie_gen;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5607

pi->ulv.supported = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5608

pi->ulv.pl = *pl;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5609

pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5614

pl->mclk = pi->vbios_boot_state.mclk_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5615

pl->sclk = pi->vbios_boot_state.sclk_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5616

pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5617

pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5622

pi->use_pcie_powersaving_levels = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5623

if (pi->pcie_gen_powersaving.max < pl->pcie_gen)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5624

pi->pcie_gen_powersaving.max = pl->pcie_gen;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5625

if (pi->pcie_gen_powersaving.min > pl->pcie_gen)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5626

pi->pcie_gen_powersaving.min = pl->pcie_gen;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5627

if (pi->pcie_lane_powersaving.max < pl->pcie_lane)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5628

pi->pcie_lane_powersaving.max = pl->pcie_lane;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5629

if (pi->pcie_lane_powersaving.min > pl->pcie_lane)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5630

pi->pcie_lane_powersaving.min = pl->pcie_lane;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5633

pi->use_pcie_performance_levels = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5634

if (pi->pcie_gen_performance.max < pl->pcie_gen)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5635

pi->pcie_gen_performance.max = pl->pcie_gen;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5636

if (pi->pcie_gen_performance.min > pl->pcie_gen)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5637

pi->pcie_gen_performance.min = pl->pcie_gen;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5638

if (pi->pcie_lane_performance.max < pl->pcie_lane)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5639

pi->pcie_lane_performance.max = pl->pcie_lane;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5640

if (pi->pcie_lane_performance.min > pl->pcie_lane)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5641

pi->pcie_lane_performance.min = pl->pcie_lane;

sys/dev/drm/amd/amdgpu/ci_dpm.c

569

dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;

sys/dev/drm/amd/amdgpu/ci_dpm.c

571

(u8)(pi->thermal_temp_setting.temperature_high / 1000);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5840

struct ci_power_info *pi;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5843

pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5844

if (pi == NULL)

sys/dev/drm/amd/amdgpu/ci_dpm.c

5846

adev->pm.dpm.priv = pi;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5848

pi->sys_pcie_mask =

sys/dev/drm/amd/amdgpu/ci_dpm.c

5851

pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5853

pi->pcie_gen_performance.max = AMDGPU_PCIE_GEN1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5854

pi->pcie_gen_performance.min = AMDGPU_PCIE_GEN3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5855

pi->pcie_gen_powersaving.max = AMDGPU_PCIE_GEN1;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5856

pi->pcie_gen_powersaving.min = AMDGPU_PCIE_GEN3;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5858

pi->pcie_lane_performance.max = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5859

pi->pcie_lane_performance.min = 16;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5860

pi->pcie_lane_powersaving.max = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5861

pi->pcie_lane_powersaving.min = 16;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5863

ret = ci_get_vbios_boot_values(adev, &pi->vbios_boot_state);

sys/dev/drm/amd/amdgpu/ci_dpm.c

5887

pi->dll_default_on = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5888

pi->sram_end = SMC_RAM_END;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5890

pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5891

pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5892

pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5893

pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5894

pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5895

pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5896

pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5897

pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5899

pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5901

pi->sclk_dpm_key_disabled = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5902

pi->mclk_dpm_key_disabled = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5903

pi->pcie_dpm_key_disabled = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5904

pi->thermal_sclk_dpm_enabled = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5907

pi->caps_sclk_ds = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5909

pi->caps_sclk_ds = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5911

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5912

pi->mclk_stutter_mode_threshold = 40000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5913

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5914

pi->mclk_edc_wr_enable_threshold = 40000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5918

pi->caps_fps = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5920

pi->caps_sclk_throttle_low_notification = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5922

pi->caps_uvd_dpm = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5923

pi->caps_vce_dpm = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5957

pi->thermal_temp_setting.temperature_low = 94500;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5958

pi->thermal_temp_setting.temperature_high = 95000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5959

pi->thermal_temp_setting.temperature_shutdown = 104000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5961

pi->thermal_temp_setting.temperature_low = 99500;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5962

pi->thermal_temp_setting.temperature_high = 100000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5963

pi->thermal_temp_setting.temperature_shutdown = 104000;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5966

pi->uvd_enabled = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

5968

dpm_table = &pi->smc_state_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6017

pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6018

pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6019

pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6021

pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6023

pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6027

pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6029

pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6036

pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6038

pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;

sys/dev/drm/amd/amdgpu/ci_dpm.c

604

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6043

pi->vddc_phase_shed_control = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6046

pi->pcie_performance_request =

sys/dev/drm/amd/amdgpu/ci_dpm.c

6049

pi->pcie_performance_request = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6054

pi->caps_sclk_ss_support = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6055

pi->caps_mclk_ss_support = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6056

pi->dynamic_ss = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6058

pi->caps_sclk_ss_support = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6059

pi->caps_mclk_ss_support = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6060

pi->dynamic_ss = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6064

pi->thermal_protection = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6066

pi->thermal_protection = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6068

pi->caps_dynamic_ac_timing = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6070

pi->uvd_power_gated = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6078

pi->fan_ctrl_is_in_default_mode = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

608

if (pi->caps_power_containment) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

6088

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6089

struct amdgpu_ps *rps = &pi->current_rps;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6104

seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");

sys/dev/drm/amd/amdgpu/ci_dpm.c

612

&pm_fuse_table_offset, pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6186

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6187

struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6198

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6199

struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);

sys/dev/drm/amd/amdgpu/ci_dpm.c

640

(u8 *)&pi->smc_powertune_table,

sys/dev/drm/amd/amdgpu/ci_dpm.c

641

sizeof(SMU7_Discrete_PmFuses), pi->sram_end);

sys/dev/drm/amd/amdgpu/ci_dpm.c

651

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

654

if (pi->caps_sq_ramping) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

6542

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6543

struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6544

struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6545

struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6610

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6620

if (!pi->sclk_dpm_key_disabled)

sys/dev/drm/amd/amdgpu/ci_dpm.c

6623

pi->dpm_level_enable_mask.sclk_dpm_enable_mask & mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6627

if (!pi->mclk_dpm_key_disabled)

sys/dev/drm/amd/amdgpu/ci_dpm.c

663

if (pi->caps_db_ramping) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

6630

pi->dpm_level_enable_mask.mclk_dpm_enable_mask & mask);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6635

uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6637

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

6657

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6658

struct ci_single_dpm_table *sclk_table = &(pi->dpm_table.sclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6660

&(pi->golden_dpm_table.sclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6674

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6677

&(pi->golden_dpm_table.sclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6693

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6694

struct ci_single_dpm_table *mclk_table = &(pi->dpm_table.mclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6696

&(pi->golden_dpm_table.mclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6710

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6713

&(pi->golden_dpm_table.mclk_table);

sys/dev/drm/amd/amdgpu/ci_dpm.c

672

if (pi->caps_td_ramping) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

681

if (pi->caps_tcp_ramping) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

741

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

744

if (pi->caps_sq_ramping || pi->caps_db_ramping ||

sys/dev/drm/amd/amdgpu/ci_dpm.c

745

pi->caps_td_ramping || pi->caps_tcp_ramping) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

766

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

771

pi->power_containment_features = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

772

if (pi->caps_power_containment) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

773

if (pi->enable_bapm_feature) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

778

pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;

sys/dev/drm/amd/amdgpu/ci_dpm.c

781

if (pi->enable_tdc_limit_feature) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

786

pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;

sys/dev/drm/amd/amdgpu/ci_dpm.c

789

if (pi->enable_pkg_pwr_tracking_feature) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

799

pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;

sys/dev/drm/amd/amdgpu/ci_dpm.c

806

if (pi->caps_power_containment && pi->power_containment_features) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

807

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)

sys/dev/drm/amd/amdgpu/ci_dpm.c

810

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)

sys/dev/drm/amd/amdgpu/ci_dpm.c

813

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)

sys/dev/drm/amd/amdgpu/ci_dpm.c

815

pi->power_containment_features = 0;

sys/dev/drm/amd/amdgpu/ci_dpm.c

824

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

828

if (pi->caps_cac) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

833

pi->cac_enabled = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

835

pi->cac_enabled = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

837

} else if (pi->cac_enabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

839

pi->cac_enabled = false;

sys/dev/drm/amd/amdgpu/ci_dpm.c

849

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

852

if (pi->thermal_sclk_dpm_enabled) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

867

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

875

if (pi->caps_power_containment) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

890

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

892

pi->uvd_power_gated = gate;

sys/dev/drm/amd/amdgpu/ci_dpm.c

929

struct ci_power_info *pi = ci_get_pi(adev);

sys/dev/drm/amd/amdgpu/ci_dpm.c

950

pi->battery_state = true;

sys/dev/drm/amd/amdgpu/ci_dpm.c

952

pi->battery_state = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1001

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1003

pi->vce_level_count++;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1007

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1009

(u8 *)&pi->vce_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1011

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1015

pi->vce_interval = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1018

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1020

(u8 *)&pi->vce_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1022

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1027

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1029

(u8 *)&pi->vce_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1031

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1038

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1048

pi->samu_level_count = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1050

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

1051

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1054

pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1055

pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1057

pi->samu_level[i].ClkBypassCntl =

sys/dev/drm/amd/amdgpu/kv_dpm.c

1064

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1066

pi->samu_level_count++;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1070

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1072

(u8 *)&pi->samu_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1074

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1078

pi->samu_interval = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1081

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1083

(u8 *)&pi->samu_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1085

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1090

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1092

(u8 *)&pi->samu_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1094

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1104

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1114

pi->acp_level_count = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1116

pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1117

pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1123

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1125

pi->acp_level_count++;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1129

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1131

(u8 *)&pi->acp_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1133

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1137

pi->acp_interval = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1140

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1142

(u8 *)&pi->acp_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1144

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1149

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1151

(u8 *)&pi->acp_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1153

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1162

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1168

for (i = 0; i < pi->graphics_dpm_level_count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1169

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1171

pi->graphics_level[i].ClkBypassCntl = 3;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1173

pi->graphics_level[i].ClkBypassCntl = 2;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1175

pi->graphics_level[i].ClkBypassCntl = 7;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1177

pi->graphics_level[i].ClkBypassCntl = 6;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1179

pi->graphics_level[i].ClkBypassCntl = 8;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1181

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1183

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1188

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1189

for (i = 0; i < pi->graphics_dpm_level_count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1190

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1192

pi->graphics_level[i].ClkBypassCntl = 3;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1194

pi->graphics_level[i].ClkBypassCntl = 2;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1196

pi->graphics_level[i].ClkBypassCntl = 7;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1198

pi->graphics_level[i].ClkBypassCntl = 6;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1200

pi->graphics_level[i].ClkBypassCntl = 8;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1202

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1204

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1218

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1220

pi->acp_boot_level = 0xff;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1227

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1229

pi->current_rps = *rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1230

pi->current_ps = *new_ps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1231

pi->current_rps.ps_priv = &pi->current_ps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1232

adev->pm.dpm.current_ps = &pi->current_rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1239

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1241

pi->requested_rps = *rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1242

pi->requested_ps = *new_ps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1243

pi->requested_rps.ps_priv = &pi->requested_ps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1244

adev->pm.dpm.requested_ps = &pi->requested_rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1250

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1253

if (pi->bapm_enable) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1262

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1308

if (pi->enable_auto_thermal_throttling) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1373

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1388

if (pi->caps_vce_pg) /* power on the VCE block */

sys/dev/drm/amd/amdgpu/kv_dpm.c

1390

if (pi->caps_uvd_pg) /* power on the UVD block */

sys/dev/drm/amd/amdgpu/kv_dpm.c

1407

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1409

return amdgpu_kv_copy_bytes_to_smc(adev, pi->soft_regs_start + reg_offset,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1410

(u8 *)&value, sizeof(u16), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1416

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1418

return amdgpu_kv_read_smc_sram_dword(adev, pi->soft_regs_start + reg_offset,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1419

value, pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1425

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1427

pi->low_sclk_interrupt_t = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1432

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1435

if (pi->caps_fps) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1439

pi->fps_high_t = cpu_to_be16(tmp);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1441

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1443

(u8 *)&pi->fps_high_t,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1444

sizeof(u16), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1447

pi->fps_low_t = cpu_to_be16(tmp);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1450

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1452

(u8 *)&pi->fps_low_t,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1453

sizeof(u16), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1461

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1463

pi->uvd_power_gated = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1464

pi->vce_power_gated = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1465

pi->samu_power_gated = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1466

pi->acp_power_gated = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1496

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1504

pi->uvd_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1506

pi->uvd_boot_level = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1508

if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1509

mask = 1 << pi->uvd_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1515

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1517

(uint8_t *)&pi->uvd_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1518

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1548

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1554

if (pi->caps_stable_p_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1555

pi->vce_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1557

pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1560

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1562

(u8 *)&pi->vce_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1564

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1568

if (pi->caps_stable_p_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1571

(1 << pi->vce_boot_level));

sys/dev/drm/amd/amdgpu/kv_dpm.c

1582

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1588

if (pi->caps_stable_p_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1589

pi->samu_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1591

pi->samu_boot_level = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1594

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1596

(u8 *)&pi->samu_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1598

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1602

if (pi->caps_stable_p_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1605

(1 << pi->samu_boot_level));

sys/dev/drm/amd/amdgpu/kv_dpm.c

1630

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1633

if (!pi->caps_stable_p_state) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1635

if (acp_boot_level != pi->acp_boot_level) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1636

pi->acp_boot_level = acp_boot_level;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1639

(1 << pi->acp_boot_level));

sys/dev/drm/amd/amdgpu/kv_dpm.c

1646

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1652

if (pi->caps_stable_p_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1653

pi->acp_boot_level = table->count - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1655

pi->acp_boot_level = kv_get_acp_boot_level(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1658

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1660

(u8 *)&pi->acp_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1662

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1666

if (pi->caps_stable_p_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1669

(1 << pi->acp_boot_level));

sys/dev/drm/amd/amdgpu/kv_dpm.c

1678

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1681

pi->uvd_power_gated = gate;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1688

if (pi->caps_uvd_pg)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1692

if (pi->caps_uvd_pg)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1706

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1709

pi->vce_power_gated = gate;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1716

if (pi->caps_vce_pg) /* power off the VCE block */

sys/dev/drm/amd/amdgpu/kv_dpm.c

1719

if (pi->caps_vce_pg) /* power on the VCE block */

sys/dev/drm/amd/amdgpu/kv_dpm.c

1731

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1733

if (pi->samu_power_gated == gate)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1736

pi->samu_power_gated = gate;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1740

if (pi->caps_samu_pg)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1743

if (pi->caps_samu_pg)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1751

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1753

if (pi->acp_power_gated == gate)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1759

pi->acp_power_gated = gate;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1763

if (pi->caps_acp_pg)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1766

if (pi->caps_acp_pg)

sys/dev/drm/amd/amdgpu/kv_dpm.c

1776

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1782

for (i = 0; i < pi->graphics_dpm_level_count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1784

(i == (pi->graphics_dpm_level_count - 1))) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1785

pi->lowest_valid = i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1790

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1794

pi->highest_valid = i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1796

if (pi->lowest_valid > pi->highest_valid) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1797

if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >

sys/dev/drm/amd/amdgpu/kv_dpm.c

1798

(table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))

sys/dev/drm/amd/amdgpu/kv_dpm.c

1799

pi->highest_valid = pi->lowest_valid;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1801

pi->lowest_valid = pi->highest_valid;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1805

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1807

for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1809

i == (int)(pi->graphics_dpm_level_count - 1)) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1810

pi->lowest_valid = i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1815

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1820

pi->highest_valid = i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1822

if (pi->lowest_valid > pi->highest_valid) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1824

table->entries[pi->highest_valid].sclk_frequency) >

sys/dev/drm/amd/amdgpu/kv_dpm.c

1825

(table->entries[pi->lowest_valid].sclk_frequency -

sys/dev/drm/amd/amdgpu/kv_dpm.c

1827

pi->highest_valid = pi->lowest_valid;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1829

pi->lowest_valid = pi->highest_valid;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1838

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1842

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1844

pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1846

(pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1848

(pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +

sys/dev/drm/amd/amdgpu/kv_dpm.c

1851

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1860

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1864

if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1867

pi->nb_dpm_enabled = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1870

if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1873

pi->nb_dpm_enabled = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1908

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1915

&pi->requested_rps,

sys/dev/drm/amd/amdgpu/kv_dpm.c

1916

&pi->current_rps);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1924

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

1925

struct amdgpu_ps *new_ps = &pi->requested_rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1926

struct amdgpu_ps *old_ps = &pi->current_rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

1929

if (pi->bapm_enable) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1938

if (pi->enable_dpm) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1967

if (pi->enable_dpm) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

1999

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2000

struct amdgpu_ps *new_ps = &pi->requested_rps;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2015

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2030

kv_set_enabled_level(adev, pi->graphics_boot_level);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2038

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2040

if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2041

int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2043

pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2046

pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2049

table->mclk = pi->sys_info.nbp_memory_clock[0];

sys/dev/drm/amd/amdgpu/kv_dpm.c

2096

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2098

pi->boot_pl.sclk = pi->sys_info.bootup_sclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2099

pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2100

pi->boot_pl.ds_divider_index = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2101

pi->boot_pl.ss_divider_index = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2102

pi->boot_pl.allow_gnb_slow = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2103

pi->boot_pl.force_nbp_state = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2104

pi->boot_pl.display_wm = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2105

pi->boot_pl.vce_wm = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2151

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2159

if (!pi->caps_sclk_ds)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2173

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2180

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

2182

pi->high_voltage_t)) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2189

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2192

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

2194

pi->high_voltage_t)) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2210

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2232

if (pi->caps_stable_p_state) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2262

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

2263

(pi->high_voltage_t <

sys/dev/drm/amd/amdgpu/kv_dpm.c

2271

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2274

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

2275

(pi->high_voltage_t <

sys/dev/drm/amd/amdgpu/kv_dpm.c

2283

if (pi->caps_stable_p_state) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2289

pi->video_start = new_rps->dclk || new_rps->vclk ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

2294

pi->battery_state = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2296

pi->battery_state = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2309

if (pi->sys_info.nb_dpm_enable) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2310

force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

2311

pi->video_start || (adev->pm.dpm.new_active_crtc_count >= 3) ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

2312

pi->disable_nb_ps3_in_battery;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2324

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2326

pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2331

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2335

if (pi->lowest_valid > pi->highest_valid)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2338

for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2339

pi->graphics_level[i].DeepSleepDivId =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2341

be32_to_cpu(pi->graphics_level[i].SclkFrequency),

sys/dev/drm/amd/amdgpu/kv_dpm.c

2349

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2356

if (pi->lowest_valid > pi->highest_valid)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2360

for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2361

pi->graphics_level[i].GnbSlow = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2362

pi->graphics_level[i].ForceNbPs1 = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2363

pi->graphics_level[i].UpH = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2366

if (!pi->sys_info.nb_dpm_enable)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2369

force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

2370

(adev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2373

for (i = pi->lowest_valid; i <= pi->highest_valid; i++)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2374

pi->graphics_level[i].GnbSlow = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2376

if (pi->battery_state)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2377

pi->graphics_level[0].ForceNbPs1 = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2379

pi->graphics_level[1].GnbSlow = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2380

pi->graphics_level[2].GnbSlow = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2381

pi->graphics_level[3].GnbSlow = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2382

pi->graphics_level[4].GnbSlow = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2385

for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2386

pi->graphics_level[i].GnbSlow = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2387

pi->graphics_level[i].ForceNbPs1 = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2388

pi->graphics_level[i].UpH = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2391

if (pi->sys_info.nb_dpm_enable && pi->battery_state) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2392

pi->graphics_level[pi->lowest_valid].UpH = 0x28;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2393

pi->graphics_level[pi->lowest_valid].GnbSlow = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2394

if (pi->lowest_valid != pi->highest_valid)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2395

pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2403

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2406

if (pi->lowest_valid > pi->highest_valid)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2409

for (i = pi->lowest_valid; i <= pi->highest_valid; i++)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2410

pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2417

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2425

pi->graphics_dpm_level_count = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2427

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

2428

(pi->high_voltage_t <

sys/dev/drm/amd/amdgpu/kv_dpm.c

2434

&pi->sys_info.vid_mapping_table,

sys/dev/drm/amd/amdgpu/kv_dpm.c

2437

kv_set_at(adev, i, pi->at[i]);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2439

pi->graphics_dpm_level_count++;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2443

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2445

pi->graphics_dpm_level_count = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2447

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

2448

pi->high_voltage_t <

sys/dev/drm/amd/amdgpu/kv_dpm.c

2454

kv_set_at(adev, i, pi->at[i]);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2456

pi->graphics_dpm_level_count++;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2466

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2470

if (i >= pi->lowest_valid && i <= pi->highest_valid)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2486

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2489

for (i = pi->lowest_valid; i <= pi->highest_valid; i++)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2501

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2507

if (pi->sys_info.nb_dpm_enable) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2561

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2578

pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2579

pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2580

pi->sys_info.bootup_nb_voltage_index =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2583

pi->sys_info.htc_tmp_lmt = 203;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2585

pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2587

pi->sys_info.htc_hyst_lmt = 5;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2589

pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2590

if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2595

pi->sys_info.nb_dpm_enable = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2597

pi->sys_info.nb_dpm_enable = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2600

pi->sys_info.nbp_memory_clock[i] =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2602

pi->sys_info.nbp_n_clock[i] =

sys/dev/drm/amd/amdgpu/kv_dpm.c

2607

pi->caps_enable_dfs_bypass = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2610

&pi->sys_info.sclk_voltage_mapping_table,

sys/dev/drm/amd/amdgpu/kv_dpm.c

2614

&pi->sys_info.vid_mapping_table,

sys/dev/drm/amd/amdgpu/kv_dpm.c

2647

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2650

ps->levels[0] = pi->boot_pl;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2684

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2696

if (pi->caps_sclk_ds) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2794

struct kv_power_info *pi;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2797

pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2798

if (pi == NULL)

sys/dev/drm/amd/amdgpu/kv_dpm.c

2800

adev->pm.dpm.priv = pi;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2811

pi->at[i] = TRINITY_AT_DFLT;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2813

pi->sram_end = SMC_RAM_END;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2815

pi->enable_nb_dpm = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2817

pi->caps_power_containment = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2818

pi->caps_cac = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2819

pi->enable_didt = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2820

if (pi->enable_didt) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

2821

pi->caps_sq_ramping = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2822

pi->caps_db_ramping = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2823

pi->caps_td_ramping = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2824

pi->caps_tcp_ramping = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2828

pi->caps_sclk_ds = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2830

pi->caps_sclk_ds = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2832

pi->enable_auto_thermal_throttling = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2833

pi->disable_nb_ps3_in_battery = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2835

pi->bapm_enable = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2837

pi->bapm_enable = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2838

pi->voltage_drop_t = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2839

pi->caps_sclk_throttle_low_notification = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2840

pi->caps_fps = false; /* true? */

sys/dev/drm/amd/amdgpu/kv_dpm.c

2841

pi->caps_uvd_pg = (adev->pg_flags & AMD_PG_SUPPORT_UVD) ? true : false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2842

pi->caps_uvd_dpm = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2843

pi->caps_vce_pg = (adev->pg_flags & AMD_PG_SUPPORT_VCE) ? true : false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2844

pi->caps_samu_pg = (adev->pg_flags & AMD_PG_SUPPORT_SAMU) ? true : false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2845

pi->caps_acp_pg = (adev->pg_flags & AMD_PG_SUPPORT_ACP) ? true : false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2846

pi->caps_stable_p_state = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2859

pi->enable_dpm = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

2869

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2880

sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2885

seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");

sys/dev/drm/amd/amdgpu/kv_dpm.c

2886

seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");

sys/dev/drm/amd/amdgpu/kv_dpm.c

2932

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2933

struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2944

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

2946

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3285

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

3300

pi->graphics_level[pl_index].SclkFrequency);

sys/dev/drm/amd/amdgpu/kv_dpm.c

380

struct kv_power_info *pi = adev->pm.dpm.priv;

sys/dev/drm/amd/amdgpu/kv_dpm.c

382

return pi;

sys/dev/drm/amd/amdgpu/kv_dpm.c

462

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

465

if (pi->caps_sq_ramping) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

474

if (pi->caps_db_ramping) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

483

if (pi->caps_td_ramping) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

492

if (pi->caps_tcp_ramping) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

504

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

507

if (pi->caps_sq_ramping ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

508

pi->caps_db_ramping ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

509

pi->caps_td_ramping ||

sys/dev/drm/amd/amdgpu/kv_dpm.c

510

pi->caps_tcp_ramping) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

532

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

534

if (pi->caps_cac) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

564

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

567

if (pi->caps_cac) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

571

pi->cac_enabled = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

573

pi->cac_enabled = true;

sys/dev/drm/amd/amdgpu/kv_dpm.c

574

} else if (pi->cac_enabled) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

576

pi->cac_enabled = false;

sys/dev/drm/amd/amdgpu/kv_dpm.c

585

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

591

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

594

pi->dpm_table_start = tmp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

598

&tmp, pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

601

pi->soft_regs_start = tmp;

sys/dev/drm/amd/amdgpu/kv_dpm.c

608

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

611

pi->graphics_voltage_change_enable = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

614

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

616

&pi->graphics_voltage_change_enable,

sys/dev/drm/amd/amdgpu/kv_dpm.c

617

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

624

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

627

pi->graphics_interval = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

630

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

632

&pi->graphics_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

633

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

640

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

644

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

646

&pi->graphics_boot_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

647

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

665

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

674

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

675

pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

689

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

691

&pi->sys_info.vid_mapping_table,

sys/dev/drm/amd/amdgpu/kv_dpm.c

700

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

702

pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;

sys/dev/drm/amd/amdgpu/kv_dpm.c

703

pi->graphics_level[index].MinVddNb =

sys/dev/drm/amd/amdgpu/kv_dpm.c

711

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

713

pi->graphics_level[index].AT = cpu_to_be16((u16)at);

sys/dev/drm/amd/amdgpu/kv_dpm.c

721

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

723

pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

783

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

787

if (pi->caps_sclk_throttle_low_notification) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

788

low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);

sys/dev/drm/amd/amdgpu/kv_dpm.c

791

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

794

sizeof(u32), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

801

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

807

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

808

if (table->entries[i].clk == pi->boot_pl.sclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

812

pi->graphics_boot_level = (u8)i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

816

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/amd/amdgpu/kv_dpm.c

821

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

822

if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)

sys/dev/drm/amd/amdgpu/kv_dpm.c

826

pi->graphics_boot_level = (u8)i;

sys/dev/drm/amd/amdgpu/kv_dpm.c

834

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

837

pi->graphics_therm_throttle_enable = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

840

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

842

&pi->graphics_therm_throttle_enable,

sys/dev/drm/amd/amdgpu/kv_dpm.c

843

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

850

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

854

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

856

(u8 *)&pi->graphics_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

858

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

864

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

866

&pi->graphics_dpm_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

867

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

879

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

882

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/amd/amdgpu/kv_dpm.c

904

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

914

pi->uvd_level_count = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

916

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

917

(pi->high_voltage_t < table->entries[i].v))

sys/dev/drm/amd/amdgpu/kv_dpm.c

920

pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

921

pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

922

pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

924

pi->uvd_level[i].VClkBypassCntl =

sys/dev/drm/amd/amdgpu/kv_dpm.c

926

pi->uvd_level[i].DClkBypassCntl =

sys/dev/drm/amd/amdgpu/kv_dpm.c

933

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

939

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/drm/amd/amdgpu/kv_dpm.c

941

pi->uvd_level_count++;

sys/dev/drm/amd/amdgpu/kv_dpm.c

945

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

947

(u8 *)&pi->uvd_level_count,

sys/dev/drm/amd/amdgpu/kv_dpm.c

948

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

952

pi->uvd_interval = 1;

sys/dev/drm/amd/amdgpu/kv_dpm.c

955

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

957

&pi->uvd_interval,

sys/dev/drm/amd/amdgpu/kv_dpm.c

958

sizeof(u8), pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

963

pi->dpm_table_start +

sys/dev/drm/amd/amdgpu/kv_dpm.c

965

(u8 *)&pi->uvd_level,

sys/dev/drm/amd/amdgpu/kv_dpm.c

967

pi->sram_end);

sys/dev/drm/amd/amdgpu/kv_dpm.c

975

struct kv_power_info *pi = kv_get_pi(adev);

sys/dev/drm/amd/amdgpu/kv_dpm.c

985

pi->vce_level_count = 0;

sys/dev/drm/amd/amdgpu/kv_dpm.c

987

if (pi->high_voltage_t &&

sys/dev/drm/amd/amdgpu/kv_dpm.c

988

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/amd/amdgpu/kv_dpm.c

991

pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);

sys/dev/drm/amd/amdgpu/kv_dpm.c

992

pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

994

pi->vce_level[i].ClkBypassCntl =

sys/dev/drm/amd/amdgpu/si_dpm.c

1857

struct si_power_info *pi = adev->pm.dpm.priv;

sys/dev/drm/amd/amdgpu/si_dpm.c

1858

return pi;

sys/dev/drm/amd/amdgpu/si_dpm.c

1959

struct rv7xx_power_info *pi = adev->pm.dpm.priv;

sys/dev/drm/amd/amdgpu/si_dpm.c

1961

return pi;

sys/dev/drm/amd/amdgpu/si_dpm.c

1966

struct ni_power_info *pi = adev->pm.dpm.priv;

sys/dev/drm/amd/amdgpu/si_dpm.c

1968

return pi;

sys/dev/drm/amd/amdgpu/si_dpm.c

2378

struct evergreen_power_info *pi = adev->pm.dpm.priv;

sys/dev/drm/amd/amdgpu/si_dpm.c

2380

return pi;

sys/dev/drm/amd/amdgpu/si_dpm.c

3399

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

3403

pi->max_vddc = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

3405

pi->max_vddc = vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

3410

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

3413

pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,

sys/dev/drm/amd/amdgpu/si_dpm.c

3415

pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,

sys/dev/drm/amd/amdgpu/si_dpm.c

3418

if (pi->sclk_ss || pi->mclk_ss)

sys/dev/drm/amd/amdgpu/si_dpm.c

3419

pi->dynamic_ss = true;

sys/dev/drm/amd/amdgpu/si_dpm.c

3421

pi->dynamic_ss = false;

sys/dev/drm/amd/amdgpu/si_dpm.c

3738

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

3764

if (pi->thermal_protection)

sys/dev/drm/amd/amdgpu/si_dpm.c

3775

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

3778

if (!(pi->active_auto_throttle_sources & (1 << source))) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3779

pi->active_auto_throttle_sources |= 1 << source;

sys/dev/drm/amd/amdgpu/si_dpm.c

3780

si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);

sys/dev/drm/amd/amdgpu/si_dpm.c

3783

if (pi->active_auto_throttle_sources & (1 << source)) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3784

pi->active_auto_throttle_sources &= ~(1 << source);

sys/dev/drm/amd/amdgpu/si_dpm.c

3785

si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);

sys/dev/drm/amd/amdgpu/si_dpm.c

4193

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4196

if (pi->sclk_ss)

sys/dev/drm/amd/amdgpu/si_dpm.c

4206

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4209

r600_calculate_u_and_p(pi->asi,

sys/dev/drm/amd/amdgpu/si_dpm.c

4212

&pi->bsp,

sys/dev/drm/amd/amdgpu/si_dpm.c

4213

&pi->bsu);

sys/dev/drm/amd/amdgpu/si_dpm.c

4215

r600_calculate_u_and_p(pi->pasi,

sys/dev/drm/amd/amdgpu/si_dpm.c

4218

&pi->pbsp,

sys/dev/drm/amd/amdgpu/si_dpm.c

4219

&pi->pbsu);

sys/dev/drm/amd/amdgpu/si_dpm.c

4222

pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);

sys/dev/drm/amd/amdgpu/si_dpm.c

4223

pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);

sys/dev/drm/amd/amdgpu/si_dpm.c

4225

WREG32(CG_BSP, pi->dsp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4279

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4281

WREG32(CG_FTV, pi->vrc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4326

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4330

if (mclk <= pi->mclk_strobe_mode_threshold)

sys/dev/drm/amd/amdgpu/si_dpm.c

4421

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4426

if (pi->voltage_control) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4465

if (pi->mvdd_control) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4470

pi->mvdd_control = false;

sys/dev/drm/amd/amdgpu/si_dpm.c

4475

pi->mvdd_control = false;

sys/dev/drm/amd/amdgpu/si_dpm.c

4512

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4531

if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4595

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4598

if (pi->mvdd_control) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4599

if (mclk <= pi->mvdd_split_frequency)

sys/dev/drm/amd/amdgpu/si_dpm.c

4819

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4822

if (pi->mvdd_control)

sys/dev/drm/amd/amdgpu/si_dpm.c

4834

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4917

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4925

if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/amd/amdgpu/si_dpm.c

4953

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

4974

if (pi->acpi_vddc) {

sys/dev/drm/amd/amdgpu/si_dpm.c

4976

pi->acpi_vddc, &table->ACPIState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4992

pi->acpi_vddc,

sys/dev/drm/amd/amdgpu/si_dpm.c

4999

pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);

sys/dev/drm/amd/amdgpu/si_dpm.c

5020

pi->min_vddc_in_table,

sys/dev/drm/amd/amdgpu/si_dpm.c

5026

if (pi->acpi_vddc) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5151

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

5153

pi->mvdd_split_frequency = 30000;

sys/dev/drm/amd/amdgpu/si_dpm.c

5247

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

5284

if (pi->sclk_ss) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5341

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

5375

if (pi->mclk_ss) {

sys/dev/drm/amd/amdgpu/si_dpm.c

5428

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

5432

smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/amd/amdgpu/si_dpm.c

5435

cpu_to_be32(pi->psp);

sys/dev/drm/amd/amdgpu/si_dpm.c

5442

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

5462

if (pi->mclk_stutter_mode_threshold &&

sys/dev/drm/amd/amdgpu/si_dpm.c

5463

(pl->mclk <= pi->mclk_stutter_mode_threshold) &&

sys/dev/drm/amd/amdgpu/si_dpm.c

5474

if (pl->mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/amd/amdgpu/si_dpm.c

5551

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

5584

a_t |= CG_R(t_l * pi->bsp / 20000);

sys/dev/drm/amd/amdgpu/si_dpm.c

5588

pi->pbsp : pi->bsp;

sys/dev/drm/amd/amdgpu/si_dpm.c

6780

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

6788

if (pi->voltage_control || si_pi->voltage_control_svi2)

sys/dev/drm/amd/amdgpu/si_dpm.c

6790

if (pi->mvdd_control)

sys/dev/drm/amd/amdgpu/si_dpm.c

6792

if (pi->voltage_control || si_pi->voltage_control_svi2) {

sys/dev/drm/amd/amdgpu/si_dpm.c

6804

if (pi->dynamic_ss)

sys/dev/drm/amd/amdgpu/si_dpm.c

6806

if (pi->thermal_protection)

sys/dev/drm/amd/amdgpu/si_dpm.c

6913

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

6921

if (pi->thermal_protection)

sys/dev/drm/amd/amdgpu/si_dpm.c

7133

struct rv7xx_power_info *pi = rv770_get_pi(adev);

sys/dev/drm/amd/amdgpu/si_dpm.c

7163

pi->acpi_vddc = pl->vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

7179

if (pi->min_vddc_in_table > pl->vddc)

sys/dev/drm/amd/amdgpu/si_dpm.c

7180

pi->min_vddc_in_table = pl->vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

7182

if (pi->max_vddc_in_table < pl->vddc)

sys/dev/drm/amd/amdgpu/si_dpm.c

7183

pi->max_vddc_in_table = pl->vddc;

sys/dev/drm/amd/amdgpu/si_dpm.c

7304

struct rv7xx_power_info *pi;

sys/dev/drm/amd/amdgpu/si_dpm.c

7317

pi = &eg_pi->rv7xx;

sys/dev/drm/amd/amdgpu/si_dpm.c

7330

pi->acpi_vddc = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

7332

pi->min_vddc_in_table = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

7333

pi->max_vddc_in_table = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

7373

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/amd/amdgpu/si_dpm.c

7375

pi->ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/amd/amdgpu/si_dpm.c

7379

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/amd/amdgpu/si_dpm.c

7381

pi->mclk_stutter_mode_threshold = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

7383

pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;

sys/dev/drm/amd/amdgpu/si_dpm.c

7384

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/amd/amdgpu/si_dpm.c

7389

pi->voltage_control =

sys/dev/drm/amd/amdgpu/si_dpm.c

7392

if (!pi->voltage_control) {

sys/dev/drm/amd/amdgpu/si_dpm.c

7401

pi->mvdd_control =

sys/dev/drm/amd/amdgpu/si_dpm.c

7419

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/amd/amdgpu/si_dpm.c

7420

pi->pasi = CYPRESS_HASI_DFLT;

sys/dev/drm/amd/amdgpu/si_dpm.c

7421

pi->vrc = SISLANDS_VRC_DFLT;

sys/dev/drm/amd/amdgpu/si_dpm.c

7423

pi->gfx_clock_gating = true;

sys/dev/drm/amd/amdgpu/si_dpm.c

7429

pi->thermal_protection = true;

sys/dev/drm/amd/amdgpu/si_dpm.c

7431

pi->thermal_protection = false;

sys/dev/drm/radeon/btc_dpm.c

1333

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

1340

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/btc_dpm.c

1359

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/btc_dpm.c

1627

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

1629

RV770_SMC_STATETABLE *table = &pi->smc_statetable;

sys/dev/drm/radeon/btc_dpm.c

1658

if (pi->mem_gddr5)

sys/dev/drm/radeon/btc_dpm.c

1682

pi->state_table_start,

sys/dev/drm/radeon/btc_dpm.c

1685

pi->sram_end);

sys/dev/drm/radeon/btc_dpm.c

1691

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

1699

pi->rlp = 10;

sys/dev/drm/radeon/btc_dpm.c

1700

pi->rmp = 100;

sys/dev/drm/radeon/btc_dpm.c

1701

pi->lhp = 100;

sys/dev/drm/radeon/btc_dpm.c

1702

pi->lmp = 10;

sys/dev/drm/radeon/btc_dpm.c

1704

pi->rlp = eg_pi->ats[idx].rlp;

sys/dev/drm/radeon/btc_dpm.c

1705

pi->rmp = eg_pi->ats[idx].rmp;

sys/dev/drm/radeon/btc_dpm.c

1706

pi->lhp = eg_pi->ats[idx].lhp;

sys/dev/drm/radeon/btc_dpm.c

1707

pi->lmp = eg_pi->ats[idx].lmp;

sys/dev/drm/radeon/btc_dpm.c

1916

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

1943

if (!pi->mem_gddr5)

sys/dev/drm/radeon/btc_dpm.c

2065

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

2068

if (pi->mclk_stutter_mode_threshold) {

sys/dev/drm/radeon/btc_dpm.c

2069

if (pi->mem_gddr5) {

sys/dev/drm/radeon/btc_dpm.c

2081

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

2083

u32 switch_limit = pi->mem_gddr5 ? 450 : 100;

sys/dev/drm/radeon/btc_dpm.c

2375

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

2380

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/btc_dpm.c

2386

if (pi->mg_clock_gating)

sys/dev/drm/radeon/btc_dpm.c

2392

if (pi->voltage_control) {

sys/dev/drm/radeon/btc_dpm.c

2401

if (pi->mvdd_control) {

sys/dev/drm/radeon/btc_dpm.c

2418

if (pi->dynamic_ss)

sys/dev/drm/radeon/btc_dpm.c

2421

if (pi->thermal_protection)

sys/dev/drm/radeon/btc_dpm.c

2433

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/btc_dpm.c

2472

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/btc_dpm.c

2475

if (pi->mg_clock_gating)

sys/dev/drm/radeon/btc_dpm.c

2492

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/btc_dpm.c

2500

if (pi->thermal_protection)

sys/dev/drm/radeon/btc_dpm.c

2503

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/btc_dpm.c

2512

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/btc_dpm.c

2515

if (pi->mg_clock_gating)

sys/dev/drm/radeon/btc_dpm.c

2551

struct rv7xx_power_info *pi;

sys/dev/drm/radeon/btc_dpm.c

2560

pi = &eg_pi->rv7xx;

sys/dev/drm/radeon/btc_dpm.c

2565

pi->acpi_vddc = 0;

sys/dev/drm/radeon/btc_dpm.c

2567

pi->min_vddc_in_table = 0;

sys/dev/drm/radeon/btc_dpm.c

2568

pi->max_vddc_in_table = 0;

sys/dev/drm/radeon/btc_dpm.c

2605

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/btc_dpm.c

2607

pi->ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2609

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/radeon/btc_dpm.c

2610

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/radeon/btc_dpm.c

2613

pi->rlp = RV770_RLP_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2614

pi->rmp = RV770_RMP_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2615

pi->lhp = RV770_LHP_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2616

pi->lmp = RV770_LMP_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2630

pi->voltage_control =

sys/dev/drm/radeon/btc_dpm.c

2633

pi->mvdd_control =

sys/dev/drm/radeon/btc_dpm.c

2641

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2642

pi->pasi = CYPRESS_HASI_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2643

pi->vrc = CYPRESS_VRC_DFLT;

sys/dev/drm/radeon/btc_dpm.c

2645

pi->power_gating = false;

sys/dev/drm/radeon/btc_dpm.c

2647

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/btc_dpm.c

2649

pi->mg_clock_gating = true;

sys/dev/drm/radeon/btc_dpm.c

2650

pi->mgcgtssm = true;

sys/dev/drm/radeon/btc_dpm.c

2654

pi->dynamic_pcie_gen2 = true;

sys/dev/drm/radeon/btc_dpm.c

2657

pi->thermal_protection = true;

sys/dev/drm/radeon/btc_dpm.c

2659

pi->thermal_protection = false;

sys/dev/drm/radeon/btc_dpm.c

2661

pi->display_gap = true;

sys/dev/drm/radeon/btc_dpm.c

2664

pi->dcodt = true;

sys/dev/drm/radeon/btc_dpm.c

2666

pi->dcodt = false;

sys/dev/drm/radeon/btc_dpm.c

2668

pi->ulps = true;

sys/dev/drm/radeon/btc_dpm.c

2689

pi->mclk_stutter_mode_threshold = 30000;

sys/dev/drm/radeon/btc_dpm.c

2691

pi->mclk_stutter_mode_threshold = 0;

sys/dev/drm/radeon/btc_dpm.c

2693

pi->sram_end = SMC_RAM_END;

sys/dev/drm/radeon/ci_dpm.c

1002

if (!pi->fan_table_start) {

sys/dev/drm/radeon/ci_dpm.c

1055

pi->fan_table_start,

sys/dev/drm/radeon/ci_dpm.c

1058

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1070

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1073

if (pi->caps_od_fuzzy_fan_control_support) {

sys/dev/drm/radeon/ci_dpm.c

1092

pi->fan_is_controlled_by_smc = true;

sys/dev/drm/radeon/ci_dpm.c

1099

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1103

pi->fan_is_controlled_by_smc = false;

sys/dev/drm/radeon/ci_dpm.c

1140

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1145

if (pi->fan_is_controlled_by_smc)

sys/dev/drm/radeon/ci_dpm.c

1185

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1188

if (pi->fan_is_controlled_by_smc)

sys/dev/drm/radeon/ci_dpm.c

1249

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1252

if (!pi->fan_ctrl_is_in_default_mode) {

sys/dev/drm/radeon/ci_dpm.c

1254

tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);

sys/dev/drm/radeon/ci_dpm.c

1258

tmp |= TMIN(pi->t_min);

sys/dev/drm/radeon/ci_dpm.c

1260

pi->fan_ctrl_is_in_default_mode = true;

sys/dev/drm/radeon/ci_dpm.c

1318

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1321

pi->soft_regs_start + reg_offset,

sys/dev/drm/radeon/ci_dpm.c

1322

value, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1329

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1332

pi->soft_regs_start + reg_offset,

sys/dev/drm/radeon/ci_dpm.c

1333

value, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1338

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1339

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/radeon/ci_dpm.c

1341

if (pi->caps_fps) {

sys/dev/drm/radeon/ci_dpm.c

1354

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1358

if (pi->caps_sclk_throttle_low_notification) {

sys/dev/drm/radeon/ci_dpm.c

1359

low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);

sys/dev/drm/radeon/ci_dpm.c

1362

pi->dpm_table_start +

sys/dev/drm/radeon/ci_dpm.c

1365

sizeof(u32), pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1374

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1379

pi->vddc_leakage.count = 0;

sys/dev/drm/radeon/ci_dpm.c

1380

pi->vddci_leakage.count = 0;

sys/dev/drm/radeon/ci_dpm.c

1388

pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;

sys/dev/drm/radeon/ci_dpm.c

1389

pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;

sys/dev/drm/radeon/ci_dpm.c

1390

pi->vddc_leakage.count++;

sys/dev/drm/radeon/ci_dpm.c

1400

pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;

sys/dev/drm/radeon/ci_dpm.c

1401

pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;

sys/dev/drm/radeon/ci_dpm.c

1402

pi->vddc_leakage.count++;

sys/dev/drm/radeon/ci_dpm.c

1405

pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;

sys/dev/drm/radeon/ci_dpm.c

1406

pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;

sys/dev/drm/radeon/ci_dpm.c

1407

pi->vddci_leakage.count++;

sys/dev/drm/radeon/ci_dpm.c

1416

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1451

if (pi->thermal_protection)

sys/dev/drm/radeon/ci_dpm.c

1467

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1470

if (!(pi->active_auto_throttle_sources & (1 << source))) {

sys/dev/drm/radeon/ci_dpm.c

1471

pi->active_auto_throttle_sources |= 1 << source;

sys/dev/drm/radeon/ci_dpm.c

1472

ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/ci_dpm.c

1475

if (pi->active_auto_throttle_sources & (1 << source)) {

sys/dev/drm/radeon/ci_dpm.c

1476

pi->active_auto_throttle_sources &= ~(1 << source);

sys/dev/drm/radeon/ci_dpm.c

1477

ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/ci_dpm.c

1490

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1493

if (!pi->need_update_smu7_dpm_table)

sys/dev/drm/radeon/ci_dpm.c

1496

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

1497

(pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {

sys/dev/drm/radeon/ci_dpm.c

1503

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

1504

(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {

sys/dev/drm/radeon/ci_dpm.c

1510

pi->need_update_smu7_dpm_table = 0;

sys/dev/drm/radeon/ci_dpm.c

1516

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1520

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1526

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1544

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1550

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1562

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1587

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1598

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1601

if (!pi->need_update_smu7_dpm_table)

sys/dev/drm/radeon/ci_dpm.c

1604

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

1605

(pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {

sys/dev/drm/radeon/ci_dpm.c

1611

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

1612

(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {

sys/dev/drm/radeon/ci_dpm.c

1623

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1636

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1668

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1680

if (pi->caps_automatic_dc_transition) {

sys/dev/drm/radeon/ci_dpm.c

1734

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1736

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1748

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1750

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1762

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1764

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

1776

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1778

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {

sys/dev/drm/radeon/ci_dpm.c

1852

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1859

&tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1863

pi->dpm_table_start = tmp;

sys/dev/drm/radeon/ci_dpm.c

1868

&tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1872

pi->soft_regs_start = tmp;

sys/dev/drm/radeon/ci_dpm.c

1877

&tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1881

pi->mc_reg_table_start = tmp;

sys/dev/drm/radeon/ci_dpm.c

1886

&tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1890

pi->fan_table_start = tmp;

sys/dev/drm/radeon/ci_dpm.c

1895

&tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

1899

pi->arb_table_start = tmp;

sys/dev/drm/radeon/ci_dpm.c

190

struct ci_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/ci_dpm.c

1906

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1908

pi->clock_registers.cg_spll_func_cntl =

sys/dev/drm/radeon/ci_dpm.c

1910

pi->clock_registers.cg_spll_func_cntl_2 =

sys/dev/drm/radeon/ci_dpm.c

1912

pi->clock_registers.cg_spll_func_cntl_3 =

sys/dev/drm/radeon/ci_dpm.c

1914

pi->clock_registers.cg_spll_func_cntl_4 =

sys/dev/drm/radeon/ci_dpm.c

1916

pi->clock_registers.cg_spll_spread_spectrum =

sys/dev/drm/radeon/ci_dpm.c

1918

pi->clock_registers.cg_spll_spread_spectrum_2 =

sys/dev/drm/radeon/ci_dpm.c

192

return pi;

sys/dev/drm/radeon/ci_dpm.c

1920

pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1921

pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1922

pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1923

pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1924

pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);

sys/dev/drm/radeon/ci_dpm.c

1925

pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);

sys/dev/drm/radeon/ci_dpm.c

1926

pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);

sys/dev/drm/radeon/ci_dpm.c

1927

pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);

sys/dev/drm/radeon/ci_dpm.c

1928

pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);

sys/dev/drm/radeon/ci_dpm.c

1933

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

1935

pi->low_sclk_interrupt_t = 0;

sys/dev/drm/radeon/ci_dpm.c

1999

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2002

if (pi->caps_sclk_ds) {

sys/dev/drm/radeon/ci_dpm.c

2010

if (pi->caps_sclk_ds) {

sys/dev/drm/radeon/ci_dpm.c

204

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2055

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2059

if (pi->caps_sclk_ss_support) {

sys/dev/drm/radeon/ci_dpm.c

2129

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

214

pi->powertune_defaults = &defaults_bonaire_xt;

sys/dev/drm/radeon/ci_dpm.c

2141

ret = ci_load_smc_ucode(rdev, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

2170

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2173

if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {

sys/dev/drm/radeon/ci_dpm.c

2176

&pi->vddc_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2179

} else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/radeon/ci_dpm.c

2182

&pi->vddc_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2187

if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)

sys/dev/drm/radeon/ci_dpm.c

2189

&pi->vddc_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2191

if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {

sys/dev/drm/radeon/ci_dpm.c

2194

&pi->vddci_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2197

} else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/radeon/ci_dpm.c

220

pi->powertune_defaults = &defaults_saturn_xt;

sys/dev/drm/radeon/ci_dpm.c

2200

&pi->vddci_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2205

if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)

sys/dev/drm/radeon/ci_dpm.c

2207

&pi->vddci_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2209

if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {

sys/dev/drm/radeon/ci_dpm.c

2212

&pi->mvdd_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2215

} else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/radeon/ci_dpm.c

2218

&pi->mvdd_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

2223

if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)

sys/dev/drm/radeon/ci_dpm.c

2225

&pi->mvdd_voltage_table);

sys/dev/drm/radeon/ci_dpm.c

224

pi->powertune_defaults = &defaults_hawaii_xt;

sys/dev/drm/radeon/ci_dpm.c

2255

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2258

table->VddcLevelCount = pi->vddc_voltage_table.count;

sys/dev/drm/radeon/ci_dpm.c

2261

&pi->vddc_voltage_table.entries[count],

sys/dev/drm/radeon/ci_dpm.c

2264

if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)

sys/dev/drm/radeon/ci_dpm.c

2266

pi->vddc_voltage_table.entries[count].smio_low;

sys/dev/drm/radeon/ci_dpm.c

2279

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

228

pi->powertune_defaults = &defaults_hawaii_pro;

sys/dev/drm/radeon/ci_dpm.c

2281

table->VddciLevelCount = pi->vddci_voltage_table.count;

sys/dev/drm/radeon/ci_dpm.c

2284

&pi->vddci_voltage_table.entries[count],

sys/dev/drm/radeon/ci_dpm.c

2287

if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)

sys/dev/drm/radeon/ci_dpm.c

2289

pi->vddci_voltage_table.entries[count].smio_low;

sys/dev/drm/radeon/ci_dpm.c

2301

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2304

table->MvddLevelCount = pi->mvdd_voltage_table.count;

sys/dev/drm/radeon/ci_dpm.c

2307

&pi->mvdd_voltage_table.entries[count],

sys/dev/drm/radeon/ci_dpm.c

2310

if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)

sys/dev/drm/radeon/ci_dpm.c

2312

pi->mvdd_voltage_table.entries[count].smio_low;

sys/dev/drm/radeon/ci_dpm.c

2344

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2347

if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

sys/dev/drm/radeon/ci_dpm.c

2350

voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;

sys/dev/drm/radeon/ci_dpm.c

238

pi->powertune_defaults = &defaults_bonaire_xt;

sys/dev/drm/radeon/ci_dpm.c

242

pi->dte_tj_offset = 0;

sys/dev/drm/radeon/ci_dpm.c

244

pi->caps_power_containment = true;

sys/dev/drm/radeon/ci_dpm.c

2449

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

245

pi->caps_cac = false;

sys/dev/drm/radeon/ci_dpm.c

2453

ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,

sys/dev/drm/radeon/ci_dpm.c

2454

&tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

246

pi->caps_sq_ramping = false;

sys/dev/drm/radeon/ci_dpm.c

2461

return ci_write_smc_sram_dword(rdev, pi->arb_table_start,

sys/dev/drm/radeon/ci_dpm.c

2462

tmp, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

247

pi->caps_db_ramping = false;

sys/dev/drm/radeon/ci_dpm.c

248

pi->caps_td_ramping = false;

sys/dev/drm/radeon/ci_dpm.c

249

pi->caps_tcp_ramping = false;

sys/dev/drm/radeon/ci_dpm.c

251

if (pi->caps_power_containment) {

sys/dev/drm/radeon/ci_dpm.c

252

pi->caps_cac = true;

sys/dev/drm/radeon/ci_dpm.c

254

pi->enable_bapm_feature = false;

sys/dev/drm/radeon/ci_dpm.c

256

pi->enable_bapm_feature = true;

sys/dev/drm/radeon/ci_dpm.c

257

pi->enable_tdc_limit_feature = true;

sys/dev/drm/radeon/ci_dpm.c

258

pi->enable_pkg_pwr_tracking_feature = true;

sys/dev/drm/radeon/ci_dpm.c

2582

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2589

for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {

sys/dev/drm/radeon/ci_dpm.c

2590

for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {

sys/dev/drm/radeon/ci_dpm.c

2592

pi->dpm_table.sclk_table.dpm_levels[i].value,

sys/dev/drm/radeon/ci_dpm.c

2593

pi->dpm_table.mclk_table.dpm_levels[j].value,

sys/dev/drm/radeon/ci_dpm.c

2602

pi->arb_table_start,

sys/dev/drm/radeon/ci_dpm.c

2605

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

2612

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2614

if (pi->need_update_smu7_dpm_table == 0)

sys/dev/drm/radeon/ci_dpm.c

2624

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2630

pi->smc_state_table.GraphicsBootLevel = level;

sys/dev/drm/radeon/ci_dpm.c

2638

pi->smc_state_table.MemoryBootLevel = level;

sys/dev/drm/radeon/ci_dpm.c

2663

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2664

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/radeon/ci_dpm.c

2677

pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;

sys/dev/drm/radeon/ci_dpm.c

2678

pi->dpm_level_enable_mask.pcie_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

269

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

270

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/radeon/ci_dpm.c

271

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/radeon/ci_dpm.c

272

u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;

sys/dev/drm/radeon/ci_dpm.c

2828

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2829

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/ci_dpm.c

2830

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ci_dpm.c

2831

u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

2832

u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

2833

u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

2834

u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;

sys/dev/drm/radeon/ci_dpm.c

2835

u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.c

2836

u32 mpll_ss1 = pi->clock_registers.mpll_ss1;

sys/dev/drm/radeon/ci_dpm.c

2837

u32 mpll_ss2 = pi->clock_registers.mpll_ss2;

sys/dev/drm/radeon/ci_dpm.c

2855

if (pi->mem_gddr5) {

sys/dev/drm/radeon/ci_dpm.c

2861

if (pi->caps_mclk_ss_support) {

sys/dev/drm/radeon/ci_dpm.c

2913

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2943

if (pi->vddc_phase_shed_control)

sys/dev/drm/radeon/ci_dpm.c

2953

memory_level->ActivityLevel = (u16)pi->mclk_activity_target;

sys/dev/drm/radeon/ci_dpm.c

2963

if (pi->mclk_stutter_mode_threshold &&

sys/dev/drm/radeon/ci_dpm.c

2964

(memory_clock <= pi->mclk_stutter_mode_threshold) &&

sys/dev/drm/radeon/ci_dpm.c

2965

(pi->uvd_enabled == false) &&

sys/dev/drm/radeon/ci_dpm.c

2970

if (pi->mclk_strobe_mode_threshold &&

sys/dev/drm/radeon/ci_dpm.c

2971

(memory_clock <= pi->mclk_strobe_mode_threshold))

sys/dev/drm/radeon/ci_dpm.c

2974

if (pi->mem_gddr5) {

sys/dev/drm/radeon/ci_dpm.c

2977

if (pi->mclk_edc_enable_threshold &&

sys/dev/drm/radeon/ci_dpm.c

2978

(memory_clock > pi->mclk_edc_enable_threshold))

sys/dev/drm/radeon/ci_dpm.c

298

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

2981

if (pi->mclk_edc_wr_enable_threshold &&

sys/dev/drm/radeon/ci_dpm.c

2982

(memory_clock > pi->mclk_edc_wr_enable_threshold))

sys/dev/drm/radeon/ci_dpm.c

299

u8 *vid = pi->smc_powertune_table.VddCVid;

sys/dev/drm/radeon/ci_dpm.c

2992

dll_state_on = pi->dll_default_on;

sys/dev/drm/radeon/ci_dpm.c

302

if (pi->vddc_voltage_table.count > 8)

sys/dev/drm/radeon/ci_dpm.c

3026

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3029

u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;

sys/dev/drm/radeon/ci_dpm.c

3030

u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;

sys/dev/drm/radeon/ci_dpm.c

3031

u32 dll_cntl = pi->clock_registers.dll_cntl;

sys/dev/drm/radeon/ci_dpm.c

3032

u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/ci_dpm.c

3037

if (pi->acpi_vddc)

sys/dev/drm/radeon/ci_dpm.c

3038

table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3040

table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3042

table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/radeon/ci_dpm.c

305

for (i = 0; i < pi->vddc_voltage_table.count; i++)

sys/dev/drm/radeon/ci_dpm.c

306

vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);

sys/dev/drm/radeon/ci_dpm.c

3064

table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/ci_dpm.c

3065

table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/ci_dpm.c

3066

table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/radeon/ci_dpm.c

3067

table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ci_dpm.c

3086

if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

sys/dev/drm/radeon/ci_dpm.c

3087

if (pi->acpi_vddci)

sys/dev/drm/radeon/ci_dpm.c

3089

cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3092

cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);

sys/dev/drm/radeon/ci_dpm.c

3109

cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);

sys/dev/drm/radeon/ci_dpm.c

3111

cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);

sys/dev/drm/radeon/ci_dpm.c

3113

cpu_to_be32(pi->clock_registers.mpll_func_cntl);

sys/dev/drm/radeon/ci_dpm.c

3115

cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);

sys/dev/drm/radeon/ci_dpm.c

3117

cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);

sys/dev/drm/radeon/ci_dpm.c

3118

table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);

sys/dev/drm/radeon/ci_dpm.c

3119

table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);

sys/dev/drm/radeon/ci_dpm.c

3127

cpu_to_be16((u16)pi->mclk_activity_target);

sys/dev/drm/radeon/ci_dpm.c

313

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

314

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/radeon/ci_dpm.c

3141

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3142

struct ci_ulv_parm *ulv = &pi->ulv;

sys/dev/drm/radeon/ci_dpm.c

3159

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

316

pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;

sys/dev/drm/radeon/ci_dpm.c

3166

pi->ulv.supported = false;

sys/dev/drm/radeon/ci_dpm.c

317

pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;

sys/dev/drm/radeon/ci_dpm.c

3170

if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {

sys/dev/drm/radeon/ci_dpm.c

318

pi->smc_powertune_table.SviLoadLineTrimVddC = 3;

sys/dev/drm/radeon/ci_dpm.c

3184

state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;

sys/dev/drm/radeon/ci_dpm.c

319

pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;

sys/dev/drm/radeon/ci_dpm.c

3197

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3199

u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;

sys/dev/drm/radeon/ci_dpm.c

3200

u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;

sys/dev/drm/radeon/ci_dpm.c

3201

u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;

sys/dev/drm/radeon/ci_dpm.c

3202

u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/ci_dpm.c

3221

if (pi->caps_sclk_ss_support) {

sys/dev/drm/radeon/ci_dpm.c

3254

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

326

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

327

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/radeon/ci_dpm.c

3272

if (pi->vddc_phase_shed_control)

sys/dev/drm/radeon/ci_dpm.c

3288

if (pi->caps_sclk_ds)

sys/dev/drm/radeon/ci_dpm.c

331

pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);

sys/dev/drm/radeon/ci_dpm.c

3312

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3313

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/radeon/ci_dpm.c

3314

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/radeon/ci_dpm.c

3318

SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;

sys/dev/drm/radeon/ci_dpm.c

332

pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =

sys/dev/drm/radeon/ci_dpm.c

3326

(u16)pi->activity_target[i],

sys/dev/drm/radeon/ci_dpm.c

3327

&pi->smc_state_table.GraphicsLevel[i]);

sys/dev/drm/radeon/ci_dpm.c

3331

pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;

sys/dev/drm/radeon/ci_dpm.c

3333

pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =

sys/dev/drm/radeon/ci_dpm.c

3336

pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;

sys/dev/drm/radeon/ci_dpm.c

3338

pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;

sys/dev/drm/radeon/ci_dpm.c

3339

pi->dpm_level_enable_mask.sclk_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

334

pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;

sys/dev/drm/radeon/ci_dpm.c

3344

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

3359

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3360

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/radeon/ci_dpm.c

3361

u32 level_array_address = pi->dpm_table_start +

sys/dev/drm/radeon/ci_dpm.c

3365

SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;

sys/dev/drm/radeon/ci_dpm.c

3375

&pi->smc_state_table.MemoryLevel[i]);

sys/dev/drm/radeon/ci_dpm.c

3380

pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;

sys/dev/drm/radeon/ci_dpm.c

3384

pi->smc_state_table.MemoryLevel[1].MinVddc =

sys/dev/drm/radeon/ci_dpm.c

3385

pi->smc_state_table.MemoryLevel[0].MinVddc;

sys/dev/drm/radeon/ci_dpm.c

3386

pi->smc_state_table.MemoryLevel[1].MinVddcPhases =

sys/dev/drm/radeon/ci_dpm.c

3387

pi->smc_state_table.MemoryLevel[0].MinVddcPhases;

sys/dev/drm/radeon/ci_dpm.c

3390

pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);

sys/dev/drm/radeon/ci_dpm.c

3392

pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;

sys/dev/drm/radeon/ci_dpm.c

3393

pi->dpm_level_enable_mask.mclk_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

3396

pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =

sys/dev/drm/radeon/ci_dpm.c

3401

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

341

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

342

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/radeon/ci_dpm.c

3429

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3431

if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)

sys/dev/drm/radeon/ci_dpm.c

3434

if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {

sys/dev/drm/radeon/ci_dpm.c

3435

pi->pcie_gen_powersaving = pi->pcie_gen_performance;

sys/dev/drm/radeon/ci_dpm.c

3436

pi->pcie_lane_powersaving = pi->pcie_lane_performance;

sys/dev/drm/radeon/ci_dpm.c

3437

} else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {

sys/dev/drm/radeon/ci_dpm.c

3438

pi->pcie_gen_performance = pi->pcie_gen_powersaving;

sys/dev/drm/radeon/ci_dpm.c

3439

pi->pcie_lane_performance = pi->pcie_lane_powersaving;

sys/dev/drm/radeon/ci_dpm.c

3443

&pi->dpm_table.pcie_speed_table,

sys/dev/drm/radeon/ci_dpm.c

3447

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,

sys/dev/drm/radeon/ci_dpm.c

3448

pi->pcie_gen_powersaving.min,

sys/dev/drm/radeon/ci_dpm.c

3449

pi->pcie_lane_powersaving.max);

sys/dev/drm/radeon/ci_dpm.c

3451

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,

sys/dev/drm/radeon/ci_dpm.c

3452

pi->pcie_gen_powersaving.min,

sys/dev/drm/radeon/ci_dpm.c

3453

pi->pcie_lane_powersaving.min);

sys/dev/drm/radeon/ci_dpm.c

3454

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,

sys/dev/drm/radeon/ci_dpm.c

3455

pi->pcie_gen_performance.min,

sys/dev/drm/radeon/ci_dpm.c

3456

pi->pcie_lane_performance.min);

sys/dev/drm/radeon/ci_dpm.c

3457

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,

sys/dev/drm/radeon/ci_dpm.c

3458

pi->pcie_gen_powersaving.min,

sys/dev/drm/radeon/ci_dpm.c

3459

pi->pcie_lane_powersaving.max);

sys/dev/drm/radeon/ci_dpm.c

3460

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,

sys/dev/drm/radeon/ci_dpm.c

3461

pi->pcie_gen_performance.min,

sys/dev/drm/radeon/ci_dpm.c

3462

pi->pcie_lane_performance.max);

sys/dev/drm/radeon/ci_dpm.c

3463

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,

sys/dev/drm/radeon/ci_dpm.c

3464

pi->pcie_gen_powersaving.max,

sys/dev/drm/radeon/ci_dpm.c

3465

pi->pcie_lane_powersaving.max);

sys/dev/drm/radeon/ci_dpm.c

3466

ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,

sys/dev/drm/radeon/ci_dpm.c

3467

pi->pcie_gen_performance.max,

sys/dev/drm/radeon/ci_dpm.c

3468

pi->pcie_lane_performance.max);

sys/dev/drm/radeon/ci_dpm.c

3470

pi->dpm_table.pcie_speed_table.count = 6;

sys/dev/drm/radeon/ci_dpm.c

3477

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

349

(u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,

sys/dev/drm/radeon/ci_dpm.c

3495

memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));

sys/dev/drm/radeon/ci_dpm.c

3498

&pi->dpm_table.sclk_table,

sys/dev/drm/radeon/ci_dpm.c

350

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

3501

&pi->dpm_table.mclk_table,

sys/dev/drm/radeon/ci_dpm.c

3504

&pi->dpm_table.vddc_table,

sys/dev/drm/radeon/ci_dpm.c

3507

&pi->dpm_table.vddci_table,

sys/dev/drm/radeon/ci_dpm.c

3510

&pi->dpm_table.mvdd_table,

sys/dev/drm/radeon/ci_dpm.c

3513

pi->dpm_table.sclk_table.count = 0;

sys/dev/drm/radeon/ci_dpm.c

3516

(pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=

sys/dev/drm/radeon/ci_dpm.c

3518

pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =

sys/dev/drm/radeon/ci_dpm.c

3520

pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =

sys/dev/drm/radeon/ci_dpm.c

3522

pi->dpm_table.sclk_table.count++;

sys/dev/drm/radeon/ci_dpm.c

3526

pi->dpm_table.mclk_table.count = 0;

sys/dev/drm/radeon/ci_dpm.c

3529

(pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=

sys/dev/drm/radeon/ci_dpm.c

3531

pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =

sys/dev/drm/radeon/ci_dpm.c

3533

pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =

sys/dev/drm/radeon/ci_dpm.c

3535

pi->dpm_table.mclk_table.count++;

sys/dev/drm/radeon/ci_dpm.c

354

pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;

sys/dev/drm/radeon/ci_dpm.c

3540

pi->dpm_table.vddc_table.dpm_levels[i].value =

sys/dev/drm/radeon/ci_dpm.c

3542

pi->dpm_table.vddc_table.dpm_levels[i].param1 =

sys/dev/drm/radeon/ci_dpm.c

3544

pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;

sys/dev/drm/radeon/ci_dpm.c

3546

pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;

sys/dev/drm/radeon/ci_dpm.c

3551

pi->dpm_table.vddci_table.dpm_levels[i].value =

sys/dev/drm/radeon/ci_dpm.c

3553

pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;

sys/dev/drm/radeon/ci_dpm.c

3555

pi->dpm_table.vddci_table.count = allowed_mclk_table->count;

sys/dev/drm/radeon/ci_dpm.c

3561

pi->dpm_table.mvdd_table.dpm_levels[i].value =

sys/dev/drm/radeon/ci_dpm.c

3563

pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;

sys/dev/drm/radeon/ci_dpm.c

3565

pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;

sys/dev/drm/radeon/ci_dpm.c

3591

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3592

struct ci_ulv_parm *ulv = &pi->ulv;

sys/dev/drm/radeon/ci_dpm.c

3594

SMU7_Discrete_DpmTable *table = &pi->smc_state_table;

sys/dev/drm/radeon/ci_dpm.c

3601

if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)

sys/dev/drm/radeon/ci_dpm.c

361

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3612

if (pi->mem_gddr5)

sys/dev/drm/radeon/ci_dpm.c

3616

ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);

sys/dev/drm/radeon/ci_dpm.c

3663

ret = ci_find_boot_level(&pi->dpm_table.sclk_table,

sys/dev/drm/radeon/ci_dpm.c

3664

pi->vbios_boot_state.sclk_bootup_value,

sys/dev/drm/radeon/ci_dpm.c

3665

(u32 *)&pi->smc_state_table.GraphicsBootLevel);

sys/dev/drm/radeon/ci_dpm.c

3667

ret = ci_find_boot_level(&pi->dpm_table.mclk_table,

sys/dev/drm/radeon/ci_dpm.c

3668

pi->vbios_boot_state.mclk_bootup_value,

sys/dev/drm/radeon/ci_dpm.c

3669

(u32 *)&pi->smc_state_table.MemoryBootLevel);

sys/dev/drm/radeon/ci_dpm.c

3671

table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

3672

table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

3673

table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

368

pi->smc_powertune_table.FuzzyFan_PwmSetDelta =

sys/dev/drm/radeon/ci_dpm.c

3690

table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *

sys/dev/drm/radeon/ci_dpm.c

3692

table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *

sys/dev/drm/radeon/ci_dpm.c

3700

table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;

sys/dev/drm/radeon/ci_dpm.c

3702

if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)

sys/dev/drm/radeon/ci_dpm.c

3726

pi->dpm_table_start +

sys/dev/drm/radeon/ci_dpm.c

3730

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

3756

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3757

struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;

sys/dev/drm/radeon/ci_dpm.c

376

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

377

u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;

sys/dev/drm/radeon/ci_dpm.c

378

u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;

sys/dev/drm/radeon/ci_dpm.c

3787

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3799

&pi->dpm_table.sclk_table,

sys/dev/drm/radeon/ci_dpm.c

3804

&pi->dpm_table.mclk_table,

sys/dev/drm/radeon/ci_dpm.c

3851

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3856

if (!pi->sclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

3857

if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

3860

pi->dpm_level_enable_mask.sclk_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

3866

if (!pi->mclk_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

3867

if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

3870

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

3876

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

3877

if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

3880

pi->dpm_level_enable_mask.pcie_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

3892

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3894

struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;

sys/dev/drm/radeon/ci_dpm.c

3896

struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;

sys/dev/drm/radeon/ci_dpm.c

3900

pi->need_update_smu7_dpm_table = 0;

sys/dev/drm/radeon/ci_dpm.c

3908

pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;

sys/dev/drm/radeon/ci_dpm.c

3915

pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;

sys/dev/drm/radeon/ci_dpm.c

3924

pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;

sys/dev/drm/radeon/ci_dpm.c

3928

pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;

sys/dev/drm/radeon/ci_dpm.c

3934

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3938

struct ci_dpm_table *dpm_table = &pi->dpm_table;

sys/dev/drm/radeon/ci_dpm.c

3941

if (!pi->need_update_smu7_dpm_table)

sys/dev/drm/radeon/ci_dpm.c

3944

if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)

sys/dev/drm/radeon/ci_dpm.c

3947

if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)

sys/dev/drm/radeon/ci_dpm.c

3950

if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {

sys/dev/drm/radeon/ci_dpm.c

3956

if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {

sys/dev/drm/radeon/ci_dpm.c

3967

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

3977

pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;

sys/dev/drm/radeon/ci_dpm.c

3981

pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;

sys/dev/drm/radeon/ci_dpm.c

3983

if (!pi->caps_uvd_dpm)

sys/dev/drm/radeon/ci_dpm.c

3990

pi->dpm_level_enable_mask.uvd_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

3992

if (pi->last_mclk_dpm_enable_mask & 0x1) {

sys/dev/drm/radeon/ci_dpm.c

3993

pi->uvd_enabled = true;

sys/dev/drm/radeon/ci_dpm.c

3994

pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;

sys/dev/drm/radeon/ci_dpm.c

3997

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

400

pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;

sys/dev/drm/radeon/ci_dpm.c

4000

if (pi->last_mclk_dpm_enable_mask & 0x1) {

sys/dev/drm/radeon/ci_dpm.c

4001

pi->uvd_enabled = false;

sys/dev/drm/radeon/ci_dpm.c

4002

pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;

sys/dev/drm/radeon/ci_dpm.c

4005

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

401

pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;

sys/dev/drm/radeon/ci_dpm.c

4016

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4026

pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;

sys/dev/drm/radeon/ci_dpm.c

4029

pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;

sys/dev/drm/radeon/ci_dpm.c

4031

if (!pi->caps_vce_dpm)

sys/dev/drm/radeon/ci_dpm.c

4038

pi->dpm_level_enable_mask.vce_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

4049

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4059

pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;

sys/dev/drm/radeon/ci_dpm.c

4062

pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;

sys/dev/drm/radeon/ci_dpm.c

4064

if (!pi->caps_samu_dpm)

sys/dev/drm/radeon/ci_dpm.c

4071

pi->dpm_level_enable_mask.samu_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

408

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4080

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

409

u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;

sys/dev/drm/radeon/ci_dpm.c

4090

pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;

sys/dev/drm/radeon/ci_dpm.c

4093

pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;

sys/dev/drm/radeon/ci_dpm.c

4095

if (!pi->caps_acp_dpm)

sys/dev/drm/radeon/ci_dpm.c

410

u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;

sys/dev/drm/radeon/ci_dpm.c

4102

pi->dpm_level_enable_mask.acp_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

4113

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4117

if (pi->caps_uvd_dpm ||

sys/dev/drm/radeon/ci_dpm.c

4119

pi->smc_state_table.UvdBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

4121

pi->smc_state_table.UvdBootLevel =

sys/dev/drm/radeon/ci_dpm.c

4126

tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);

sys/dev/drm/radeon/ci_dpm.c

4152

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4161

pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);

sys/dev/drm/radeon/ci_dpm.c

4164

tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);

sys/dev/drm/radeon/ci_dpm.c

417

pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);

sys/dev/drm/radeon/ci_dpm.c

418

pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);

sys/dev/drm/radeon/ci_dpm.c

4186

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4190

pi->smc_state_table.AcpBootLevel = 0;

sys/dev/drm/radeon/ci_dpm.c

4194

tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);

sys/dev/drm/radeon/ci_dpm.c

4205

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4212

pi->dpm_level_enable_mask.sclk_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

4213

ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);

sys/dev/drm/radeon/ci_dpm.c

4214

pi->dpm_level_enable_mask.mclk_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

4215

ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);

sys/dev/drm/radeon/ci_dpm.c

4216

pi->last_mclk_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

4217

pi->dpm_level_enable_mask.mclk_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.c

4218

if (pi->uvd_enabled) {

sys/dev/drm/radeon/ci_dpm.c

4219

if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)

sys/dev/drm/radeon/ci_dpm.c

4220

pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;

sys/dev/drm/radeon/ci_dpm.c

4222

pi->dpm_level_enable_mask.pcie_dpm_enable_mask =

sys/dev/drm/radeon/ci_dpm.c

4223

ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);

sys/dev/drm/radeon/ci_dpm.c

4243

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4248

if ((!pi->pcie_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

4249

pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

425

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4251

tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.c

426

const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;

sys/dev/drm/radeon/ci_dpm.c

4267

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

4268

pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

427

SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;

sys/dev/drm/radeon/ci_dpm.c

4270

tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.c

4286

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

4287

pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

4289

tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;

sys/dev/drm/radeon/ci_dpm.c

4306

if ((!pi->sclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

4307

pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

4309

pi->dpm_level_enable_mask.sclk_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

4321

if ((!pi->mclk_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

4322

pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

4324

pi->dpm_level_enable_mask.mclk_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

4336

if ((!pi->pcie_dpm_key_disabled) &&

sys/dev/drm/radeon/ci_dpm.c

4337

pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {

sys/dev/drm/radeon/ci_dpm.c

4339

pi->dpm_level_enable_mask.pcie_dpm_enable_mask);

sys/dev/drm/radeon/ci_dpm.c

4352

if (!pi->pcie_dpm_key_disabled) {

sys/dev/drm/radeon/ci_dpm.c

4373

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

438

dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;

sys/dev/drm/radeon/ci_dpm.c

4399

if (!pi->mem_gddr5)

sys/dev/drm/radeon/ci_dpm.c

440

(u8)(pi->thermal_temp_setting.temperature_high / 1000);

sys/dev/drm/radeon/ci_dpm.c

4406

if (!pi->mem_gddr5) {

sys/dev/drm/radeon/ci_dpm.c

4660

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4662

struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;

sys/dev/drm/radeon/ci_dpm.c

4720

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4723

for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {

sys/dev/drm/radeon/ci_dpm.c

4724

if (pi->mc_reg_table.valid_flag & (1 << j)) {

sys/dev/drm/radeon/ci_dpm.c

4727

mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);

sys/dev/drm/radeon/ci_dpm.c

4728

mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);

sys/dev/drm/radeon/ci_dpm.c

473

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4756

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4759

for(i = 0; i < pi->mc_reg_table.num_entries; i++) {

sys/dev/drm/radeon/ci_dpm.c

4760

if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)

sys/dev/drm/radeon/ci_dpm.c

4764

if ((i == pi->mc_reg_table.num_entries) && (i > 0))

sys/dev/drm/radeon/ci_dpm.c

4767

ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],

sys/dev/drm/radeon/ci_dpm.c

4768

mc_reg_table_data, pi->mc_reg_table.last,

sys/dev/drm/radeon/ci_dpm.c

4769

pi->mc_reg_table.valid_flag);

sys/dev/drm/radeon/ci_dpm.c

477

if (pi->caps_power_containment) {

sys/dev/drm/radeon/ci_dpm.c

4775

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4778

for (i = 0; i < pi->dpm_table.mclk_table.count; i++)

sys/dev/drm/radeon/ci_dpm.c

4780

pi->dpm_table.mclk_table.dpm_levels[i].value,

sys/dev/drm/radeon/ci_dpm.c

4786

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4789

memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));

sys/dev/drm/radeon/ci_dpm.c

4791

ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);

sys/dev/drm/radeon/ci_dpm.c

4794

ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);

sys/dev/drm/radeon/ci_dpm.c

4797

pi->mc_reg_table_start,

sys/dev/drm/radeon/ci_dpm.c

4798

(u8 *)&pi->smc_mc_reg_table,

sys/dev/drm/radeon/ci_dpm.c

4800

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

4805

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4807

if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))

sys/dev/drm/radeon/ci_dpm.c

481

&pm_fuse_table_offset, pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

4810

memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));

sys/dev/drm/radeon/ci_dpm.c

4812

ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);

sys/dev/drm/radeon/ci_dpm.c

4815

pi->mc_reg_table_start +

sys/dev/drm/radeon/ci_dpm.c

4817

(u8 *)&pi->smc_mc_reg_table.data[0],

sys/dev/drm/radeon/ci_dpm.c

4819

pi->dpm_table.mclk_table.count,

sys/dev/drm/radeon/ci_dpm.c

4820

pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

4887

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4892

if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)

sys/dev/drm/radeon/ci_dpm.c

4895

current_link_speed = pi->force_pcie_gen;

sys/dev/drm/radeon/ci_dpm.c

4897

pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;

sys/dev/drm/radeon/ci_dpm.c

4898

pi->pspp_notify_required = false;

sys/dev/drm/radeon/ci_dpm.c

4905

pi->force_pcie_gen = RADEON_PCIE_GEN2;

sys/dev/drm/radeon/ci_dpm.c

4913

pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);

sys/dev/drm/radeon/ci_dpm.c

4918

pi->pspp_notify_required = true;

sys/dev/drm/radeon/ci_dpm.c

4926

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4931

if (pi->pspp_notify_required) {

sys/dev/drm/radeon/ci_dpm.c

4951

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4972

pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;

sys/dev/drm/radeon/ci_dpm.c

4973

pi->max_vddc_in_pp_table =

sys/dev/drm/radeon/ci_dpm.c

4976

pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;

sys/dev/drm/radeon/ci_dpm.c

4977

pi->max_vddci_in_pp_table =

sys/dev/drm/radeon/ci_dpm.c

4994

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

4995

struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;

sys/dev/drm/radeon/ci_dpm.c

5008

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5009

struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;

sys/dev/drm/radeon/ci_dpm.c

509

(u8 *)&pi->smc_powertune_table,

sys/dev/drm/radeon/ci_dpm.c

510

sizeof(SMU7_Discrete_PmFuses), pi->sram_end);

sys/dev/drm/radeon/ci_dpm.c

5127

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5134

pi->mem_gddr5 = true;

sys/dev/drm/radeon/ci_dpm.c

5136

pi->mem_gddr5 = false;

sys/dev/drm/radeon/ci_dpm.c

5144

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5146

pi->current_rps = *rps;

sys/dev/drm/radeon/ci_dpm.c

5147

pi->current_ps = *new_ps;

sys/dev/drm/radeon/ci_dpm.c

5148

pi->current_rps.ps_priv = &pi->current_ps;

sys/dev/drm/radeon/ci_dpm.c

5155

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5157

pi->requested_rps = *rps;

sys/dev/drm/radeon/ci_dpm.c

5158

pi->requested_ps = *new_ps;

sys/dev/drm/radeon/ci_dpm.c

5159

pi->requested_rps.ps_priv = &pi->requested_ps;

sys/dev/drm/radeon/ci_dpm.c

5164

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5170

ci_apply_state_adjust_rules(rdev, &pi->requested_rps);

sys/dev/drm/radeon/ci_dpm.c

5177

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5178

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/ci_dpm.c

5199

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

520

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5205

if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {

sys/dev/drm/radeon/ci_dpm.c

5213

if (pi->caps_dynamic_ac_timing) {

sys/dev/drm/radeon/ci_dpm.c

5216

pi->caps_dynamic_ac_timing = false;

sys/dev/drm/radeon/ci_dpm.c

5218

if (pi->dynamic_ss)

sys/dev/drm/radeon/ci_dpm.c

5220

if (pi->thermal_protection)

sys/dev/drm/radeon/ci_dpm.c

523

if (pi->caps_sq_ramping) {

sys/dev/drm/radeon/ci_dpm.c

5250

if (pi->caps_dynamic_ac_timing) {

sys/dev/drm/radeon/ci_dpm.c

532

if (pi->caps_db_ramping) {

sys/dev/drm/radeon/ci_dpm.c

5354

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5364

if (pi->thermal_protection)

sys/dev/drm/radeon/ci_dpm.c

5385

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5386

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/ci_dpm.c

5387

struct radeon_ps *old_ps = &pi->current_rps;

sys/dev/drm/radeon/ci_dpm.c

5391

if (pi->pcie_performance_request)

sys/dev/drm/radeon/ci_dpm.c

541

if (pi->caps_td_ramping) {

sys/dev/drm/radeon/ci_dpm.c

5420

if (pi->caps_dynamic_ac_timing) {

sys/dev/drm/radeon/ci_dpm.c

5442

if (pi->pcie_performance_request)

sys/dev/drm/radeon/ci_dpm.c

550

if (pi->caps_tcp_ramping) {

sys/dev/drm/radeon/ci_dpm.c

5510

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5522

pi->sys_pcie_mask,

sys/dev/drm/radeon/ci_dpm.c

5523

pi->vbios_boot_state.pcie_gen_bootup_value,

sys/dev/drm/radeon/ci_dpm.c

5526

pi->vbios_boot_state.pcie_lane_bootup_value,

sys/dev/drm/radeon/ci_dpm.c

5530

pi->acpi_pcie_gen = pl->pcie_gen;

sys/dev/drm/radeon/ci_dpm.c

5534

pi->ulv.supported = true;

sys/dev/drm/radeon/ci_dpm.c

5535

pi->ulv.pl = *pl;

sys/dev/drm/radeon/ci_dpm.c

5536

pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5541

pl->mclk = pi->vbios_boot_state.mclk_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

5542

pl->sclk = pi->vbios_boot_state.sclk_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

5543

pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

5544

pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;

sys/dev/drm/radeon/ci_dpm.c

5549

pi->use_pcie_powersaving_levels = true;

sys/dev/drm/radeon/ci_dpm.c

5550

if (pi->pcie_gen_powersaving.max < pl->pcie_gen)

sys/dev/drm/radeon/ci_dpm.c

5551

pi->pcie_gen_powersaving.max = pl->pcie_gen;

sys/dev/drm/radeon/ci_dpm.c

5552

if (pi->pcie_gen_powersaving.min > pl->pcie_gen)

sys/dev/drm/radeon/ci_dpm.c

5553

pi->pcie_gen_powersaving.min = pl->pcie_gen;

sys/dev/drm/radeon/ci_dpm.c

5554

if (pi->pcie_lane_powersaving.max < pl->pcie_lane)

sys/dev/drm/radeon/ci_dpm.c

5555

pi->pcie_lane_powersaving.max = pl->pcie_lane;

sys/dev/drm/radeon/ci_dpm.c

5556

if (pi->pcie_lane_powersaving.min > pl->pcie_lane)

sys/dev/drm/radeon/ci_dpm.c

5557

pi->pcie_lane_powersaving.min = pl->pcie_lane;

sys/dev/drm/radeon/ci_dpm.c

5560

pi->use_pcie_performance_levels = true;

sys/dev/drm/radeon/ci_dpm.c

5561

if (pi->pcie_gen_performance.max < pl->pcie_gen)

sys/dev/drm/radeon/ci_dpm.c

5562

pi->pcie_gen_performance.max = pl->pcie_gen;

sys/dev/drm/radeon/ci_dpm.c

5563

if (pi->pcie_gen_performance.min > pl->pcie_gen)

sys/dev/drm/radeon/ci_dpm.c

5564

pi->pcie_gen_performance.min = pl->pcie_gen;

sys/dev/drm/radeon/ci_dpm.c

5565

if (pi->pcie_lane_performance.max < pl->pcie_lane)

sys/dev/drm/radeon/ci_dpm.c

5566

pi->pcie_lane_performance.max = pl->pcie_lane;

sys/dev/drm/radeon/ci_dpm.c

5567

if (pi->pcie_lane_performance.min > pl->pcie_lane)

sys/dev/drm/radeon/ci_dpm.c

5568

pi->pcie_lane_performance.min = pl->pcie_lane;

sys/dev/drm/radeon/ci_dpm.c

5723

struct ci_power_info *pi;

sys/dev/drm/radeon/ci_dpm.c

5728

pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);

sys/dev/drm/radeon/ci_dpm.c

5729

if (pi == NULL)

sys/dev/drm/radeon/ci_dpm.c

5731

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/ci_dpm.c

5738

pi->sys_pcie_mask = 0;

sys/dev/drm/radeon/ci_dpm.c

5741

pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |

sys/dev/drm/radeon/ci_dpm.c

5745

pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 |

sys/dev/drm/radeon/ci_dpm.c

5748

pi->sys_pcie_mask = RADEON_PCIE_SPEED_25;

sys/dev/drm/radeon/ci_dpm.c

5750

pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;

sys/dev/drm/radeon/ci_dpm.c

5752

pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;

sys/dev/drm/radeon/ci_dpm.c

5753

pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;

sys/dev/drm/radeon/ci_dpm.c

5754

pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;

sys/dev/drm/radeon/ci_dpm.c

5755

pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;

sys/dev/drm/radeon/ci_dpm.c

5757

pi->pcie_lane_performance.max = 0;

sys/dev/drm/radeon/ci_dpm.c

5758

pi->pcie_lane_performance.min = 16;

sys/dev/drm/radeon/ci_dpm.c

5759

pi->pcie_lane_powersaving.max = 0;

sys/dev/drm/radeon/ci_dpm.c

5760

pi->pcie_lane_powersaving.min = 16;

sys/dev/drm/radeon/ci_dpm.c

5762

ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);

sys/dev/drm/radeon/ci_dpm.c

5787

pi->dll_default_on = false;

sys/dev/drm/radeon/ci_dpm.c

5788

pi->sram_end = SMC_RAM_END;

sys/dev/drm/radeon/ci_dpm.c

5790

pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5791

pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5792

pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5793

pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5794

pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5795

pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5796

pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5797

pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5799

pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;

sys/dev/drm/radeon/ci_dpm.c

5801

pi->sclk_dpm_key_disabled = 0;

sys/dev/drm/radeon/ci_dpm.c

5802

pi->mclk_dpm_key_disabled = 0;

sys/dev/drm/radeon/ci_dpm.c

5803

pi->pcie_dpm_key_disabled = 0;

sys/dev/drm/radeon/ci_dpm.c

5804

pi->thermal_sclk_dpm_enabled = 0;

sys/dev/drm/radeon/ci_dpm.c

5809

pi->mclk_dpm_key_disabled = 1;

sys/dev/drm/radeon/ci_dpm.c

5812

pi->caps_sclk_ds = true;

sys/dev/drm/radeon/ci_dpm.c

5814

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/radeon/ci_dpm.c

5815

pi->mclk_stutter_mode_threshold = 40000;

sys/dev/drm/radeon/ci_dpm.c

5816

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/radeon/ci_dpm.c

5817

pi->mclk_edc_wr_enable_threshold = 40000;

sys/dev/drm/radeon/ci_dpm.c

5821

pi->caps_fps = false;

sys/dev/drm/radeon/ci_dpm.c

5823

pi->caps_sclk_throttle_low_notification = false;

sys/dev/drm/radeon/ci_dpm.c

5825

pi->caps_uvd_dpm = true;

sys/dev/drm/radeon/ci_dpm.c

5826

pi->caps_vce_dpm = true;

sys/dev/drm/radeon/ci_dpm.c

5858

pi->thermal_temp_setting.temperature_low = 94500;

sys/dev/drm/radeon/ci_dpm.c

5859

pi->thermal_temp_setting.temperature_high = 95000;

sys/dev/drm/radeon/ci_dpm.c

5860

pi->thermal_temp_setting.temperature_shutdown = 104000;

sys/dev/drm/radeon/ci_dpm.c

5862

pi->thermal_temp_setting.temperature_low = 99500;

sys/dev/drm/radeon/ci_dpm.c

5863

pi->thermal_temp_setting.temperature_high = 100000;

sys/dev/drm/radeon/ci_dpm.c

5864

pi->thermal_temp_setting.temperature_shutdown = 104000;

sys/dev/drm/radeon/ci_dpm.c

5867

pi->uvd_enabled = false;

sys/dev/drm/radeon/ci_dpm.c

5869

dpm_table = &pi->smc_state_table;

sys/dev/drm/radeon/ci_dpm.c

5918

pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;

sys/dev/drm/radeon/ci_dpm.c

5919

pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;

sys/dev/drm/radeon/ci_dpm.c

5920

pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;

sys/dev/drm/radeon/ci_dpm.c

5922

pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;

sys/dev/drm/radeon/ci_dpm.c

5924

pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;

sys/dev/drm/radeon/ci_dpm.c

5928

pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;

sys/dev/drm/radeon/ci_dpm.c

5930

pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;

sys/dev/drm/radeon/ci_dpm.c

5937

pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;

sys/dev/drm/radeon/ci_dpm.c

5939

pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;

sys/dev/drm/radeon/ci_dpm.c

5944

pi->vddc_phase_shed_control = true;

sys/dev/drm/radeon/ci_dpm.c

5947

pi->pcie_performance_request =

sys/dev/drm/radeon/ci_dpm.c

5950

pi->pcie_performance_request = false;

sys/dev/drm/radeon/ci_dpm.c

5955

pi->caps_sclk_ss_support = true;

sys/dev/drm/radeon/ci_dpm.c

5956

pi->caps_mclk_ss_support = true;

sys/dev/drm/radeon/ci_dpm.c

5957

pi->dynamic_ss = true;

sys/dev/drm/radeon/ci_dpm.c

5959

pi->caps_sclk_ss_support = false;

sys/dev/drm/radeon/ci_dpm.c

5960

pi->caps_mclk_ss_support = false;

sys/dev/drm/radeon/ci_dpm.c

5961

pi->dynamic_ss = true;

sys/dev/drm/radeon/ci_dpm.c

5965

pi->thermal_protection = true;

sys/dev/drm/radeon/ci_dpm.c

5967

pi->thermal_protection = false;

sys/dev/drm/radeon/ci_dpm.c

5969

pi->caps_dynamic_ac_timing = true;

sys/dev/drm/radeon/ci_dpm.c

5971

pi->uvd_power_gated = false;

sys/dev/drm/radeon/ci_dpm.c

5979

pi->fan_ctrl_is_in_default_mode = true;

sys/dev/drm/radeon/ci_dpm.c

5987

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

5988

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/ci_dpm.c

5992

seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");

sys/dev/drm/radeon/ci_dpm.c

6032

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

6033

struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);

sys/dev/drm/radeon/ci_dpm.c

6043

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

6044

struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);

sys/dev/drm/radeon/ci_dpm.c

610

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

613

if (pi->caps_sq_ramping || pi->caps_db_ramping ||

sys/dev/drm/radeon/ci_dpm.c

614

pi->caps_td_ramping || pi->caps_tcp_ramping) {

sys/dev/drm/radeon/ci_dpm.c

635

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

640

pi->power_containment_features = 0;

sys/dev/drm/radeon/ci_dpm.c

641

if (pi->caps_power_containment) {

sys/dev/drm/radeon/ci_dpm.c

642

if (pi->enable_bapm_feature) {

sys/dev/drm/radeon/ci_dpm.c

647

pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;

sys/dev/drm/radeon/ci_dpm.c

650

if (pi->enable_tdc_limit_feature) {

sys/dev/drm/radeon/ci_dpm.c

655

pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;

sys/dev/drm/radeon/ci_dpm.c

658

if (pi->enable_pkg_pwr_tracking_feature) {

sys/dev/drm/radeon/ci_dpm.c

668

pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;

sys/dev/drm/radeon/ci_dpm.c

675

if (pi->caps_power_containment && pi->power_containment_features) {

sys/dev/drm/radeon/ci_dpm.c

676

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)

sys/dev/drm/radeon/ci_dpm.c

679

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)

sys/dev/drm/radeon/ci_dpm.c

682

if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)

sys/dev/drm/radeon/ci_dpm.c

684

pi->power_containment_features = 0;

sys/dev/drm/radeon/ci_dpm.c

693

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

697

if (pi->caps_cac) {

sys/dev/drm/radeon/ci_dpm.c

702

pi->cac_enabled = false;

sys/dev/drm/radeon/ci_dpm.c

704

pi->cac_enabled = true;

sys/dev/drm/radeon/ci_dpm.c

706

} else if (pi->cac_enabled) {

sys/dev/drm/radeon/ci_dpm.c

708

pi->cac_enabled = false;

sys/dev/drm/radeon/ci_dpm.c

718

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

721

if (pi->thermal_sclk_dpm_enabled) {

sys/dev/drm/radeon/ci_dpm.c

736

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

744

if (pi->caps_power_containment) {

sys/dev/drm/radeon/ci_dpm.c

758

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

760

if (pi->uvd_power_gated == gate)

sys/dev/drm/radeon/ci_dpm.c

763

pi->uvd_power_gated = gate;

sys/dev/drm/radeon/ci_dpm.c

770

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

772

u32 switch_limit = pi->mem_gddr5 ? 450 : 300;

sys/dev/drm/radeon/ci_dpm.c

833

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

854

pi->battery_state = true;

sys/dev/drm/radeon/ci_dpm.c

856

pi->battery_state = false;

sys/dev/drm/radeon/ci_dpm.c

971

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/ci_dpm.c

974

if (pi->fan_ctrl_is_in_default_mode) {

sys/dev/drm/radeon/ci_dpm.c

976

pi->fan_ctrl_default_mode = tmp;

sys/dev/drm/radeon/ci_dpm.c

978

pi->t_min = tmp;

sys/dev/drm/radeon/ci_dpm.c

979

pi->fan_ctrl_is_in_default_mode = false;

sys/dev/drm/radeon/ci_dpm.c

993

struct ci_power_info *pi = ci_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

100

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

102

if (pi->gfx_clock_gating) {

sys/dev/drm/radeon/cypress_dpm.c

1076

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1082

pi->mem_gddr5,

sys/dev/drm/radeon/cypress_dpm.c

1243

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1248

cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);

sys/dev/drm/radeon/cypress_dpm.c

1250

cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);

sys/dev/drm/radeon/cypress_dpm.c

1252

cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);

sys/dev/drm/radeon/cypress_dpm.c

1254

cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);

sys/dev/drm/radeon/cypress_dpm.c

1256

cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);

sys/dev/drm/radeon/cypress_dpm.c

1258

cpu_to_be32(pi->clk_regs.rv770.dll_cntl);

sys/dev/drm/radeon/cypress_dpm.c

1261

cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);

sys/dev/drm/radeon/cypress_dpm.c

1263

cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);

sys/dev/drm/radeon/cypress_dpm.c

1269

cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);

sys/dev/drm/radeon/cypress_dpm.c

1271

cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);

sys/dev/drm/radeon/cypress_dpm.c

1273

cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);

sys/dev/drm/radeon/cypress_dpm.c

1275

cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);

sys/dev/drm/radeon/cypress_dpm.c

1277

cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);

sys/dev/drm/radeon/cypress_dpm.c

1303

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/cypress_dpm.c

1306

if (pi->boot_in_gen2)

sys/dev/drm/radeon/cypress_dpm.c

1315

if (pi->mem_gddr5) {

sys/dev/drm/radeon/cypress_dpm.c

1320

if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/cypress_dpm.c

1337

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1340

pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/cypress_dpm.c

1342

pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/cypress_dpm.c

1344

pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/cypress_dpm.c

1346

pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/cypress_dpm.c

1348

pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/cypress_dpm.c

1350

pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/cypress_dpm.c

1352

pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/cypress_dpm.c

1354

pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/cypress_dpm.c

1356

pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/cypress_dpm.c

1362

if (pi->acpi_vddc) {

sys/dev/drm/radeon/cypress_dpm.c

1365

pi->acpi_vddc,

sys/dev/drm/radeon/cypress_dpm.c

1367

if (pi->pcie_gen2) {

sys/dev/drm/radeon/cypress_dpm.c

1368

if (pi->acpi_pcie_gen2)

sys/dev/drm/radeon/cypress_dpm.c

1374

if (pi->acpi_pcie_gen2)

sys/dev/drm/radeon/cypress_dpm.c

1381

pi->min_vddc_in_table,

sys/dev/drm/radeon/cypress_dpm.c

1399

if (pi->mem_gddr5)

sys/dev/drm/radeon/cypress_dpm.c

1530

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1544

if (pi->max_vddc_in_table <=

sys/dev/drm/radeon/cypress_dpm.c

1576

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1585

pi->mvdd_control = false;

sys/dev/drm/radeon/cypress_dpm.c

1600

pi->mvdd_control = false;

sys/dev/drm/radeon/cypress_dpm.c

1604

pi->mvdd_split_frequency =

sys/dev/drm/radeon/cypress_dpm.c

1607

if (pi->mvdd_split_frequency == 0) {

sys/dev/drm/radeon/cypress_dpm.c

1608

pi->mvdd_control = false;

sys/dev/drm/radeon/cypress_dpm.c

1618

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1619

RV770_SMC_STATETABLE *table = &pi->smc_statetable;

sys/dev/drm/radeon/cypress_dpm.c

1648

if (pi->mem_gddr5)

sys/dev/drm/radeon/cypress_dpm.c

1662

pi->state_table_start,

sys/dev/drm/radeon/cypress_dpm.c

1664

pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

1670

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1692

pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

1697

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1705

&tmp, pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

1709

pi->state_table_start = (u16)tmp;

sys/dev/drm/radeon/cypress_dpm.c

1714

&tmp, pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

1718

pi->soft_regs_start = (u16)tmp;

sys/dev/drm/radeon/cypress_dpm.c

1723

&tmp, pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

174

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1809

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1814

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/cypress_dpm.c

1820

if (pi->voltage_control) {

sys/dev/drm/radeon/cypress_dpm.c

1829

if (pi->mvdd_control) {

sys/dev/drm/radeon/cypress_dpm.c

1849

if (pi->dynamic_ss)

sys/dev/drm/radeon/cypress_dpm.c

1852

if (pi->thermal_protection)

sys/dev/drm/radeon/cypress_dpm.c

1864

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/cypress_dpm.c

1907

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/cypress_dpm.c

1910

if (pi->mg_clock_gating)

sys/dev/drm/radeon/cypress_dpm.c

1920

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

1929

if (pi->thermal_protection)

sys/dev/drm/radeon/cypress_dpm.c

1932

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/cypress_dpm.c

194

if (pi->mgcgtssm)

sys/dev/drm/radeon/cypress_dpm.c

1941

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/cypress_dpm.c

1944

if (pi->mg_clock_gating)

sys/dev/drm/radeon/cypress_dpm.c

2027

struct rv7xx_power_info *pi;

sys/dev/drm/radeon/cypress_dpm.c

2036

pi = &eg_pi->rv7xx;

sys/dev/drm/radeon/cypress_dpm.c

2041

pi->acpi_vddc = 0;

sys/dev/drm/radeon/cypress_dpm.c

2043

pi->min_vddc_in_table = 0;

sys/dev/drm/radeon/cypress_dpm.c

2044

pi->max_vddc_in_table = 0;

sys/dev/drm/radeon/cypress_dpm.c

2062

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/cypress_dpm.c

2064

pi->ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2066

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/radeon/cypress_dpm.c

2067

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/radeon/cypress_dpm.c

2070

pi->rlp = RV770_RLP_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2071

pi->rmp = RV770_RMP_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2072

pi->lhp = RV770_LHP_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2073

pi->lmp = RV770_LMP_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2075

pi->voltage_control =

sys/dev/drm/radeon/cypress_dpm.c

2078

pi->mvdd_control =

sys/dev/drm/radeon/cypress_dpm.c

2086

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2087

pi->pasi = CYPRESS_HASI_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2088

pi->vrc = CYPRESS_VRC_DFLT;

sys/dev/drm/radeon/cypress_dpm.c

2090

pi->power_gating = false;

sys/dev/drm/radeon/cypress_dpm.c

2094

pi->gfx_clock_gating = false;

sys/dev/drm/radeon/cypress_dpm.c

2096

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/cypress_dpm.c

2098

pi->mg_clock_gating = true;

sys/dev/drm/radeon/cypress_dpm.c

2099

pi->mgcgtssm = true;

sys/dev/drm/radeon/cypress_dpm.c

2103

pi->dynamic_pcie_gen2 = true;

sys/dev/drm/radeon/cypress_dpm.c

2106

pi->thermal_protection = true;

sys/dev/drm/radeon/cypress_dpm.c

2108

pi->thermal_protection = false;

sys/dev/drm/radeon/cypress_dpm.c

2110

pi->display_gap = true;

sys/dev/drm/radeon/cypress_dpm.c

2113

pi->dcodt = true;

sys/dev/drm/radeon/cypress_dpm.c

2115

pi->dcodt = false;

sys/dev/drm/radeon/cypress_dpm.c

2117

pi->ulps = true;

sys/dev/drm/radeon/cypress_dpm.c

2139

pi->mclk_stutter_mode_threshold = 0;

sys/dev/drm/radeon/cypress_dpm.c

2141

pi->sram_end = SMC_RAM_END;

sys/dev/drm/radeon/cypress_dpm.c

215

if (pi->mgcgtssm)

sys/dev/drm/radeon/cypress_dpm.c

2159

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

2162

u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

sys/dev/drm/radeon/cypress_dpm.c

223

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

226

if (pi->sclk_ss)

sys/dev/drm/radeon/cypress_dpm.c

229

if (pi->mclk_ss)

sys/dev/drm/radeon/cypress_dpm.c

330

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

341

pi->pcie_gen2 = true;

sys/dev/drm/radeon/cypress_dpm.c

343

pi->pcie_gen2 = false;

sys/dev/drm/radeon/cypress_dpm.c

345

if (!pi->pcie_gen2)

sys/dev/drm/radeon/cypress_dpm.c

425

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

429

if (pi->mem_gddr5) {

sys/dev/drm/radeon/cypress_dpm.c

430

if (mclk <= pi->mclk_strobe_mode_threshold)

sys/dev/drm/radeon/cypress_dpm.c

478

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

481

pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/cypress_dpm.c

483

pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/cypress_dpm.c

485

pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/cypress_dpm.c

487

pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/cypress_dpm.c

489

pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/cypress_dpm.c

491

pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/cypress_dpm.c

492

u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;

sys/dev/drm/radeon/cypress_dpm.c

493

u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;

sys/dev/drm/radeon/cypress_dpm.c

52

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

530

if (pi->mem_gddr5) {

sys/dev/drm/radeon/cypress_dpm.c

553

if (pi->mclk_ss) {

sys/dev/drm/radeon/cypress_dpm.c

577

dll_speed = rv740_get_dll_speed(pi->mem_gddr5,

sys/dev/drm/radeon/cypress_dpm.c

59

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/cypress_dpm.c

659

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

662

if (!pi->mvdd_control) {

sys/dev/drm/radeon/cypress_dpm.c

668

if (mclk <= pi->mvdd_split_frequency) {

sys/dev/drm/radeon/cypress_dpm.c

684

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

689

level->gen2PCIE = pi->pcie_gen2 ?

sys/dev/drm/radeon/cypress_dpm.c

700

if (pi->mclk_stutter_mode_threshold &&

sys/dev/drm/radeon/cypress_dpm.c

701

(pl->mclk <= pi->mclk_stutter_mode_threshold) &&

sys/dev/drm/radeon/cypress_dpm.c

710

if (pi->mem_gddr5) {

sys/dev/drm/radeon/cypress_dpm.c

711

if (pl->mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/cypress_dpm.c

76

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/cypress_dpm.c

873

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

874

u16 address = pi->state_table_start +

sys/dev/drm/radeon/cypress_dpm.c

885

pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

891

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

904

pi->sram_end);

sys/dev/drm/radeon/cypress_dpm.c

910

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/cypress_dpm.c

911

u32 multiplier = pi->mem_gddr5 ? 1 : 2;

sys/dev/drm/radeon/kv_dpm.c

1002

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1004

(u8 *)&pi->samu_level,

sys/dev/drm/radeon/kv_dpm.c

1006

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1016

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1026

pi->acp_level_count = 0;

sys/dev/drm/radeon/kv_dpm.c

1028

pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

1029

pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

1035

pi->acp_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

1037

pi->acp_level_count++;

sys/dev/drm/radeon/kv_dpm.c

1041

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1043

(u8 *)&pi->acp_level_count,

sys/dev/drm/radeon/kv_dpm.c

1045

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1049

pi->acp_interval = 1;

sys/dev/drm/radeon/kv_dpm.c

1052

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1054

(u8 *)&pi->acp_interval,

sys/dev/drm/radeon/kv_dpm.c

1056

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1061

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1063

(u8 *)&pi->acp_level,

sys/dev/drm/radeon/kv_dpm.c

1065

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1074

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1080

for (i = 0; i < pi->graphics_dpm_level_count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1081

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/radeon/kv_dpm.c

1083

pi->graphics_level[i].ClkBypassCntl = 3;

sys/dev/drm/radeon/kv_dpm.c

1085

pi->graphics_level[i].ClkBypassCntl = 2;

sys/dev/drm/radeon/kv_dpm.c

1087

pi->graphics_level[i].ClkBypassCntl = 7;

sys/dev/drm/radeon/kv_dpm.c

1089

pi->graphics_level[i].ClkBypassCntl = 6;

sys/dev/drm/radeon/kv_dpm.c

1091

pi->graphics_level[i].ClkBypassCntl = 8;

sys/dev/drm/radeon/kv_dpm.c

1093

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/radeon/kv_dpm.c

1095

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/radeon/kv_dpm.c

1100

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/radeon/kv_dpm.c

1101

for (i = 0; i < pi->graphics_dpm_level_count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1102

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/radeon/kv_dpm.c

1104

pi->graphics_level[i].ClkBypassCntl = 3;

sys/dev/drm/radeon/kv_dpm.c

1106

pi->graphics_level[i].ClkBypassCntl = 2;

sys/dev/drm/radeon/kv_dpm.c

1108

pi->graphics_level[i].ClkBypassCntl = 7;

sys/dev/drm/radeon/kv_dpm.c

1110

pi->graphics_level[i].ClkBypassCntl = 6;

sys/dev/drm/radeon/kv_dpm.c

1112

pi->graphics_level[i].ClkBypassCntl = 8;

sys/dev/drm/radeon/kv_dpm.c

1114

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/radeon/kv_dpm.c

1116

pi->graphics_level[i].ClkBypassCntl = 0;

sys/dev/drm/radeon/kv_dpm.c

1130

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1132

pi->acp_boot_level = 0xff;

sys/dev/drm/radeon/kv_dpm.c

1139

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1141

pi->current_rps = *rps;

sys/dev/drm/radeon/kv_dpm.c

1142

pi->current_ps = *new_ps;

sys/dev/drm/radeon/kv_dpm.c

1143

pi->current_rps.ps_priv = &pi->current_ps;

sys/dev/drm/radeon/kv_dpm.c

1150

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1152

pi->requested_rps = *rps;

sys/dev/drm/radeon/kv_dpm.c

1153

pi->requested_ps = *new_ps;

sys/dev/drm/radeon/kv_dpm.c

1154

pi->requested_rps.ps_priv = &pi->requested_ps;

sys/dev/drm/radeon/kv_dpm.c

1159

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1162

if (pi->bapm_enable) {

sys/dev/drm/radeon/kv_dpm.c

1184

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1230

if (pi->enable_auto_thermal_throttling) {

sys/dev/drm/radeon/kv_dpm.c

1333

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1335

return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,

sys/dev/drm/radeon/kv_dpm.c

1336

(u8 *)&value, sizeof(u16), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1342

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1344

return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,

sys/dev/drm/radeon/kv_dpm.c

1345

value, pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1351

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1353

pi->low_sclk_interrupt_t = 0;

sys/dev/drm/radeon/kv_dpm.c

1358

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1361

if (pi->caps_fps) {

sys/dev/drm/radeon/kv_dpm.c

1365

pi->fps_high_t = cpu_to_be16(tmp);

sys/dev/drm/radeon/kv_dpm.c

1367

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1369

(u8 *)&pi->fps_high_t,

sys/dev/drm/radeon/kv_dpm.c

1370

sizeof(u16), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1373

pi->fps_low_t = cpu_to_be16(tmp);

sys/dev/drm/radeon/kv_dpm.c

1376

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1378

(u8 *)&pi->fps_low_t,

sys/dev/drm/radeon/kv_dpm.c

1379

sizeof(u16), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1387

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1389

pi->uvd_power_gated = false;

sys/dev/drm/radeon/kv_dpm.c

1390

pi->vce_power_gated = false;

sys/dev/drm/radeon/kv_dpm.c

1391

pi->samu_power_gated = false;

sys/dev/drm/radeon/kv_dpm.c

1392

pi->acp_power_gated = false;

sys/dev/drm/radeon/kv_dpm.c

1422

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1430

pi->uvd_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1432

pi->uvd_boot_level = 0;

sys/dev/drm/radeon/kv_dpm.c

1434

if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) {

sys/dev/drm/radeon/kv_dpm.c

1435

mask = 1 << pi->uvd_boot_level;

sys/dev/drm/radeon/kv_dpm.c

1441

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1443

(uint8_t *)&pi->uvd_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1444

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1474

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1483

if (pi->caps_stable_p_state)

sys/dev/drm/radeon/kv_dpm.c

1484

pi->vce_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1486

pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk);

sys/dev/drm/radeon/kv_dpm.c

1489

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1491

(u8 *)&pi->vce_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1493

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1497

if (pi->caps_stable_p_state)

sys/dev/drm/radeon/kv_dpm.c

1500

(1 << pi->vce_boot_level));

sys/dev/drm/radeon/kv_dpm.c

1515

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1521

if (pi->caps_stable_p_state)

sys/dev/drm/radeon/kv_dpm.c

1522

pi->samu_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1524

pi->samu_boot_level = 0;

sys/dev/drm/radeon/kv_dpm.c

1527

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1529

(u8 *)&pi->samu_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1531

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1535

if (pi->caps_stable_p_state)

sys/dev/drm/radeon/kv_dpm.c

1538

(1 << pi->samu_boot_level));

sys/dev/drm/radeon/kv_dpm.c

1563

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1566

if (!pi->caps_stable_p_state) {

sys/dev/drm/radeon/kv_dpm.c

1568

if (acp_boot_level != pi->acp_boot_level) {

sys/dev/drm/radeon/kv_dpm.c

1569

pi->acp_boot_level = acp_boot_level;

sys/dev/drm/radeon/kv_dpm.c

1572

(1 << pi->acp_boot_level));

sys/dev/drm/radeon/kv_dpm.c

1579

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1585

if (pi->caps_stable_p_state)

sys/dev/drm/radeon/kv_dpm.c

1586

pi->acp_boot_level = table->count - 1;

sys/dev/drm/radeon/kv_dpm.c

1588

pi->acp_boot_level = kv_get_acp_boot_level(rdev);

sys/dev/drm/radeon/kv_dpm.c

1591

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1593

(u8 *)&pi->acp_boot_level,

sys/dev/drm/radeon/kv_dpm.c

1595

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1599

if (pi->caps_stable_p_state)

sys/dev/drm/radeon/kv_dpm.c

1602

(1 << pi->acp_boot_level));

sys/dev/drm/radeon/kv_dpm.c

1610

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1612

if (pi->uvd_power_gated == gate)

sys/dev/drm/radeon/kv_dpm.c

1615

pi->uvd_power_gated = gate;

sys/dev/drm/radeon/kv_dpm.c

1618

if (pi->caps_uvd_pg) {

sys/dev/drm/radeon/kv_dpm.c

1623

if (pi->caps_uvd_pg)

sys/dev/drm/radeon/kv_dpm.c

1626

if (pi->caps_uvd_pg) {

sys/dev/drm/radeon/kv_dpm.c

1638

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1640

if (pi->vce_power_gated == gate)

sys/dev/drm/radeon/kv_dpm.c

1643

pi->vce_power_gated = gate;

sys/dev/drm/radeon/kv_dpm.c

1646

if (pi->caps_vce_pg) {

sys/dev/drm/radeon/kv_dpm.c

1651

if (pi->caps_vce_pg) {

sys/dev/drm/radeon/kv_dpm.c

1661

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1663

if (pi->samu_power_gated == gate)

sys/dev/drm/radeon/kv_dpm.c

1666

pi->samu_power_gated = gate;

sys/dev/drm/radeon/kv_dpm.c

1670

if (pi->caps_samu_pg)

sys/dev/drm/radeon/kv_dpm.c

1673

if (pi->caps_samu_pg)

sys/dev/drm/radeon/kv_dpm.c

1681

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1683

if (pi->acp_power_gated == gate)

sys/dev/drm/radeon/kv_dpm.c

1689

pi->acp_power_gated = gate;

sys/dev/drm/radeon/kv_dpm.c

1693

if (pi->caps_acp_pg)

sys/dev/drm/radeon/kv_dpm.c

1696

if (pi->caps_acp_pg)

sys/dev/drm/radeon/kv_dpm.c

1706

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1712

for (i = 0; i < pi->graphics_dpm_level_count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1714

(i == (pi->graphics_dpm_level_count - 1))) {

sys/dev/drm/radeon/kv_dpm.c

1715

pi->lowest_valid = i;

sys/dev/drm/radeon/kv_dpm.c

1720

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

1724

pi->highest_valid = i;

sys/dev/drm/radeon/kv_dpm.c

1726

if (pi->lowest_valid > pi->highest_valid) {

sys/dev/drm/radeon/kv_dpm.c

1727

if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >

sys/dev/drm/radeon/kv_dpm.c

1728

(table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))

sys/dev/drm/radeon/kv_dpm.c

1729

pi->highest_valid = pi->lowest_valid;

sys/dev/drm/radeon/kv_dpm.c

1731

pi->lowest_valid = pi->highest_valid;

sys/dev/drm/radeon/kv_dpm.c

1735

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/radeon/kv_dpm.c

1737

for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {

sys/dev/drm/radeon/kv_dpm.c

1739

i == (int)(pi->graphics_dpm_level_count - 1)) {

sys/dev/drm/radeon/kv_dpm.c

1740

pi->lowest_valid = i;

sys/dev/drm/radeon/kv_dpm.c

1745

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

1750

pi->highest_valid = i;

sys/dev/drm/radeon/kv_dpm.c

1752

if (pi->lowest_valid > pi->highest_valid) {

sys/dev/drm/radeon/kv_dpm.c

1754

table->entries[pi->highest_valid].sclk_frequency) >

sys/dev/drm/radeon/kv_dpm.c

1755

(table->entries[pi->lowest_valid].sclk_frequency -

sys/dev/drm/radeon/kv_dpm.c

1757

pi->highest_valid = pi->lowest_valid;

sys/dev/drm/radeon/kv_dpm.c

1759

pi->lowest_valid = pi->highest_valid;

sys/dev/drm/radeon/kv_dpm.c

1768

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1772

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/radeon/kv_dpm.c

1774

pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;

sys/dev/drm/radeon/kv_dpm.c

1776

(pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

1778

(pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +

sys/dev/drm/radeon/kv_dpm.c

1781

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

1790

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1794

if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {

sys/dev/drm/radeon/kv_dpm.c

1797

pi->nb_dpm_enabled = true;

sys/dev/drm/radeon/kv_dpm.c

1800

if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {

sys/dev/drm/radeon/kv_dpm.c

1803

pi->nb_dpm_enabled = false;

sys/dev/drm/radeon/kv_dpm.c

1836

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1843

&pi->requested_rps,

sys/dev/drm/radeon/kv_dpm.c

1844

&pi->current_rps);

sys/dev/drm/radeon/kv_dpm.c

1851

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1852

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/kv_dpm.c

1853

struct radeon_ps *old_ps = &pi->current_rps;

sys/dev/drm/radeon/kv_dpm.c

1856

if (pi->bapm_enable) {

sys/dev/drm/radeon/kv_dpm.c

1865

if (pi->enable_dpm) {

sys/dev/drm/radeon/kv_dpm.c

1894

if (pi->enable_dpm) {

sys/dev/drm/radeon/kv_dpm.c

1925

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1926

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/kv_dpm.c

1941

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1956

kv_set_enabled_level(rdev, pi->graphics_boot_level);

sys/dev/drm/radeon/kv_dpm.c

1966

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

1968

if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {

sys/dev/drm/radeon/kv_dpm.c

1969

int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;

sys/dev/drm/radeon/kv_dpm.c

1971

pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;

sys/dev/drm/radeon/kv_dpm.c

1974

pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);

sys/dev/drm/radeon/kv_dpm.c

1977

table->mclk = pi->sys_info.nbp_memory_clock[0];

sys/dev/drm/radeon/kv_dpm.c

2024

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2026

pi->boot_pl.sclk = pi->sys_info.bootup_sclk;

sys/dev/drm/radeon/kv_dpm.c

2027

pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;

sys/dev/drm/radeon/kv_dpm.c

2028

pi->boot_pl.ds_divider_index = 0;

sys/dev/drm/radeon/kv_dpm.c

2029

pi->boot_pl.ss_divider_index = 0;

sys/dev/drm/radeon/kv_dpm.c

2030

pi->boot_pl.allow_gnb_slow = 1;

sys/dev/drm/radeon/kv_dpm.c

2031

pi->boot_pl.force_nbp_state = 0;

sys/dev/drm/radeon/kv_dpm.c

2032

pi->boot_pl.display_wm = 0;

sys/dev/drm/radeon/kv_dpm.c

2033

pi->boot_pl.vce_wm = 0;

sys/dev/drm/radeon/kv_dpm.c

2079

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2088

if (!pi->caps_sclk_ds)

sys/dev/drm/radeon/kv_dpm.c

2102

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2109

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

2111

pi->high_voltage_t)) {

sys/dev/drm/radeon/kv_dpm.c

2118

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/radeon/kv_dpm.c

2121

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

2123

pi->high_voltage_t)) {

sys/dev/drm/radeon/kv_dpm.c

2139

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2161

if (pi->caps_stable_p_state) {

sys/dev/drm/radeon/kv_dpm.c

2191

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

2192

(pi->high_voltage_t <

sys/dev/drm/radeon/kv_dpm.c

2200

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/radeon/kv_dpm.c

2203

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

2204

(pi->high_voltage_t <

sys/dev/drm/radeon/kv_dpm.c

2212

if (pi->caps_stable_p_state) {

sys/dev/drm/radeon/kv_dpm.c

2218

pi->video_start = new_rps->dclk || new_rps->vclk ||

sys/dev/drm/radeon/kv_dpm.c

2223

pi->battery_state = true;

sys/dev/drm/radeon/kv_dpm.c

2225

pi->battery_state = false;

sys/dev/drm/radeon/kv_dpm.c

2238

if (pi->sys_info.nb_dpm_enable) {

sys/dev/drm/radeon/kv_dpm.c

2239

force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||

sys/dev/drm/radeon/kv_dpm.c

2240

pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||

sys/dev/drm/radeon/kv_dpm.c

2241

pi->disable_nb_ps3_in_battery;

sys/dev/drm/radeon/kv_dpm.c

2253

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2255

pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;

sys/dev/drm/radeon/kv_dpm.c

2260

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2264

if (pi->lowest_valid > pi->highest_valid)

sys/dev/drm/radeon/kv_dpm.c

2267

for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {

sys/dev/drm/radeon/kv_dpm.c

2268

pi->graphics_level[i].DeepSleepDivId =

sys/dev/drm/radeon/kv_dpm.c

2270

be32_to_cpu(pi->graphics_level[i].SclkFrequency),

sys/dev/drm/radeon/kv_dpm.c

2278

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2285

if (pi->lowest_valid > pi->highest_valid)

sys/dev/drm/radeon/kv_dpm.c

2289

for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {

sys/dev/drm/radeon/kv_dpm.c

2290

pi->graphics_level[i].GnbSlow = 1;

sys/dev/drm/radeon/kv_dpm.c

2291

pi->graphics_level[i].ForceNbPs1 = 0;

sys/dev/drm/radeon/kv_dpm.c

2292

pi->graphics_level[i].UpH = 0;

sys/dev/drm/radeon/kv_dpm.c

2295

if (!pi->sys_info.nb_dpm_enable)

sys/dev/drm/radeon/kv_dpm.c

2298

force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||

sys/dev/drm/radeon/kv_dpm.c

2299

(rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);

sys/dev/drm/radeon/kv_dpm.c

2302

for (i = pi->lowest_valid; i <= pi->highest_valid; i++)

sys/dev/drm/radeon/kv_dpm.c

2303

pi->graphics_level[i].GnbSlow = 0;

sys/dev/drm/radeon/kv_dpm.c

2305

if (pi->battery_state)

sys/dev/drm/radeon/kv_dpm.c

2306

pi->graphics_level[0].ForceNbPs1 = 1;

sys/dev/drm/radeon/kv_dpm.c

2308

pi->graphics_level[1].GnbSlow = 0;

sys/dev/drm/radeon/kv_dpm.c

2309

pi->graphics_level[2].GnbSlow = 0;

sys/dev/drm/radeon/kv_dpm.c

2310

pi->graphics_level[3].GnbSlow = 0;

sys/dev/drm/radeon/kv_dpm.c

2311

pi->graphics_level[4].GnbSlow = 0;

sys/dev/drm/radeon/kv_dpm.c

2314

for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {

sys/dev/drm/radeon/kv_dpm.c

2315

pi->graphics_level[i].GnbSlow = 1;

sys/dev/drm/radeon/kv_dpm.c

2316

pi->graphics_level[i].ForceNbPs1 = 0;

sys/dev/drm/radeon/kv_dpm.c

2317

pi->graphics_level[i].UpH = 0;

sys/dev/drm/radeon/kv_dpm.c

2320

if (pi->sys_info.nb_dpm_enable && pi->battery_state) {

sys/dev/drm/radeon/kv_dpm.c

2321

pi->graphics_level[pi->lowest_valid].UpH = 0x28;

sys/dev/drm/radeon/kv_dpm.c

2322

pi->graphics_level[pi->lowest_valid].GnbSlow = 0;

sys/dev/drm/radeon/kv_dpm.c

2323

if (pi->lowest_valid != pi->highest_valid)

sys/dev/drm/radeon/kv_dpm.c

2324

pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;

sys/dev/drm/radeon/kv_dpm.c

2332

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2335

if (pi->lowest_valid > pi->highest_valid)

sys/dev/drm/radeon/kv_dpm.c

2338

for (i = pi->lowest_valid; i <= pi->highest_valid; i++)

sys/dev/drm/radeon/kv_dpm.c

2339

pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;

sys/dev/drm/radeon/kv_dpm.c

2346

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2354

pi->graphics_dpm_level_count = 0;

sys/dev/drm/radeon/kv_dpm.c

2356

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

2357

(pi->high_voltage_t <

sys/dev/drm/radeon/kv_dpm.c

2363

&pi->sys_info.vid_mapping_table,

sys/dev/drm/radeon/kv_dpm.c

2366

kv_set_at(rdev, i, pi->at[i]);

sys/dev/drm/radeon/kv_dpm.c

2368

pi->graphics_dpm_level_count++;

sys/dev/drm/radeon/kv_dpm.c

2372

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/radeon/kv_dpm.c

2374

pi->graphics_dpm_level_count = 0;

sys/dev/drm/radeon/kv_dpm.c

2376

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

2377

pi->high_voltage_t <

sys/dev/drm/radeon/kv_dpm.c

2383

kv_set_at(rdev, i, pi->at[i]);

sys/dev/drm/radeon/kv_dpm.c

2385

pi->graphics_dpm_level_count++;

sys/dev/drm/radeon/kv_dpm.c

2395

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2399

if (i >= pi->lowest_valid && i <= pi->highest_valid)

sys/dev/drm/radeon/kv_dpm.c

2415

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2418

for (i = pi->lowest_valid; i <= pi->highest_valid; i++)

sys/dev/drm/radeon/kv_dpm.c

2430

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2436

if (pi->sys_info.nb_dpm_enable) {

sys/dev/drm/radeon/kv_dpm.c

248

struct kv_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/kv_dpm.c

2487

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

250

return pi;

sys/dev/drm/radeon/kv_dpm.c

2504

pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);

sys/dev/drm/radeon/kv_dpm.c

2505

pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);

sys/dev/drm/radeon/kv_dpm.c

2506

pi->sys_info.bootup_nb_voltage_index =

sys/dev/drm/radeon/kv_dpm.c

2509

pi->sys_info.htc_tmp_lmt = 203;

sys/dev/drm/radeon/kv_dpm.c

2511

pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;

sys/dev/drm/radeon/kv_dpm.c

2513

pi->sys_info.htc_hyst_lmt = 5;

sys/dev/drm/radeon/kv_dpm.c

2515

pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;

sys/dev/drm/radeon/kv_dpm.c

2516

if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {

sys/dev/drm/radeon/kv_dpm.c

2521

pi->sys_info.nb_dpm_enable = true;

sys/dev/drm/radeon/kv_dpm.c

2523

pi->sys_info.nb_dpm_enable = false;

sys/dev/drm/radeon/kv_dpm.c

2526

pi->sys_info.nbp_memory_clock[i] =

sys/dev/drm/radeon/kv_dpm.c

2528

pi->sys_info.nbp_n_clock[i] =

sys/dev/drm/radeon/kv_dpm.c

2533

pi->caps_enable_dfs_bypass = true;

sys/dev/drm/radeon/kv_dpm.c

2536

&pi->sys_info.sclk_voltage_mapping_table,

sys/dev/drm/radeon/kv_dpm.c

2540

&pi->sys_info.vid_mapping_table,

sys/dev/drm/radeon/kv_dpm.c

2573

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2576

ps->levels[0] = pi->boot_pl;

sys/dev/drm/radeon/kv_dpm.c

2610

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2622

if (pi->caps_sclk_ds) {

sys/dev/drm/radeon/kv_dpm.c

2719

struct kv_power_info *pi;

sys/dev/drm/radeon/kv_dpm.c

2722

pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);

sys/dev/drm/radeon/kv_dpm.c

2723

if (pi == NULL)

sys/dev/drm/radeon/kv_dpm.c

2725

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/kv_dpm.c

2736

pi->at[i] = TRINITY_AT_DFLT;

sys/dev/drm/radeon/kv_dpm.c

2738

pi->sram_end = SMC_RAM_END;

sys/dev/drm/radeon/kv_dpm.c

2742

pi->enable_nb_dpm = false;

sys/dev/drm/radeon/kv_dpm.c

2744

pi->enable_nb_dpm = true;

sys/dev/drm/radeon/kv_dpm.c

2746

pi->caps_power_containment = true;

sys/dev/drm/radeon/kv_dpm.c

2747

pi->caps_cac = true;

sys/dev/drm/radeon/kv_dpm.c

2748

pi->enable_didt = false;

sys/dev/drm/radeon/kv_dpm.c

2749

if (pi->enable_didt) {

sys/dev/drm/radeon/kv_dpm.c

2750

pi->caps_sq_ramping = true;

sys/dev/drm/radeon/kv_dpm.c

2751

pi->caps_db_ramping = true;

sys/dev/drm/radeon/kv_dpm.c

2752

pi->caps_td_ramping = true;

sys/dev/drm/radeon/kv_dpm.c

2753

pi->caps_tcp_ramping = true;

sys/dev/drm/radeon/kv_dpm.c

2756

pi->caps_sclk_ds = true;

sys/dev/drm/radeon/kv_dpm.c

2757

pi->enable_auto_thermal_throttling = true;

sys/dev/drm/radeon/kv_dpm.c

2758

pi->disable_nb_ps3_in_battery = false;

sys/dev/drm/radeon/kv_dpm.c

2762

pi->bapm_enable = true;

sys/dev/drm/radeon/kv_dpm.c

2764

pi->bapm_enable = false;

sys/dev/drm/radeon/kv_dpm.c

2766

pi->bapm_enable = false;

sys/dev/drm/radeon/kv_dpm.c

2768

pi->bapm_enable = true;

sys/dev/drm/radeon/kv_dpm.c

2770

pi->voltage_drop_t = 0;

sys/dev/drm/radeon/kv_dpm.c

2771

pi->caps_sclk_throttle_low_notification = false;

sys/dev/drm/radeon/kv_dpm.c

2772

pi->caps_fps = false; /* true? */

sys/dev/drm/radeon/kv_dpm.c

2773

pi->caps_uvd_pg = true;

sys/dev/drm/radeon/kv_dpm.c

2774

pi->caps_uvd_dpm = true;

sys/dev/drm/radeon/kv_dpm.c

2775

pi->caps_vce_pg = false; /* XXX true */

sys/dev/drm/radeon/kv_dpm.c

2776

pi->caps_samu_pg = false;

sys/dev/drm/radeon/kv_dpm.c

2777

pi->caps_acp_pg = false;

sys/dev/drm/radeon/kv_dpm.c

2778

pi->caps_stable_p_state = false;

sys/dev/drm/radeon/kv_dpm.c

2791

pi->enable_dpm = true;

sys/dev/drm/radeon/kv_dpm.c

2799

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2809

sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);

sys/dev/drm/radeon/kv_dpm.c

2813

seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");

sys/dev/drm/radeon/kv_dpm.c

2814

seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en");

sys/dev/drm/radeon/kv_dpm.c

2822

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2831

sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);

sys/dev/drm/radeon/kv_dpm.c

2838

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2840

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/radeon/kv_dpm.c

2880

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2881

struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);

sys/dev/drm/radeon/kv_dpm.c

2891

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

2893

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/radeon/kv_dpm.c

330

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

333

if (pi->caps_sq_ramping) {

sys/dev/drm/radeon/kv_dpm.c

342

if (pi->caps_db_ramping) {

sys/dev/drm/radeon/kv_dpm.c

351

if (pi->caps_td_ramping) {

sys/dev/drm/radeon/kv_dpm.c

360

if (pi->caps_tcp_ramping) {

sys/dev/drm/radeon/kv_dpm.c

372

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

375

if (pi->caps_sq_ramping ||

sys/dev/drm/radeon/kv_dpm.c

376

pi->caps_db_ramping ||

sys/dev/drm/radeon/kv_dpm.c

377

pi->caps_td_ramping ||

sys/dev/drm/radeon/kv_dpm.c

378

pi->caps_tcp_ramping) {

sys/dev/drm/radeon/kv_dpm.c

400

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

402

if (pi->caps_cac) {

sys/dev/drm/radeon/kv_dpm.c

432

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

435

if (pi->caps_cac) {

sys/dev/drm/radeon/kv_dpm.c

439

pi->cac_enabled = false;

sys/dev/drm/radeon/kv_dpm.c

441

pi->cac_enabled = true;

sys/dev/drm/radeon/kv_dpm.c

442

} else if (pi->cac_enabled) {

sys/dev/drm/radeon/kv_dpm.c

444

pi->cac_enabled = false;

sys/dev/drm/radeon/kv_dpm.c

453

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

459

&tmp, pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

462

pi->dpm_table_start = tmp;

sys/dev/drm/radeon/kv_dpm.c

466

&tmp, pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

469

pi->soft_regs_start = tmp;

sys/dev/drm/radeon/kv_dpm.c

476

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

479

pi->graphics_voltage_change_enable = 1;

sys/dev/drm/radeon/kv_dpm.c

482

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

484

&pi->graphics_voltage_change_enable,

sys/dev/drm/radeon/kv_dpm.c

485

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

492

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

495

pi->graphics_interval = 1;

sys/dev/drm/radeon/kv_dpm.c

498

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

500

&pi->graphics_interval,

sys/dev/drm/radeon/kv_dpm.c

501

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

508

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

512

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

514

&pi->graphics_boot_level,

sys/dev/drm/radeon/kv_dpm.c

515

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

533

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

542

pi->graphics_level[index].SclkDid = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

543

pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);

sys/dev/drm/radeon/kv_dpm.c

603

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

605

&pi->sys_info.vid_mapping_table,

sys/dev/drm/radeon/kv_dpm.c

614

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

616

pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;

sys/dev/drm/radeon/kv_dpm.c

617

pi->graphics_level[index].MinVddNb =

sys/dev/drm/radeon/kv_dpm.c

625

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

627

pi->graphics_level[index].AT = cpu_to_be16((u16)at);

sys/dev/drm/radeon/kv_dpm.c

635

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

637

pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;

sys/dev/drm/radeon/kv_dpm.c

695

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

699

if (pi->caps_sclk_throttle_low_notification) {

sys/dev/drm/radeon/kv_dpm.c

700

low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);

sys/dev/drm/radeon/kv_dpm.c

703

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

706

sizeof(u32), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

713

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

719

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

720

if (table->entries[i].clk == pi->boot_pl.sclk)

sys/dev/drm/radeon/kv_dpm.c

724

pi->graphics_boot_level = (u8)i;

sys/dev/drm/radeon/kv_dpm.c

728

&pi->sys_info.sclk_voltage_mapping_table;

sys/dev/drm/radeon/kv_dpm.c

733

for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {

sys/dev/drm/radeon/kv_dpm.c

734

if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)

sys/dev/drm/radeon/kv_dpm.c

738

pi->graphics_boot_level = (u8)i;

sys/dev/drm/radeon/kv_dpm.c

746

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

749

pi->graphics_therm_throttle_enable = 1;

sys/dev/drm/radeon/kv_dpm.c

752

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

754

&pi->graphics_therm_throttle_enable,

sys/dev/drm/radeon/kv_dpm.c

755

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

762

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

766

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

768

(u8 *)&pi->graphics_level,

sys/dev/drm/radeon/kv_dpm.c

770

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

776

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

778

&pi->graphics_dpm_level_count,

sys/dev/drm/radeon/kv_dpm.c

779

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

791

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

794

if (pi->caps_enable_dfs_bypass) {

sys/dev/drm/radeon/kv_dpm.c

816

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

826

pi->uvd_level_count = 0;

sys/dev/drm/radeon/kv_dpm.c

828

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

829

(pi->high_voltage_t < table->entries[i].v))

sys/dev/drm/radeon/kv_dpm.c

832

pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);

sys/dev/drm/radeon/kv_dpm.c

833

pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);

sys/dev/drm/radeon/kv_dpm.c

834

pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

836

pi->uvd_level[i].VClkBypassCntl =

sys/dev/drm/radeon/kv_dpm.c

838

pi->uvd_level[i].DClkBypassCntl =

sys/dev/drm/radeon/kv_dpm.c

845

pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

851

pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

853

pi->uvd_level_count++;

sys/dev/drm/radeon/kv_dpm.c

857

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

859

(u8 *)&pi->uvd_level_count,

sys/dev/drm/radeon/kv_dpm.c

860

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

864

pi->uvd_interval = 1;

sys/dev/drm/radeon/kv_dpm.c

867

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

869

&pi->uvd_interval,

sys/dev/drm/radeon/kv_dpm.c

870

sizeof(u8), pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

875

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

877

(u8 *)&pi->uvd_level,

sys/dev/drm/radeon/kv_dpm.c

879

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

887

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

897

pi->vce_level_count = 0;

sys/dev/drm/radeon/kv_dpm.c

899

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

900

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/radeon/kv_dpm.c

903

pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);

sys/dev/drm/radeon/kv_dpm.c

904

pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

906

pi->vce_level[i].ClkBypassCntl =

sys/dev/drm/radeon/kv_dpm.c

913

pi->vce_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

915

pi->vce_level_count++;

sys/dev/drm/radeon/kv_dpm.c

919

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

921

(u8 *)&pi->vce_level_count,

sys/dev/drm/radeon/kv_dpm.c

923

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

927

pi->vce_interval = 1;

sys/dev/drm/radeon/kv_dpm.c

930

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

932

(u8 *)&pi->vce_interval,

sys/dev/drm/radeon/kv_dpm.c

934

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

939

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

941

(u8 *)&pi->vce_level,

sys/dev/drm/radeon/kv_dpm.c

943

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

950

struct kv_power_info *pi = kv_get_pi(rdev);

sys/dev/drm/radeon/kv_dpm.c

960

pi->samu_level_count = 0;

sys/dev/drm/radeon/kv_dpm.c

962

if (pi->high_voltage_t &&

sys/dev/drm/radeon/kv_dpm.c

963

pi->high_voltage_t < table->entries[i].v)

sys/dev/drm/radeon/kv_dpm.c

966

pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);

sys/dev/drm/radeon/kv_dpm.c

967

pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);

sys/dev/drm/radeon/kv_dpm.c

969

pi->samu_level[i].ClkBypassCntl =

sys/dev/drm/radeon/kv_dpm.c

976

pi->samu_level[i].Divider = (u8)dividers.post_div;

sys/dev/drm/radeon/kv_dpm.c

978

pi->samu_level_count++;

sys/dev/drm/radeon/kv_dpm.c

982

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

984

(u8 *)&pi->samu_level_count,

sys/dev/drm/radeon/kv_dpm.c

986

pi->sram_end);

sys/dev/drm/radeon/kv_dpm.c

990

pi->samu_interval = 1;

sys/dev/drm/radeon/kv_dpm.c

993

pi->dpm_table_start +

sys/dev/drm/radeon/kv_dpm.c

995

(u8 *)&pi->samu_interval,

sys/dev/drm/radeon/kv_dpm.c

997

pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1000

table->entries[i].v = pi->max_vddc;

sys/dev/drm/radeon/ni_dpm.c

1099

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1108

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1113

pi->state_table_start = (u16)tmp;

sys/dev/drm/radeon/ni_dpm.c

1118

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1123

pi->soft_regs_start = (u16)tmp;

sys/dev/drm/radeon/ni_dpm.c

1128

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1138

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1148

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1158

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1168

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1202

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1204

if (pi->gfx_clock_gating) {

sys/dev/drm/radeon/ni_dpm.c

1272

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1283

if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {

sys/dev/drm/radeon/ni_dpm.c

1324

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1327

if (!pi->mvdd_control) {

sys/dev/drm/radeon/ni_dpm.c

1333

if (mclk <= pi->mvdd_split_frequency) {

sys/dev/drm/radeon/ni_dpm.c

1455

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1493

(u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +

sys/dev/drm/radeon/ni_dpm.c

1496

sizeof(u32) * 4, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1571

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1577

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1585

tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1595

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1601

&tmp, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1639

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1656

pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

1684

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1754

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/ni_dpm.c

1756

if (pi->boot_in_gen2)

sys/dev/drm/radeon/ni_dpm.c

1761

if (pi->mem_gddr5) {

sys/dev/drm/radeon/ni_dpm.c

1766

if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/ni_dpm.c

1793

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1813

if (pi->acpi_vddc) {

sys/dev/drm/radeon/ni_dpm.c

1816

pi->acpi_vddc, &table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/ni_dpm.c

1828

if (pi->pcie_gen2) {

sys/dev/drm/radeon/ni_dpm.c

1829

if (pi->acpi_pcie_gen2)

sys/dev/drm/radeon/ni_dpm.c

1839

pi->min_vddc_in_table,

sys/dev/drm/radeon/ni_dpm.c

1868

if (pi->mem_gddr5)

sys/dev/drm/radeon/ni_dpm.c

1940

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

1972

if (pi->mem_gddr5)

sys/dev/drm/radeon/ni_dpm.c

1992

return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,

sys/dev/drm/radeon/ni_dpm.c

1993

sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

2000

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2038

if (pi->sclk_ss) {

sys/dev/drm/radeon/ni_dpm.c

2090

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2151

sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

2165

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2211

if (pi->mem_gddr5) {

sys/dev/drm/radeon/ni_dpm.c

2234

if (pi->mclk_ss) {

sys/dev/drm/radeon/ni_dpm.c

2258

dll_speed = rv740_get_dll_speed(pi->mem_gddr5,

sys/dev/drm/radeon/ni_dpm.c

2301

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2305

smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/ni_dpm.c

2308

cpu_to_be32(pi->psp);

sys/dev/drm/radeon/ni_dpm.c

2315

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2323

level->gen2PCIE = pi->pcie_gen2 ?

sys/dev/drm/radeon/ni_dpm.c

2331

if (pi->mclk_stutter_mode_threshold &&

sys/dev/drm/radeon/ni_dpm.c

2332

(pl->mclk <= pi->mclk_stutter_mode_threshold) &&

sys/dev/drm/radeon/ni_dpm.c

2338

if (pi->mem_gddr5) {

sys/dev/drm/radeon/ni_dpm.c

2339

if (pl->mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/ni_dpm.c

2396

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2439

a_t |= CG_R(t_l * pi->bsp / 20000);

sys/dev/drm/radeon/ni_dpm.c

2443

pi->pbsp : pi->bsp;

sys/dev/drm/radeon/ni_dpm.c

2456

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2489

pi->state_table_start +

sys/dev/drm/radeon/ni_dpm.c

2493

pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

2688

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2689

u16 address = pi->state_table_start +

sys/dev/drm/radeon/ni_dpm.c

2703

ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

2714

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

2741

if (!pi->mem_gddr5)

sys/dev/drm/radeon/ni_dpm.c

2995

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3020

pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

3026

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3043

pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

3141

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3195

sizeof(PP_NIslands_CACTABLES), pi->sram_end);

sys/dev/drm/radeon/ni_dpm.c

3441

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3448

pi->pcie_gen2 = true;

sys/dev/drm/radeon/ni_dpm.c

3450

pi->pcie_gen2 = false;

sys/dev/drm/radeon/ni_dpm.c

3452

if (!pi->pcie_gen2)

sys/dev/drm/radeon/ni_dpm.c

3461

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3469

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/ni_dpm.c

3484

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/ni_dpm.c

3587

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3592

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/ni_dpm.c

3596

if (pi->mg_clock_gating)

sys/dev/drm/radeon/ni_dpm.c

3600

if (pi->voltage_control) {

sys/dev/drm/radeon/ni_dpm.c

3613

if (pi->dynamic_ss)

sys/dev/drm/radeon/ni_dpm.c

3615

if (pi->thermal_protection)

sys/dev/drm/radeon/ni_dpm.c

3624

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/ni_dpm.c

3689

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/ni_dpm.c

3691

if (pi->mg_clock_gating)

sys/dev/drm/radeon/ni_dpm.c

3705

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3712

if (pi->thermal_protection)

sys/dev/drm/radeon/ni_dpm.c

3718

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/ni_dpm.c

3727

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/ni_dpm.c

3729

if (pi->mg_clock_gating)

sys/dev/drm/radeon/ni_dpm.c

3924

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

3942

if (pi->max_vddc)

sys/dev/drm/radeon/ni_dpm.c

3943

pl->vddc = pi->max_vddc;

sys/dev/drm/radeon/ni_dpm.c

3947

pi->acpi_vddc = pl->vddc;

sys/dev/drm/radeon/ni_dpm.c

3950

pi->acpi_pcie_gen2 = true;

sys/dev/drm/radeon/ni_dpm.c

3952

pi->acpi_pcie_gen2 = false;

sys/dev/drm/radeon/ni_dpm.c

3960

if (pi->min_vddc_in_table > pl->vddc)

sys/dev/drm/radeon/ni_dpm.c

3961

pi->min_vddc_in_table = pl->vddc;

sys/dev/drm/radeon/ni_dpm.c

3963

if (pi->max_vddc_in_table < pl->vddc)

sys/dev/drm/radeon/ni_dpm.c

3964

pi->max_vddc_in_table = pl->vddc;

sys/dev/drm/radeon/ni_dpm.c

4047

struct rv7xx_power_info *pi;

sys/dev/drm/radeon/ni_dpm.c

4058

pi = &eg_pi->rv7xx;

sys/dev/drm/radeon/ni_dpm.c

4063

pi->acpi_vddc = 0;

sys/dev/drm/radeon/ni_dpm.c

4065

pi->min_vddc_in_table = 0;

sys/dev/drm/radeon/ni_dpm.c

4066

pi->max_vddc_in_table = 0;

sys/dev/drm/radeon/ni_dpm.c

4105

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/ni_dpm.c

4107

pi->ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4109

pi->rlp = RV770_RLP_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4110

pi->rmp = RV770_RMP_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4111

pi->lhp = RV770_LHP_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4112

pi->lmp = RV770_LMP_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4127

pi->mclk_strobe_mode_threshold = 55000;

sys/dev/drm/radeon/ni_dpm.c

4128

pi->mclk_edc_enable_threshold = 55000;

sys/dev/drm/radeon/ni_dpm.c

4131

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/radeon/ni_dpm.c

4132

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/radeon/ni_dpm.c

4137

pi->voltage_control =

sys/dev/drm/radeon/ni_dpm.c

4140

pi->mvdd_control =

sys/dev/drm/radeon/ni_dpm.c

4148

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4149

pi->pasi = CYPRESS_HASI_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4150

pi->vrc = CYPRESS_VRC_DFLT;

sys/dev/drm/radeon/ni_dpm.c

4152

pi->power_gating = false;

sys/dev/drm/radeon/ni_dpm.c

4154

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/ni_dpm.c

4156

pi->mg_clock_gating = true;

sys/dev/drm/radeon/ni_dpm.c

4157

pi->mgcgtssm = true;

sys/dev/drm/radeon/ni_dpm.c

4161

pi->dynamic_pcie_gen2 = true;

sys/dev/drm/radeon/ni_dpm.c

4164

pi->thermal_protection = true;

sys/dev/drm/radeon/ni_dpm.c

4166

pi->thermal_protection = false;

sys/dev/drm/radeon/ni_dpm.c

4168

pi->display_gap = true;

sys/dev/drm/radeon/ni_dpm.c

4170

pi->dcodt = true;

sys/dev/drm/radeon/ni_dpm.c

4172

pi->ulps = true;

sys/dev/drm/radeon/ni_dpm.c

4190

pi->mclk_stutter_mode_threshold = 0;

sys/dev/drm/radeon/ni_dpm.c

4192

pi->sram_end = SMC_RAM_END;

sys/dev/drm/radeon/ni_dpm.c

728

struct ni_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/ni_dpm.c

730

return pi;

sys/dev/drm/radeon/ni_dpm.c

773

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

776

u32 switch_limit = pi->mem_gddr5 ? 450 : 0;

sys/dev/drm/radeon/ni_dpm.c

992

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/ni_dpm.c

998

if (pi->max_vddc == 0)

sys/dev/drm/radeon/rs780_dpm.c

1021

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

1023

return pi->bootup_uma_clk;

sys/dev/drm/radeon/rs780_dpm.c

1029

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

1039

if (pi->voltage_control)

sys/dev/drm/radeon/rs780_dpm.c

1040

rs780_force_voltage(rdev, pi->max_voltage);

sys/dev/drm/radeon/rs780_dpm.c

1056

if (pi->voltage_control)

sys/dev/drm/radeon/rs780_dpm.c

1057

rs780_force_voltage(rdev, pi->min_voltage);

sys/dev/drm/radeon/rs780_dpm.c

1059

if (pi->voltage_control)

sys/dev/drm/radeon/rs780_dpm.c

1060

rs780_force_voltage(rdev, pi->max_voltage);

sys/dev/drm/radeon/rs780_dpm.c

1067

if (pi->voltage_control) {

sys/dev/drm/radeon/rs780_dpm.c

224

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

244

if (pi->pwm_voltage_control) {

sys/dev/drm/radeon/rs780_dpm.c

245

fv_throt_pwm_range[0] = pi->min_voltage;

sys/dev/drm/radeon/rs780_dpm.c

246

fv_throt_pwm_range[1] = pi->min_voltage;

sys/dev/drm/radeon/rs780_dpm.c

247

fv_throt_pwm_range[2] = pi->max_voltage;

sys/dev/drm/radeon/rs780_dpm.c

248

fv_throt_pwm_range[3] = pi->max_voltage;

sys/dev/drm/radeon/rs780_dpm.c

250

fv_throt_pwm_range[0] = pi->invert_pwm_required ?

sys/dev/drm/radeon/rs780_dpm.c

252

fv_throt_pwm_range[1] = pi->invert_pwm_required ?

sys/dev/drm/radeon/rs780_dpm.c

254

fv_throt_pwm_range[2] = pi->invert_pwm_required ?

sys/dev/drm/radeon/rs780_dpm.c

256

fv_throt_pwm_range[3] = pi->invert_pwm_required ?

sys/dev/drm/radeon/rs780_dpm.c

261

STARTING_PWM_HIGHTIME(pi->max_voltage),

sys/dev/drm/radeon/rs780_dpm.c

265

NUMBER_OF_CYCLES_IN_PERIOD(pi->num_of_cycles_in_period),

sys/dev/drm/radeon/rs780_dpm.c

271

if (pi->invert_pwm_required)

sys/dev/drm/radeon/rs780_dpm.c

279

(MIN_PWM_HIGHTIME(pi->min_voltage) |

sys/dev/drm/radeon/rs780_dpm.c

280

MAX_PWM_HIGHTIME(pi->max_voltage)));

sys/dev/drm/radeon/rs780_dpm.c

364

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

366

WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

367

WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

368

WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

369

WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

370

WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

43

struct igp_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/rs780_dpm.c

45

return pi;

sys/dev/drm/radeon/rs780_dpm.c

479

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

485

if (pi->crtc_id == 0)

sys/dev/drm/radeon/rs780_dpm.c

50

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

512

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

515

return pi->max_voltage;

sys/dev/drm/radeon/rs780_dpm.c

517

return pi->min_voltage;

sys/dev/drm/radeon/rs780_dpm.c

519

return pi->max_voltage;

sys/dev/drm/radeon/rs780_dpm.c

526

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

549

if (pi->max_voltage != vddc_high) {

sys/dev/drm/radeon/rs780_dpm.c

57

pi->crtc_id = 0;

sys/dev/drm/radeon/rs780_dpm.c

58

pi->refresh_rate = 60;

sys/dev/drm/radeon/rs780_dpm.c

599

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

615

if (pi->voltage_control)

sys/dev/drm/radeon/rs780_dpm.c

624

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rs780_dpm.c

632

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

639

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rs780_dpm.c

64

pi->crtc_id = radeon_crtc->crtc_id;

sys/dev/drm/radeon/rs780_dpm.c

651

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

66

pi->refresh_rate = drm_mode_vrefresh(&crtc->mode);

sys/dev/drm/radeon/rs780_dpm.c

660

if (pi->voltage_control) {

sys/dev/drm/radeon/rs780_dpm.c

661

rs780_force_voltage(rdev, pi->max_voltage);

sys/dev/drm/radeon/rs780_dpm.c

672

if (pi->voltage_control)

sys/dev/drm/radeon/rs780_dpm.c

848

struct igp_power_info *pi;

sys/dev/drm/radeon/rs780_dpm.c

855

pi = kzalloc(sizeof(struct igp_power_info), GFP_KERNEL);

sys/dev/drm/radeon/rs780_dpm.c

856

if (pi == NULL)

sys/dev/drm/radeon/rs780_dpm.c

858

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/rs780_dpm.c

868

pi->voltage_control = false;

sys/dev/drm/radeon/rs780_dpm.c

869

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/rs780_dpm.c

878

pi->num_of_cycles_in_period =

sys/dev/drm/radeon/rs780_dpm.c

880

pi->num_of_cycles_in_period |=

sys/dev/drm/radeon/rs780_dpm.c

882

pi->invert_pwm_required =

sys/dev/drm/radeon/rs780_dpm.c

883

(pi->num_of_cycles_in_period & 0x8000) ? true : false;

sys/dev/drm/radeon/rs780_dpm.c

884

pi->boot_voltage = info->info.ucStartingPWM_HighTime;

sys/dev/drm/radeon/rs780_dpm.c

885

pi->max_voltage = info->info.ucMaxNBVoltage;

sys/dev/drm/radeon/rs780_dpm.c

886

pi->max_voltage |= info->info.ucMaxNBVoltageHigh << 8;

sys/dev/drm/radeon/rs780_dpm.c

887

pi->min_voltage = info->info.ucMinNBVoltage;

sys/dev/drm/radeon/rs780_dpm.c

888

pi->min_voltage |= info->info.ucMinNBVoltageHigh << 8;

sys/dev/drm/radeon/rs780_dpm.c

889

pi->inter_voltage_low =

sys/dev/drm/radeon/rs780_dpm.c

891

pi->inter_voltage_high =

sys/dev/drm/radeon/rs780_dpm.c

893

pi->voltage_control = true;

sys/dev/drm/radeon/rs780_dpm.c

894

pi->bootup_uma_clk = info->info.usK8MemoryClock * 100;

sys/dev/drm/radeon/rs780_dpm.c

897

pi->num_of_cycles_in_period =

sys/dev/drm/radeon/rs780_dpm.c

899

pi->invert_pwm_required =

sys/dev/drm/radeon/rs780_dpm.c

900

(pi->num_of_cycles_in_period & 0x8000) ? true : false;

sys/dev/drm/radeon/rs780_dpm.c

901

pi->boot_voltage =

sys/dev/drm/radeon/rs780_dpm.c

903

pi->max_voltage =

sys/dev/drm/radeon/rs780_dpm.c

905

pi->min_voltage =

sys/dev/drm/radeon/rs780_dpm.c

907

pi->system_config =

sys/dev/drm/radeon/rs780_dpm.c

909

pi->pwm_voltage_control =

sys/dev/drm/radeon/rs780_dpm.c

910

(pi->system_config & 0x4) ? true : false;

sys/dev/drm/radeon/rs780_dpm.c

911

pi->voltage_control = true;

sys/dev/drm/radeon/rs780_dpm.c

912

pi->bootup_uma_clk = le32_to_cpu(info->info_2.ulBootUpUMAClock);

sys/dev/drm/radeon/rs780_dpm.c

918

if (pi->min_voltage > pi->max_voltage)

sys/dev/drm/radeon/rs780_dpm.c

919

pi->voltage_control = false;

sys/dev/drm/radeon/rs780_dpm.c

920

if (pi->pwm_voltage_control) {

sys/dev/drm/radeon/rs780_dpm.c

921

if ((pi->num_of_cycles_in_period == 0) ||

sys/dev/drm/radeon/rs780_dpm.c

922

(pi->max_voltage == 0) ||

sys/dev/drm/radeon/rs780_dpm.c

923

(pi->min_voltage == 0))

sys/dev/drm/radeon/rs780_dpm.c

924

pi->voltage_control = false;

sys/dev/drm/radeon/rs780_dpm.c

926

if ((pi->num_of_cycles_in_period == 0) ||

sys/dev/drm/radeon/rs780_dpm.c

927

(pi->max_voltage == 0))

sys/dev/drm/radeon/rs780_dpm.c

928

pi->voltage_control = false;

sys/dev/drm/radeon/rs780_dpm.c

975

struct igp_power_info *pi = rs780_get_pi(rdev);

sys/dev/drm/radeon/rs780_dpm.c

977

return pi->bootup_uma_clk;

sys/dev/drm/radeon/rv6xx_dpm.c

1022

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1024

pi->hw.lp[0] = 0;

sys/dev/drm/radeon/rv6xx_dpm.c

1025

pi->hw.rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS - 1]

sys/dev/drm/radeon/rv6xx_dpm.c

1033

&pi->hw.lp[1],

sys/dev/drm/radeon/rv6xx_dpm.c

1034

&pi->hw.rp[0]);

sys/dev/drm/radeon/rv6xx_dpm.c

1041

&pi->hw.lp[2],

sys/dev/drm/radeon/rv6xx_dpm.c

1042

&pi->hw.rp[1]);

sys/dev/drm/radeon/rv6xx_dpm.c

1059

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1062

if (pi->voltage_control)

sys/dev/drm/radeon/rv6xx_dpm.c

1072

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1075

if (pi->voltage_control)

sys/dev/drm/radeon/rv6xx_dpm.c

1083

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1086

pi->hw.low_vddc_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1088

pi->hw.low_mclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1090

pi->hw.low_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1094

pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);

sys/dev/drm/radeon/rv6xx_dpm.c

1099

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1109

pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);

sys/dev/drm/radeon/rv6xx_dpm.c

1115

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1118

pi->hw.medium_vddc_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1120

pi->hw.medium_mclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1122

pi->hw.medium_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1126

pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM]);

sys/dev/drm/radeon/rv6xx_dpm.c

1131

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1135

pi->hw.mclks[pi->hw.low_mclk_index]);

sys/dev/drm/radeon/rv6xx_dpm.c

1142

pi->hw.medium_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1150

pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW]);

sys/dev/drm/radeon/rv6xx_dpm.c

1155

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1158

pi->hw.high_vddc_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1160

pi->hw.high_mclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1162

pi->hw.high_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1168

pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH]);

sys/dev/drm/radeon/rv6xx_dpm.c

1337

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1339

if ((pi->restricted_levels < 1) ||

sys/dev/drm/radeon/rv6xx_dpm.c

1340

(pi->restricted_levels == 3))

sys/dev/drm/radeon/rv6xx_dpm.c

1346

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1348

if (pi->restricted_levels < 2)

sys/dev/drm/radeon/rv6xx_dpm.c

1354

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1382

if (pi->thermal_protection)

sys/dev/drm/radeon/rv6xx_dpm.c

1393

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1396

if (!(pi->active_auto_throttle_sources & (1 << source))) {

sys/dev/drm/radeon/rv6xx_dpm.c

1397

pi->active_auto_throttle_sources |= 1 << source;

sys/dev/drm/radeon/rv6xx_dpm.c

1398

rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/rv6xx_dpm.c

1401

if (pi->active_auto_throttle_sources & (1 << source)) {

sys/dev/drm/radeon/rv6xx_dpm.c

1402

pi->active_auto_throttle_sources &= ~(1 << source);

sys/dev/drm/radeon/rv6xx_dpm.c

1403

rv6xx_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/rv6xx_dpm.c

1412

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1414

if (pi->active_auto_throttle_sources)

sys/dev/drm/radeon/rv6xx_dpm.c

1424

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1429

0, &pi->hw.medium_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1436

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1438

pi->hw.low_sclk_index = 0;

sys/dev/drm/radeon/rv6xx_dpm.c

1446

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1449

pi->hw.medium_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1456

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1458

pi->hw.low_sclk_index = 0;

sys/dev/drm/radeon/rv6xx_dpm.c

1464

&pi->hw.medium_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1468

pi->hw.medium_sclk_index,

sys/dev/drm/radeon/rv6xx_dpm.c

1469

&pi->hw.high_sclk_index);

sys/dev/drm/radeon/rv6xx_dpm.c

1548

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1557

if (pi->dynamic_ss)

sys/dev/drm/radeon/rv6xx_dpm.c

1572

if (pi->display_gap == false)

sys/dev/drm/radeon/rv6xx_dpm.c

1579

if (pi->voltage_control)

sys/dev/drm/radeon/rv6xx_dpm.c

1601

if (pi->voltage_control)

sys/dev/drm/radeon/rv6xx_dpm.c

1604

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/rv6xx_dpm.c

1607

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rv6xx_dpm.c

1615

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1627

if (pi->thermal_protection)

sys/dev/drm/radeon/rv6xx_dpm.c

163

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1639

if (pi->voltage_control)

sys/dev/drm/radeon/rv6xx_dpm.c

1642

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/rv6xx_dpm.c

1651

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rv6xx_dpm.c

1659

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

1664

pi->restricted_levels = 0;

sys/dev/drm/radeon/rv6xx_dpm.c

1672

if (pi->thermal_protection)

sys/dev/drm/radeon/rv6xx_dpm.c

168

pi->spll_ref_div,

sys/dev/drm/radeon/rv6xx_dpm.c

1682

if (pi->voltage_control) {

sys/dev/drm/radeon/rv6xx_dpm.c

1691

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/rv6xx_dpm.c

1694

if (pi->voltage_control)

sys/dev/drm/radeon/rv6xx_dpm.c

1700

if (pi->voltage_control) {

sys/dev/drm/radeon/rv6xx_dpm.c

1720

if (pi->voltage_control) {

sys/dev/drm/radeon/rv6xx_dpm.c

1732

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/rv6xx_dpm.c

1745

if (pi->thermal_protection)

sys/dev/drm/radeon/rv6xx_dpm.c

184

fb_divider = ((step->vco_frequency * pi->spll_ref_div) / ref_clk) >>

sys/dev/drm/radeon/rv6xx_dpm.c

185

pi->fb_div_scale;

sys/dev/drm/radeon/rv6xx_dpm.c

188

pi->spll_ref_div - 1);

sys/dev/drm/radeon/rv6xx_dpm.c

1936

struct rv6xx_power_info *pi;

sys/dev/drm/radeon/rv6xx_dpm.c

1939

pi = kzalloc(sizeof(struct rv6xx_power_info), GFP_KERNEL);

sys/dev/drm/radeon/rv6xx_dpm.c

1940

if (pi == NULL)

sys/dev/drm/radeon/rv6xx_dpm.c

1942

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/rv6xx_dpm.c

1960

pi->spll_ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/rv6xx_dpm.c

1962

pi->spll_ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/rv6xx_dpm.c

1967

pi->mpll_ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/rv6xx_dpm.c

1969

pi->mpll_ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/rv6xx_dpm.c

1972

pi->fb_div_scale = 1;

sys/dev/drm/radeon/rv6xx_dpm.c

1974

pi->fb_div_scale = 0;

sys/dev/drm/radeon/rv6xx_dpm.c

1976

pi->voltage_control =

sys/dev/drm/radeon/rv6xx_dpm.c

1979

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/rv6xx_dpm.c

1981

pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,

sys/dev/drm/radeon/rv6xx_dpm.c

1983

pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,

sys/dev/drm/radeon/rv6xx_dpm.c

1987

pi->sclk_ss = false;

sys/dev/drm/radeon/rv6xx_dpm.c

1989

if (pi->sclk_ss || pi->mclk_ss)

sys/dev/drm/radeon/rv6xx_dpm.c

1990

pi->dynamic_ss = true;

sys/dev/drm/radeon/rv6xx_dpm.c

1992

pi->dynamic_ss = false;

sys/dev/drm/radeon/rv6xx_dpm.c

1994

pi->dynamic_pcie_gen2 = true;

sys/dev/drm/radeon/rv6xx_dpm.c

1996

if (pi->gfx_clock_gating &&

sys/dev/drm/radeon/rv6xx_dpm.c

1998

pi->thermal_protection = true;

sys/dev/drm/radeon/rv6xx_dpm.c

2000

pi->thermal_protection = false;

sys/dev/drm/radeon/rv6xx_dpm.c

2002

pi->display_gap = true;

sys/dev/drm/radeon/rv6xx_dpm.c

2133

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

2136

pi->restricted_levels = 3;

sys/dev/drm/radeon/rv6xx_dpm.c

2138

pi->restricted_levels = 2;

sys/dev/drm/radeon/rv6xx_dpm.c

2140

pi->restricted_levels = 0;

sys/dev/drm/radeon/rv6xx_dpm.c

2151

if (pi->restricted_levels == 3)

sys/dev/drm/radeon/rv6xx_dpm.c

437

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

439

pi->hw.sclks[R600_POWER_LEVEL_LOW] =

sys/dev/drm/radeon/rv6xx_dpm.c

441

pi->hw.sclks[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

443

pi->hw.sclks[R600_POWER_LEVEL_HIGH] =

sys/dev/drm/radeon/rv6xx_dpm.c

446

pi->hw.low_sclk_index = R600_POWER_LEVEL_LOW;

sys/dev/drm/radeon/rv6xx_dpm.c

447

pi->hw.medium_sclk_index = R600_POWER_LEVEL_MEDIUM;

sys/dev/drm/radeon/rv6xx_dpm.c

448

pi->hw.high_sclk_index = R600_POWER_LEVEL_HIGH;

sys/dev/drm/radeon/rv6xx_dpm.c

454

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

456

pi->hw.mclks[R600_POWER_LEVEL_CTXSW] =

sys/dev/drm/radeon/rv6xx_dpm.c

458

pi->hw.mclks[R600_POWER_LEVEL_HIGH] =

sys/dev/drm/radeon/rv6xx_dpm.c

46

struct rv6xx_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/rv6xx_dpm.c

460

pi->hw.mclks[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

462

pi->hw.mclks[R600_POWER_LEVEL_LOW] =

sys/dev/drm/radeon/rv6xx_dpm.c

465

pi->hw.high_mclk_index = R600_POWER_LEVEL_HIGH;

sys/dev/drm/radeon/rv6xx_dpm.c

468

pi->hw.medium_mclk_index =

sys/dev/drm/radeon/rv6xx_dpm.c

469

pi->hw.high_mclk_index;

sys/dev/drm/radeon/rv6xx_dpm.c

471

pi->hw.medium_mclk_index = R600_POWER_LEVEL_MEDIUM;

sys/dev/drm/radeon/rv6xx_dpm.c

475

pi->hw.low_mclk_index =

sys/dev/drm/radeon/rv6xx_dpm.c

476

pi->hw.medium_mclk_index;

sys/dev/drm/radeon/rv6xx_dpm.c

478

pi->hw.low_mclk_index = R600_POWER_LEVEL_LOW;

sys/dev/drm/radeon/rv6xx_dpm.c

48

return pi;

sys/dev/drm/radeon/rv6xx_dpm.c

484

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

486

pi->hw.vddc[R600_POWER_LEVEL_CTXSW] = state->high.vddc;

sys/dev/drm/radeon/rv6xx_dpm.c

487

pi->hw.vddc[R600_POWER_LEVEL_HIGH] = state->high.vddc;

sys/dev/drm/radeon/rv6xx_dpm.c

488

pi->hw.vddc[R600_POWER_LEVEL_MEDIUM] = state->medium.vddc;

sys/dev/drm/radeon/rv6xx_dpm.c

489

pi->hw.vddc[R600_POWER_LEVEL_LOW] = state->low.vddc;

sys/dev/drm/radeon/rv6xx_dpm.c

491

pi->hw.backbias[R600_POWER_LEVEL_CTXSW] =

sys/dev/drm/radeon/rv6xx_dpm.c

493

pi->hw.backbias[R600_POWER_LEVEL_HIGH] =

sys/dev/drm/radeon/rv6xx_dpm.c

495

pi->hw.backbias[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

497

pi->hw.backbias[R600_POWER_LEVEL_LOW] =

sys/dev/drm/radeon/rv6xx_dpm.c

500

pi->hw.pcie_gen2[R600_POWER_LEVEL_HIGH] =

sys/dev/drm/radeon/rv6xx_dpm.c

502

pi->hw.pcie_gen2[R600_POWER_LEVEL_MEDIUM] =

sys/dev/drm/radeon/rv6xx_dpm.c

504

pi->hw.pcie_gen2[R600_POWER_LEVEL_LOW] =

sys/dev/drm/radeon/rv6xx_dpm.c

507

pi->hw.high_vddc_index = R600_POWER_LEVEL_HIGH;

sys/dev/drm/radeon/rv6xx_dpm.c

512

pi->hw.medium_vddc_index =

sys/dev/drm/radeon/rv6xx_dpm.c

513

pi->hw.high_vddc_index;

sys/dev/drm/radeon/rv6xx_dpm.c

515

pi->hw.medium_vddc_index = R600_POWER_LEVEL_MEDIUM;

sys/dev/drm/radeon/rv6xx_dpm.c

520

pi->hw.low_vddc_index =

sys/dev/drm/radeon/rv6xx_dpm.c

521

pi->hw.medium_vddc_index;

sys/dev/drm/radeon/rv6xx_dpm.c

523

pi->hw.medium_vddc_index = R600_POWER_LEVEL_LOW;

sys/dev/drm/radeon/rv6xx_dpm.c

553

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

560

if (clock && pi->sclk_ss) {

sys/dev/drm/radeon/rv6xx_dpm.c

563

pi->fb_div_scale);

sys/dev/drm/radeon/rv6xx_dpm.c

571

pi->fb_div_scale);

sys/dev/drm/radeon/rv6xx_dpm.c

586

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

589

pi->hw.sclks[R600_POWER_LEVEL_HIGH],

sys/dev/drm/radeon/rv6xx_dpm.c

593

pi->hw.sclks[R600_POWER_LEVEL_MEDIUM],

sys/dev/drm/radeon/rv6xx_dpm.c

621

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

625

if (pi->hw.mclks[i])

sys/dev/drm/radeon/rv6xx_dpm.c

627

pi->hw.mclks[i]);

sys/dev/drm/radeon/rv6xx_dpm.c

637

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

644

pi->fb_div_scale);

sys/dev/drm/radeon/rv6xx_dpm.c

655

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

663

if (pi->mclk_ss) {

sys/dev/drm/radeon/rv6xx_dpm.c

665

pi->hw.mclks[pi->hw.high_mclk_index],

sys/dev/drm/radeon/rv6xx_dpm.c

671

pi->hw.mclks[pi->hw.medium_mclk_index],

sys/dev/drm/radeon/rv6xx_dpm.c

677

pi->hw.mclks[pi->hw.low_mclk_index],

sys/dev/drm/radeon/rv6xx_dpm.c

689

pi->fb_div_scale);

sys/dev/drm/radeon/rv6xx_dpm.c

721

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

726

pi->hw.vddc[i]);

sys/dev/drm/radeon/rv6xx_dpm.c

732

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

734

if (pi->hw.backbias[1])

sys/dev/drm/radeon/rv6xx_dpm.c

739

if (pi->hw.backbias[2])

sys/dev/drm/radeon/rv6xx_dpm.c

747

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

750

pi->hw.sclks[R600_POWER_LEVEL_LOW],

sys/dev/drm/radeon/rv6xx_dpm.c

756

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

758

if (pi->hw.mclks[0])

sys/dev/drm/radeon/rv6xx_dpm.c

760

pi->hw.mclks[0]);

sys/dev/drm/radeon/rv6xx_dpm.c

765

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

768

pi->hw.vddc[0]);

sys/dev/drm/radeon/rv6xx_dpm.c

774

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

776

if (pi->hw.backbias[0])

sys/dev/drm/radeon/rv6xx_dpm.c

797

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

802

if (pi->hw.sclks[R600_POWER_LEVEL_HIGH] <

sys/dev/drm/radeon/rv6xx_dpm.c

803

(pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40))

sys/dev/drm/radeon/rv6xx_dpm.c

804

high_clock = pi->hw.sclks[R600_POWER_LEVEL_HIGH];

sys/dev/drm/radeon/rv6xx_dpm.c

807

pi->hw.sclks[R600_POWER_LEVEL_LOW] * 0xFF / 0x40;

sys/dev/drm/radeon/rv6xx_dpm.c

811

sqm_ratio = (STATE0(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_LOW]) |

sys/dev/drm/radeon/rv6xx_dpm.c

812

STATE1(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_MEDIUM]) |

sys/dev/drm/radeon/rv6xx_dpm.c

813

STATE2(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]) |

sys/dev/drm/radeon/rv6xx_dpm.c

814

STATE3(64 * high_clock / pi->hw.sclks[R600_POWER_LEVEL_HIGH]));

sys/dev/drm/radeon/rv6xx_dpm.c

819

pi->hw.sclks[R600_POWER_LEVEL_LOW])) |

sys/dev/drm/radeon/rv6xx_dpm.c

821

pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |

sys/dev/drm/radeon/rv6xx_dpm.c

823

pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |

sys/dev/drm/radeon/rv6xx_dpm.c

825

pi->hw.sclks[R600_POWER_LEVEL_HIGH])));

sys/dev/drm/radeon/rv6xx_dpm.c

831

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

834

pi->mpll_ref_div);

sys/dev/drm/radeon/rv6xx_dpm.c

840

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

845

&pi->bsp,

sys/dev/drm/radeon/rv6xx_dpm.c

846

&pi->bsu);

sys/dev/drm/radeon/rv6xx_dpm.c

848

r600_set_bsp(rdev, pi->bsu, pi->bsp);

sys/dev/drm/radeon/rv6xx_dpm.c

853

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

856

(pi->hw.rp[0] * pi->bsp) / 200,

sys/dev/drm/radeon/rv6xx_dpm.c

857

(pi->hw.rp[1] * pi->bsp) / 200,

sys/dev/drm/radeon/rv6xx_dpm.c

858

(pi->hw.lp[2] * pi->bsp) / 200,

sys/dev/drm/radeon/rv6xx_dpm.c

859

(pi->hw.lp[1] * pi->bsp) / 200);

sys/dev/drm/radeon/rv6xx_dpm.c

940

struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);

sys/dev/drm/radeon/rv6xx_dpm.c

949

pi->hw.vddc[i],

sys/dev/drm/radeon/rv730_dpm.c

123

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

124

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv730_dpm.c

125

u32 dll_cntl = pi->clk_regs.rv730.dll_cntl;

sys/dev/drm/radeon/rv730_dpm.c

126

u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

127

u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;

sys/dev/drm/radeon/rv730_dpm.c

128

u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;

sys/dev/drm/radeon/rv730_dpm.c

129

u32 mpll_ss = pi->clk_regs.rv730.mpll_ss;

sys/dev/drm/radeon/rv730_dpm.c

130

u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2;

sys/dev/drm/radeon/rv730_dpm.c

166

if (pi->mclk_ss) {

sys/dev/drm/radeon/rv730_dpm.c

200

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

202

pi->clk_regs.rv730.cg_spll_func_cntl =

sys/dev/drm/radeon/rv730_dpm.c

204

pi->clk_regs.rv730.cg_spll_func_cntl_2 =

sys/dev/drm/radeon/rv730_dpm.c

206

pi->clk_regs.rv730.cg_spll_func_cntl_3 =

sys/dev/drm/radeon/rv730_dpm.c

208

pi->clk_regs.rv730.cg_spll_spread_spectrum =

sys/dev/drm/radeon/rv730_dpm.c

210

pi->clk_regs.rv730.cg_spll_spread_spectrum_2 =

sys/dev/drm/radeon/rv730_dpm.c

213

pi->clk_regs.rv730.mclk_pwrmgt_cntl =

sys/dev/drm/radeon/rv730_dpm.c

215

pi->clk_regs.rv730.dll_cntl =

sys/dev/drm/radeon/rv730_dpm.c

217

pi->clk_regs.rv730.mpll_func_cntl =

sys/dev/drm/radeon/rv730_dpm.c

219

pi->clk_regs.rv730.mpll_func_cntl2 =

sys/dev/drm/radeon/rv730_dpm.c

221

pi->clk_regs.rv730.mpll_func_cntl3 =

sys/dev/drm/radeon/rv730_dpm.c

223

pi->clk_regs.rv730.mpll_ss =

sys/dev/drm/radeon/rv730_dpm.c

225

pi->clk_regs.rv730.mpll_ss2 =

sys/dev/drm/radeon/rv730_dpm.c

232

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

245

if (pi->acpi_vddc) {

sys/dev/drm/radeon/rv730_dpm.c

246

rv770_populate_vddc_value(rdev, pi->acpi_vddc,

sys/dev/drm/radeon/rv730_dpm.c

248

table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ?

sys/dev/drm/radeon/rv730_dpm.c

249

pi->acpi_pcie_gen2 : 0;

sys/dev/drm/radeon/rv730_dpm.c

251

pi->acpi_pcie_gen2;

sys/dev/drm/radeon/rv730_dpm.c

253

rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,

sys/dev/drm/radeon/rv730_dpm.c

258

mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

259

mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2;

sys/dev/drm/radeon/rv730_dpm.c

260

mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3;

sys/dev/drm/radeon/rv730_dpm.c

287

spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

288

spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv730_dpm.c

289

spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv730_dpm.c

324

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

328

cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl);

sys/dev/drm/radeon/rv730_dpm.c

330

cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2);

sys/dev/drm/radeon/rv730_dpm.c

332

cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3);

sys/dev/drm/radeon/rv730_dpm.c

334

cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl);

sys/dev/drm/radeon/rv730_dpm.c

336

cpu_to_be32(pi->clk_regs.rv730.dll_cntl);

sys/dev/drm/radeon/rv730_dpm.c

338

cpu_to_be32(pi->clk_regs.rv730.mpll_ss);

sys/dev/drm/radeon/rv730_dpm.c

340

cpu_to_be32(pi->clk_regs.rv730.mpll_ss2);

sys/dev/drm/radeon/rv730_dpm.c

346

cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl);

sys/dev/drm/radeon/rv730_dpm.c

348

cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2);

sys/dev/drm/radeon/rv730_dpm.c

350

cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3);

sys/dev/drm/radeon/rv730_dpm.c

352

cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum);

sys/dev/drm/radeon/rv730_dpm.c

354

cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2);

sys/dev/drm/radeon/rv730_dpm.c

374

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/rv730_dpm.c

376

if (pi->boot_in_gen2)

sys/dev/drm/radeon/rv730_dpm.c

44

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

46

u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl;

sys/dev/drm/radeon/rv730_dpm.c

47

u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv730_dpm.c

478

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

48

u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv730_dpm.c

484

mc4_io_pad_cntl |= pi->odt_value_0[i];

sys/dev/drm/radeon/rv730_dpm.c

49

u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv730_dpm.c

490

mc4_io_pad_cntl |= pi->odt_value_1[i];

sys/dev/drm/radeon/rv730_dpm.c

497

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv730_dpm.c

50

u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv730_dpm.c

500

pi->odt_value_0[0] = (u8)0;

sys/dev/drm/radeon/rv730_dpm.c

501

pi->odt_value_1[0] = (u8)0x80;

sys/dev/drm/radeon/rv730_dpm.c

504

pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff);

sys/dev/drm/radeon/rv730_dpm.c

507

pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff);

sys/dev/drm/radeon/rv730_dpm.c

91

if (pi->sclk_ss) {

sys/dev/drm/radeon/rv740_dpm.c

124

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv740_dpm.c

126

u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

127

u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

128

u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv740_dpm.c

129

u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv740_dpm.c

130

u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv740_dpm.c

159

if (pi->sclk_ss) {

sys/dev/drm/radeon/rv740_dpm.c

191

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv740_dpm.c

192

u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

193

u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

194

u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

195

u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

196

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv740_dpm.c

197

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/rv740_dpm.c

198

u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;

sys/dev/drm/radeon/rv740_dpm.c

199

u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;

sys/dev/drm/radeon/rv740_dpm.c

228

if (pi->mem_gddr5) {

sys/dev/drm/radeon/rv740_dpm.c

246

if (pi->mclk_ss) {

sys/dev/drm/radeon/rv740_dpm.c

270

dll_speed = rv740_get_dll_speed(pi->mem_gddr5,

sys/dev/drm/radeon/rv740_dpm.c

291

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv740_dpm.c

293

pi->clk_regs.rv770.cg_spll_func_cntl =

sys/dev/drm/radeon/rv740_dpm.c

295

pi->clk_regs.rv770.cg_spll_func_cntl_2 =

sys/dev/drm/radeon/rv740_dpm.c

297

pi->clk_regs.rv770.cg_spll_func_cntl_3 =

sys/dev/drm/radeon/rv740_dpm.c

299

pi->clk_regs.rv770.cg_spll_spread_spectrum =

sys/dev/drm/radeon/rv740_dpm.c

301

pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =

sys/dev/drm/radeon/rv740_dpm.c

304

pi->clk_regs.rv770.mpll_ad_func_cntl =

sys/dev/drm/radeon/rv740_dpm.c

306

pi->clk_regs.rv770.mpll_ad_func_cntl_2 =

sys/dev/drm/radeon/rv740_dpm.c

308

pi->clk_regs.rv770.mpll_dq_func_cntl =

sys/dev/drm/radeon/rv740_dpm.c

310

pi->clk_regs.rv770.mpll_dq_func_cntl_2 =

sys/dev/drm/radeon/rv740_dpm.c

312

pi->clk_regs.rv770.mclk_pwrmgt_cntl =

sys/dev/drm/radeon/rv740_dpm.c

314

pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);

sys/dev/drm/radeon/rv740_dpm.c

315

pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1);

sys/dev/drm/radeon/rv740_dpm.c

316

pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2);

sys/dev/drm/radeon/rv740_dpm.c

322

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv740_dpm.c

323

u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

324

u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

325

u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

326

u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

327

u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/rv740_dpm.c

328

u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv740_dpm.c

329

u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv740_dpm.c

330

u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv740_dpm.c

331

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/rv740_dpm.c

337

if (pi->acpi_vddc) {

sys/dev/drm/radeon/rv740_dpm.c

338

rv770_populate_vddc_value(rdev, pi->acpi_vddc,

sys/dev/drm/radeon/rv740_dpm.c

341

pi->pcie_gen2 ?

sys/dev/drm/radeon/rv740_dpm.c

342

pi->acpi_pcie_gen2 : 0;

sys/dev/drm/radeon/rv740_dpm.c

344

pi->acpi_pcie_gen2;

sys/dev/drm/radeon/rv740_dpm.c

346

rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,

sys/dev/drm/radeon/rv770_dpm.c

1013

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1015

if ((pi->s0_vid_lower_smio_cntl & pi->mvdd_mask_low) ==

sys/dev/drm/radeon/rv770_dpm.c

1016

(pi->mvdd_low_smio[MVDD_LOW_INDEX] & pi->mvdd_mask_low) ) {

sys/dev/drm/radeon/rv770_dpm.c

1032

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1036

cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);

sys/dev/drm/radeon/rv770_dpm.c

1038

cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);

sys/dev/drm/radeon/rv770_dpm.c

1040

cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);

sys/dev/drm/radeon/rv770_dpm.c

1042

cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);

sys/dev/drm/radeon/rv770_dpm.c

1044

cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);

sys/dev/drm/radeon/rv770_dpm.c

1046

cpu_to_be32(pi->clk_regs.rv770.dll_cntl);

sys/dev/drm/radeon/rv770_dpm.c

1049

cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);

sys/dev/drm/radeon/rv770_dpm.c

1051

cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);

sys/dev/drm/radeon/rv770_dpm.c

1057

cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);

sys/dev/drm/radeon/rv770_dpm.c

1059

cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);

sys/dev/drm/radeon/rv770_dpm.c

1061

cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);

sys/dev/drm/radeon/rv770_dpm.c

1063

cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);

sys/dev/drm/radeon/rv770_dpm.c

1065

cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);

sys/dev/drm/radeon/rv770_dpm.c

1084

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/rv770_dpm.c

1086

if (pi->boot_in_gen2)

sys/dev/drm/radeon/rv770_dpm.c

1096

if (pi->mem_gddr5) {

sys/dev/drm/radeon/rv770_dpm.c

1097

if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold)

sys/dev/drm/radeon/rv770_dpm.c

1103

if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/rv770_dpm.c

1121

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1124

for (i = 0; i < pi->valid_vddc_entries; i++) {

sys/dev/drm/radeon/rv770_dpm.c

1125

table->highSMIO[pi->vddc_table[i].vddc_index] =

sys/dev/drm/radeon/rv770_dpm.c

1126

pi->vddc_table[i].high_smio;

sys/dev/drm/radeon/rv770_dpm.c

1127

table->lowSMIO[pi->vddc_table[i].vddc_index] =

sys/dev/drm/radeon/rv770_dpm.c

1128

cpu_to_be32(pi->vddc_table[i].low_smio);

sys/dev/drm/radeon/rv770_dpm.c

1133

cpu_to_be32(pi->vddc_mask_low);

sys/dev/drm/radeon/rv770_dpm.c

1136

((i < pi->valid_vddc_entries) &&

sys/dev/drm/radeon/rv770_dpm.c

1137

(pi->max_vddc_in_table >

sys/dev/drm/radeon/rv770_dpm.c

1138

pi->vddc_table[i].vddc));

sys/dev/drm/radeon/rv770_dpm.c

1142

pi->vddc_table[i].vddc_index;

sys/dev/drm/radeon/rv770_dpm.c

1150

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1152

if (pi->mvdd_control) {

sys/dev/drm/radeon/rv770_dpm.c

1154

cpu_to_be32(pi->mvdd_low_smio[MVDD_HIGH_INDEX]);

sys/dev/drm/radeon/rv770_dpm.c

1156

cpu_to_be32(pi->mvdd_low_smio[MVDD_LOW_INDEX]);

sys/dev/drm/radeon/rv770_dpm.c

1160

cpu_to_be32(pi->mvdd_mask_low);

sys/dev/drm/radeon/rv770_dpm.c

1169

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1171

RV770_SMC_STATETABLE *table = &pi->smc_statetable;

sys/dev/drm/radeon/rv770_dpm.c

1176

pi->boot_sclk = boot_state->low.sclk;

sys/dev/drm/radeon/rv770_dpm.c

1208

if (pi->mem_gddr5)

sys/dev/drm/radeon/rv770_dpm.c

1230

pi->state_table_start,

sys/dev/drm/radeon/rv770_dpm.c

1233

pi->sram_end);

sys/dev/drm/radeon/rv770_dpm.c

1238

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1256

pi->vddc_table[i].vddc = (u16)(min + i * step);

sys/dev/drm/radeon/rv770_dpm.c

1258

pi->vddc_table[i].vddc,

sys/dev/drm/radeon/rv770_dpm.c

1261

pi->vddc_table[i].low_smio = gpio_pins & gpio_mask;

sys/dev/drm/radeon/rv770_dpm.c

1262

pi->vddc_table[i].high_smio = 0;

sys/dev/drm/radeon/rv770_dpm.c

1263

pi->vddc_mask_low = gpio_mask;

sys/dev/drm/radeon/rv770_dpm.c

1265

if ((pi->vddc_table[i].low_smio !=

sys/dev/drm/radeon/rv770_dpm.c

1266

pi->vddc_table[i - 1].low_smio ) ||

sys/dev/drm/radeon/rv770_dpm.c

1267

(pi->vddc_table[i].high_smio !=

sys/dev/drm/radeon/rv770_dpm.c

1268

pi->vddc_table[i - 1].high_smio))

sys/dev/drm/radeon/rv770_dpm.c

1271

pi->vddc_table[i].vddc_index = vddc_index;

sys/dev/drm/radeon/rv770_dpm.c

1274

pi->valid_vddc_entries = (u8)steps;

sys/dev/drm/radeon/rv770_dpm.c

1289

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1295

pi->mvdd_mask_low = gpio_mask;

sys/dev/drm/radeon/rv770_dpm.c

1296

pi->mvdd_low_smio[MVDD_HIGH_INDEX] =

sys/dev/drm/radeon/rv770_dpm.c

1302

pi->mvdd_low_smio[MVDD_LOW_INDEX] =

sys/dev/drm/radeon/rv770_dpm.c

1315

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1322

pi->mvdd_control = false;

sys/dev/drm/radeon/rv770_dpm.c

1326

pi->mvdd_split_frequency =

sys/dev/drm/radeon/rv770_dpm.c

1329

if (pi->mvdd_split_frequency == 0) {

sys/dev/drm/radeon/rv770_dpm.c

1330

pi->mvdd_control = false;

sys/dev/drm/radeon/rv770_dpm.c

1389

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1390

u16 address = pi->state_table_start +

sys/dev/drm/radeon/rv770_dpm.c

1401

pi->sram_end);

sys/dev/drm/radeon/rv770_dpm.c

150

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1523

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1525

pi->clk_regs.rv770.cg_spll_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

1527

pi->clk_regs.rv770.cg_spll_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

1529

pi->clk_regs.rv770.cg_spll_func_cntl_3 =

sys/dev/drm/radeon/rv770_dpm.c

1531

pi->clk_regs.rv770.cg_spll_spread_spectrum =

sys/dev/drm/radeon/rv770_dpm.c

1533

pi->clk_regs.rv770.cg_spll_spread_spectrum_2 =

sys/dev/drm/radeon/rv770_dpm.c

1535

pi->clk_regs.rv770.mpll_ad_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

1537

pi->clk_regs.rv770.mpll_ad_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

1539

pi->clk_regs.rv770.mpll_dq_func_cntl =

sys/dev/drm/radeon/rv770_dpm.c

1541

pi->clk_regs.rv770.mpll_dq_func_cntl_2 =

sys/dev/drm/radeon/rv770_dpm.c

1543

pi->clk_regs.rv770.mclk_pwrmgt_cntl =

sys/dev/drm/radeon/rv770_dpm.c

1545

pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL);

sys/dev/drm/radeon/rv770_dpm.c

1560

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1562

pi->s0_vid_lower_smio_cntl =

sys/dev/drm/radeon/rv770_dpm.c

1568

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1586

vid_smio_cntl = pi->s0_vid_lower_smio_cntl;

sys/dev/drm/radeon/rv770_dpm.c

1596

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1603

pi->mem_gddr5 = true;

sys/dev/drm/radeon/rv770_dpm.c

1605

pi->mem_gddr5 = false;

sys/dev/drm/radeon/rv770_dpm.c

1611

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1618

pi->pcie_gen2 = true;

sys/dev/drm/radeon/rv770_dpm.c

1620

pi->pcie_gen2 = false;

sys/dev/drm/radeon/rv770_dpm.c

1622

if (pi->pcie_gen2) {

sys/dev/drm/radeon/rv770_dpm.c

1624

pi->boot_in_gen2 = true;

sys/dev/drm/radeon/rv770_dpm.c

1626

pi->boot_in_gen2 = false;

sys/dev/drm/radeon/rv770_dpm.c

1628

pi->boot_in_gen2 = false;

sys/dev/drm/radeon/rv770_dpm.c

163

if (pi->mgcgtssm)

sys/dev/drm/radeon/rv770_dpm.c

1634

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1636

if (pi->gfx_clock_gating) {

sys/dev/drm/radeon/rv770_dpm.c

1653

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1667

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rv770_dpm.c

1676

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1680

pi->mclk_odt_threshold = 0;

sys/dev/drm/radeon/rv770_dpm.c

1690

pi->mclk_odt_threshold = 30000;

sys/dev/drm/radeon/rv770_dpm.c

1696

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1700

pi->max_vddc = 0;

sys/dev/drm/radeon/rv770_dpm.c

1702

pi->max_vddc = vddc;

sys/dev/drm/radeon/rv770_dpm.c

1752

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1758

if (pi->mclk_odt_threshold == 0)

sys/dev/drm/radeon/rv770_dpm.c

1761

if (current_state->high.mclk <= pi->mclk_odt_threshold)

sys/dev/drm/radeon/rv770_dpm.c

1764

if (new_state->high.mclk <= pi->mclk_odt_threshold)

sys/dev/drm/radeon/rv770_dpm.c

1781

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1787

if (pi->mclk_odt_threshold == 0)

sys/dev/drm/radeon/rv770_dpm.c

1790

if (current_state->high.mclk <= pi->mclk_odt_threshold)

sys/dev/drm/radeon/rv770_dpm.c

1793

if (new_state->high.mclk <= pi->mclk_odt_threshold)

sys/dev/drm/radeon/rv770_dpm.c

1808

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1810

if (pi->mclk_odt_threshold == 0)

sys/dev/drm/radeon/rv770_dpm.c

1819

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1847

if (pi->thermal_protection)

sys/dev/drm/radeon/rv770_dpm.c

1858

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1861

if (!(pi->active_auto_throttle_sources & (1 << source))) {

sys/dev/drm/radeon/rv770_dpm.c

1862

pi->active_auto_throttle_sources |= 1 << source;

sys/dev/drm/radeon/rv770_dpm.c

1863

rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/rv770_dpm.c

1866

if (pi->active_auto_throttle_sources & (1 << source)) {

sys/dev/drm/radeon/rv770_dpm.c

1867

pi->active_auto_throttle_sources &= ~(1 << source);

sys/dev/drm/radeon/rv770_dpm.c

1868

rv770_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/rv770_dpm.c

1900

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

1904

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rv770_dpm.c

1910

if (pi->voltage_control) {

sys/dev/drm/radeon/rv770_dpm.c

1919

if (pi->dcodt)

sys/dev/drm/radeon/rv770_dpm.c

1922

if (pi->mvdd_control) {

sys/dev/drm/radeon/rv770_dpm.c

1935

if (pi->thermal_protection)

sys/dev/drm/radeon/rv770_dpm.c

1948

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/rv770_dpm.c

1970

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rv770_dpm.c

1973

if (pi->mg_clock_gating)

sys/dev/drm/radeon/rv770_dpm.c

2005

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2012

if (pi->thermal_protection)

sys/dev/drm/radeon/rv770_dpm.c

2017

if (pi->dynamic_pcie_gen2)

sys/dev/drm/radeon/rv770_dpm.c

2026

if (pi->gfx_clock_gating)

sys/dev/drm/radeon/rv770_dpm.c

2029

if (pi->mg_clock_gating)

sys/dev/drm/radeon/rv770_dpm.c

2043

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2065

if (pi->dcodt)

sys/dev/drm/radeon/rv770_dpm.c

2077

if (pi->dcodt)

sys/dev/drm/radeon/rv770_dpm.c

2087

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2091

if (pi->dcodt)

sys/dev/drm/radeon/rv770_dpm.c

2094

if (pi->dcodt)

sys/dev/drm/radeon/rv770_dpm.c

2101

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2106

if (pi->dcodt)

sys/dev/drm/radeon/rv770_dpm.c

2182

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2225

if (pi->max_vddc)

sys/dev/drm/radeon/rv770_dpm.c

2226

pl->vddc = pi->max_vddc;

sys/dev/drm/radeon/rv770_dpm.c

2230

pi->acpi_vddc = pl->vddc;

sys/dev/drm/radeon/rv770_dpm.c

2234

pi->acpi_pcie_gen2 = true;

sys/dev/drm/radeon/rv770_dpm.c

2236

pi->acpi_pcie_gen2 = false;

sys/dev/drm/radeon/rv770_dpm.c

2246

if (pi->min_vddc_in_table > pl->vddc)

sys/dev/drm/radeon/rv770_dpm.c

2247

pi->min_vddc_in_table = pl->vddc;

sys/dev/drm/radeon/rv770_dpm.c

2249

if (pi->max_vddc_in_table < pl->vddc)

sys/dev/drm/radeon/rv770_dpm.c

2250

pi->max_vddc_in_table = pl->vddc;

sys/dev/drm/radeon/rv770_dpm.c

2333

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2336

pi->sclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,

sys/dev/drm/radeon/rv770_dpm.c

2338

pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,

sys/dev/drm/radeon/rv770_dpm.c

2341

if (pi->sclk_ss || pi->mclk_ss)

sys/dev/drm/radeon/rv770_dpm.c

2342

pi->dynamic_ss = true;

sys/dev/drm/radeon/rv770_dpm.c

2344

pi->dynamic_ss = false;

sys/dev/drm/radeon/rv770_dpm.c

2349

struct rv7xx_power_info *pi;

sys/dev/drm/radeon/rv770_dpm.c

2353

pi = kzalloc(sizeof(struct rv7xx_power_info), GFP_KERNEL);

sys/dev/drm/radeon/rv770_dpm.c

2354

if (pi == NULL)

sys/dev/drm/radeon/rv770_dpm.c

2356

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/rv770_dpm.c

2360

pi->acpi_vddc = 0;

sys/dev/drm/radeon/rv770_dpm.c

2361

pi->min_vddc_in_table = 0;

sys/dev/drm/radeon/rv770_dpm.c

2362

pi->max_vddc_in_table = 0;

sys/dev/drm/radeon/rv770_dpm.c

2380

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/rv770_dpm.c

2382

pi->ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2384

pi->mclk_strobe_mode_threshold = 30000;

sys/dev/drm/radeon/rv770_dpm.c

2385

pi->mclk_edc_enable_threshold = 30000;

sys/dev/drm/radeon/rv770_dpm.c

2387

pi->rlp = RV770_RLP_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2388

pi->rmp = RV770_RMP_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2389

pi->lhp = RV770_LHP_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2390

pi->lmp = RV770_LMP_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2392

pi->voltage_control =

sys/dev/drm/radeon/rv770_dpm.c

2395

pi->mvdd_control =

sys/dev/drm/radeon/rv770_dpm.c

2400

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2401

pi->pasi = RV770_HASI_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2402

pi->vrc = RV770_VRC_DFLT;

sys/dev/drm/radeon/rv770_dpm.c

2404

pi->power_gating = false;

sys/dev/drm/radeon/rv770_dpm.c

2406

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/rv770_dpm.c

2408

pi->mg_clock_gating = true;

sys/dev/drm/radeon/rv770_dpm.c

2409

pi->mgcgtssm = true;

sys/dev/drm/radeon/rv770_dpm.c

2411

pi->dynamic_pcie_gen2 = true;

sys/dev/drm/radeon/rv770_dpm.c

2414

pi->thermal_protection = true;

sys/dev/drm/radeon/rv770_dpm.c

2416

pi->thermal_protection = false;

sys/dev/drm/radeon/rv770_dpm.c

2418

pi->display_gap = true;

sys/dev/drm/radeon/rv770_dpm.c

242

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

2421

pi->dcodt = true;

sys/dev/drm/radeon/rv770_dpm.c

2423

pi->dcodt = false;

sys/dev/drm/radeon/rv770_dpm.c

2425

pi->ulps = true;

sys/dev/drm/radeon/rv770_dpm.c

2427

pi->mclk_stutter_mode_threshold = 0;

sys/dev/drm/radeon/rv770_dpm.c

2429

pi->sram_end = SMC_RAM_END;

sys/dev/drm/radeon/rv770_dpm.c

2430

pi->state_table_start = RV770_SMC_TABLE_ADDRESS;

sys/dev/drm/radeon/rv770_dpm.c

2431

pi->soft_regs_start = RV770_SMC_SOFT_REGISTERS_START;

sys/dev/drm/radeon/rv770_dpm.c

245

pi->soft_regs_start + reg_offset,

sys/dev/drm/radeon/rv770_dpm.c

246

value, pi->sram_end);

sys/dev/drm/radeon/rv770_dpm.c

253

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

256

pi->soft_regs_start + reg_offset,

sys/dev/drm/radeon/rv770_dpm.c

257

value, pi->sram_end);

sys/dev/drm/radeon/rv770_dpm.c

265

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

276

a_n = (int)state->medium.sclk * pi->lmp +

sys/dev/drm/radeon/rv770_dpm.c

277

(int)state->low.sclk * (R600_AH_DFLT - pi->rlp);

sys/dev/drm/radeon/rv770_dpm.c

278

a_d = (int)state->low.sclk * (100 - (int)pi->rlp) +

sys/dev/drm/radeon/rv770_dpm.c

279

(int)state->medium.sclk * pi->lmp;

sys/dev/drm/radeon/rv770_dpm.c

281

l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

282

r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

284

a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk *

sys/dev/drm/radeon/rv770_dpm.c

285

(R600_AH_DFLT - pi->rmp);

sys/dev/drm/radeon/rv770_dpm.c

286

a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) +

sys/dev/drm/radeon/rv770_dpm.c

287

(int)state->high.sclk * pi->lhp;

sys/dev/drm/radeon/rv770_dpm.c

289

l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

290

r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d);

sys/dev/drm/radeon/rv770_dpm.c

293

a_t = CG_R(r[i] * pi->bsp / 200) | CG_L(l[i] * pi->bsp / 200);

sys/dev/drm/radeon/rv770_dpm.c

297

a_t = CG_R(r[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200) |

sys/dev/drm/radeon/rv770_dpm.c

298

CG_L(l[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1] * pi->pbsp / 200);

sys/dev/drm/radeon/rv770_dpm.c

310

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

314

smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/rv770_dpm.c

317

cpu_to_be32(pi->psp);

sys/dev/drm/radeon/rv770_dpm.c

394

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

397

pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/rv770_dpm.c

399

pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.c

401

pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/rv770_dpm.c

403

pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.c

405

pi->clk_regs.rv770.mclk_pwrmgt_cntl;

sys/dev/drm/radeon/rv770_dpm.c

406

u32 dll_cntl = pi->clk_regs.rv770.dll_cntl;

sys/dev/drm/radeon/rv770_dpm.c

423

pi->mem_gddr5,

sys/dev/drm/radeon/rv770_dpm.c

448

if (pi->mem_gddr5) {

sys/dev/drm/radeon/rv770_dpm.c

451

pi->mem_gddr5,

sys/dev/drm/radeon/rv770_dpm.c

492

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

495

pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/rv770_dpm.c

497

pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.c

499

pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv770_dpm.c

501

pi->clk_regs.rv770.cg_spll_spread_spectrum;

sys/dev/drm/radeon/rv770_dpm.c

503

pi->clk_regs.rv770.cg_spll_spread_spectrum_2;

sys/dev/drm/radeon/rv770_dpm.c

542

if (pi->sclk_ss) {

sys/dev/drm/radeon/rv770_dpm.c

573

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

576

if (!pi->voltage_control) {

sys/dev/drm/radeon/rv770_dpm.c

582

for (i = 0; i < pi->valid_vddc_entries; i++) {

sys/dev/drm/radeon/rv770_dpm.c

583

if (vddc <= pi->vddc_table[i].vddc) {

sys/dev/drm/radeon/rv770_dpm.c

584

voltage->index = pi->vddc_table[i].vddc_index;

sys/dev/drm/radeon/rv770_dpm.c

590

if (i == pi->valid_vddc_entries)

sys/dev/drm/radeon/rv770_dpm.c

599

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

601

if (!pi->mvdd_control) {

sys/dev/drm/radeon/rv770_dpm.c

607

if (mclk <= pi->mvdd_split_frequency) {

sys/dev/drm/radeon/rv770_dpm.c

61

struct rv7xx_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/rv770_dpm.c

623

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

626

level->gen2PCIE = pi->pcie_gen2 ?

sys/dev/drm/radeon/rv770_dpm.c

63

return pi;

sys/dev/drm/radeon/rv770_dpm.c

645

if (pi->mem_gddr5) {

sys/dev/drm/radeon/rv770_dpm.c

646

if (pl->mclk <= pi->mclk_strobe_mode_threshold)

sys/dev/drm/radeon/rv770_dpm.c

652

if (pl->mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/rv770_dpm.c

68

struct evergreen_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/rv770_dpm.c

70

return pi;

sys/dev/drm/radeon/rv770_dpm.c

747

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

76

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

761

STATE0(64 * high_clock / pi->boot_sclk) |

sys/dev/drm/radeon/rv770_dpm.c

768

POWERMODE0(rv770_calculate_memory_refresh_rate(rdev, pi->boot_sclk)) |

sys/dev/drm/radeon/rv770_dpm.c

787

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

790

if (pi->sclk_ss)

sys/dev/drm/radeon/rv770_dpm.c

793

if (pi->mclk_ss) {

sys/dev/drm/radeon/rv770_dpm.c

811

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

813

if ((rdev->family == CHIP_RV770) && !pi->mem_gddr5) {

sys/dev/drm/radeon/rv770_dpm.c

815

(MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) |

sys/dev/drm/radeon/rv770_dpm.c

822

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

825

r600_calculate_u_and_p(pi->asi,

sys/dev/drm/radeon/rv770_dpm.c

828

&pi->bsp,

sys/dev/drm/radeon/rv770_dpm.c

829

&pi->bsu);

sys/dev/drm/radeon/rv770_dpm.c

831

r600_calculate_u_and_p(pi->pasi,

sys/dev/drm/radeon/rv770_dpm.c

834

&pi->pbsp,

sys/dev/drm/radeon/rv770_dpm.c

835

&pi->pbsu);

sys/dev/drm/radeon/rv770_dpm.c

837

pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);

sys/dev/drm/radeon/rv770_dpm.c

838

pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);

sys/dev/drm/radeon/rv770_dpm.c

840

WREG32(CG_BSP, pi->dsp);

sys/dev/drm/radeon/rv770_dpm.c

85

if (!pi->boot_in_gen2) {

sys/dev/drm/radeon/rv770_dpm.c

894

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

896

WREG32(CG_FTV, pi->vrc);

sys/dev/drm/radeon/rv770_dpm.c

906

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

912

ret = rv770_load_smc_ucode(rdev, pi->sram_end);

sys/dev/drm/radeon/rv770_dpm.c

922

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/rv770_dpm.c

925

pi->clk_regs.rv770.mpll_ad_func_cntl;

sys/dev/drm/radeon/rv770_dpm.c

927

pi->clk_regs.rv770.mpll_ad_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.c

929

pi->clk_regs.rv770.mpll_dq_func_cntl;

sys/dev/drm/radeon/rv770_dpm.c

931

pi->clk_regs.rv770.mpll_dq_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.c

933

pi->clk_regs.rv770.cg_spll_func_cntl;

sys/dev/drm/radeon/rv770_dpm.c

935

pi->clk_regs.rv770.cg_spll_func_cntl_2;

sys/dev/drm/radeon/rv770_dpm.c

937

pi->clk_regs.rv770.cg_spll_func_cntl_3;

sys/dev/drm/radeon/rv770_dpm.c

945

if (pi->acpi_vddc) {

sys/dev/drm/radeon/rv770_dpm.c

946

rv770_populate_vddc_value(rdev, pi->acpi_vddc,

sys/dev/drm/radeon/rv770_dpm.c

948

if (pi->pcie_gen2) {

sys/dev/drm/radeon/rv770_dpm.c

949

if (pi->acpi_pcie_gen2)

sys/dev/drm/radeon/rv770_dpm.c

955

if (pi->acpi_pcie_gen2)

sys/dev/drm/radeon/rv770_dpm.c

960

rv770_populate_vddc_value(rdev, pi->min_vddc_in_table,

sys/dev/drm/radeon/si_dpm.c

1766

struct si_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/si_dpm.c

1768

return pi;

sys/dev/drm/radeon/si_dpm.c

3283

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3309

if (pi->thermal_protection)

sys/dev/drm/radeon/si_dpm.c

3320

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3323

if (!(pi->active_auto_throttle_sources & (1 << source))) {

sys/dev/drm/radeon/si_dpm.c

3324

pi->active_auto_throttle_sources |= 1 << source;

sys/dev/drm/radeon/si_dpm.c

3325

si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/si_dpm.c

3328

if (pi->active_auto_throttle_sources & (1 << source)) {

sys/dev/drm/radeon/si_dpm.c

3329

pi->active_auto_throttle_sources &= ~(1 << source);

sys/dev/drm/radeon/si_dpm.c

3330

si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);

sys/dev/drm/radeon/si_dpm.c

3731

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3734

if (pi->sclk_ss)

sys/dev/drm/radeon/si_dpm.c

3744

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3747

r600_calculate_u_and_p(pi->asi,

sys/dev/drm/radeon/si_dpm.c

3750

&pi->bsp,

sys/dev/drm/radeon/si_dpm.c

3751

&pi->bsu);

sys/dev/drm/radeon/si_dpm.c

3753

r600_calculate_u_and_p(pi->pasi,

sys/dev/drm/radeon/si_dpm.c

3756

&pi->pbsp,

sys/dev/drm/radeon/si_dpm.c

3757

&pi->pbsu);

sys/dev/drm/radeon/si_dpm.c

3760

pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);

sys/dev/drm/radeon/si_dpm.c

3761

pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);

sys/dev/drm/radeon/si_dpm.c

3763

WREG32(CG_BSP, pi->dsp);

sys/dev/drm/radeon/si_dpm.c

3817

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3819

WREG32(CG_FTV, pi->vrc);

sys/dev/drm/radeon/si_dpm.c

3864

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3868

if (mclk <= pi->mclk_strobe_mode_threshold)

sys/dev/drm/radeon/si_dpm.c

3871

if (pi->mem_gddr5)

sys/dev/drm/radeon/si_dpm.c

3962

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

3967

if (pi->voltage_control) {

sys/dev/drm/radeon/si_dpm.c

4006

if (pi->mvdd_control) {

sys/dev/drm/radeon/si_dpm.c

4011

pi->mvdd_control = false;

sys/dev/drm/radeon/si_dpm.c

4016

pi->mvdd_control = false;

sys/dev/drm/radeon/si_dpm.c

4053

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4072

if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {

sys/dev/drm/radeon/si_dpm.c

4136

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4139

if (pi->mvdd_control) {

sys/dev/drm/radeon/si_dpm.c

4140

if (mclk <= pi->mvdd_split_frequency)

sys/dev/drm/radeon/si_dpm.c

4358

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4361

if (pi->mvdd_control)

sys/dev/drm/radeon/si_dpm.c

4373

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4457

table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/si_dpm.c

4461

if (pi->mem_gddr5) {

sys/dev/drm/radeon/si_dpm.c

4466

if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/si_dpm.c

4494

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4515

if (pi->acpi_vddc) {

sys/dev/drm/radeon/si_dpm.c

4517

pi->acpi_vddc, &table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4533

pi->acpi_vddc,

sys/dev/drm/radeon/si_dpm.c

4540

pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);

sys/dev/drm/radeon/si_dpm.c

4560

pi->min_vddc_in_table,

sys/dev/drm/radeon/si_dpm.c

4566

if (pi->acpi_vddc) {

sys/dev/drm/radeon/si_dpm.c

4691

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4693

pi->mvdd_split_frequency = 30000;

sys/dev/drm/radeon/si_dpm.c

4698

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4733

if (pi->mem_gddr5)

sys/dev/drm/radeon/si_dpm.c

4788

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4825

if (pi->sclk_ss) {

sys/dev/drm/radeon/si_dpm.c

4882

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4910

if (pi->mem_gddr5) {

sys/dev/drm/radeon/si_dpm.c

4916

if (pi->mclk_ss) {

sys/dev/drm/radeon/si_dpm.c

4922

if (pi->mem_gddr5)

sys/dev/drm/radeon/si_dpm.c

4969

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

4973

smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);

sys/dev/drm/radeon/si_dpm.c

4976

cpu_to_be32(pi->psp);

sys/dev/drm/radeon/si_dpm.c

4983

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

5003

if (pi->mclk_stutter_mode_threshold &&

sys/dev/drm/radeon/si_dpm.c

5004

(pl->mclk <= pi->mclk_stutter_mode_threshold) &&

sys/dev/drm/radeon/si_dpm.c

5014

if (pi->mem_gddr5) {

sys/dev/drm/radeon/si_dpm.c

5015

if (pl->mclk > pi->mclk_edc_enable_threshold)

sys/dev/drm/radeon/si_dpm.c

5092

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

5125

a_t |= CG_R(t_l * pi->bsp / 20000);

sys/dev/drm/radeon/si_dpm.c

5129

pi->pbsp : pi->bsp;

sys/dev/drm/radeon/si_dpm.c

5361

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

5388

if (!pi->mem_gddr5)

sys/dev/drm/radeon/si_dpm.c

5395

if (!pi->mem_gddr5) {

sys/dev/drm/radeon/si_dpm.c

6351

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

6359

if (pi->voltage_control || si_pi->voltage_control_svi2)

sys/dev/drm/radeon/si_dpm.c

6361

if (pi->mvdd_control)

sys/dev/drm/radeon/si_dpm.c

6363

if (pi->voltage_control || si_pi->voltage_control_svi2) {

sys/dev/drm/radeon/si_dpm.c

6375

if (pi->dynamic_ss)

sys/dev/drm/radeon/si_dpm.c

6377

if (pi->thermal_protection)

sys/dev/drm/radeon/si_dpm.c

6498

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

6506

if (pi->thermal_protection)

sys/dev/drm/radeon/si_dpm.c

6736

struct rv7xx_power_info *pi = rv770_get_pi(rdev);

sys/dev/drm/radeon/si_dpm.c

6766

pi->acpi_vddc = pl->vddc;

sys/dev/drm/radeon/si_dpm.c

6782

if (pi->min_vddc_in_table > pl->vddc)

sys/dev/drm/radeon/si_dpm.c

6783

pi->min_vddc_in_table = pl->vddc;

sys/dev/drm/radeon/si_dpm.c

6785

if (pi->max_vddc_in_table < pl->vddc)

sys/dev/drm/radeon/si_dpm.c

6786

pi->max_vddc_in_table = pl->vddc;

sys/dev/drm/radeon/si_dpm.c

6901

struct rv7xx_power_info *pi;

sys/dev/drm/radeon/si_dpm.c

6916

pi = &eg_pi->rv7xx;

sys/dev/drm/radeon/si_dpm.c

6944

pi->acpi_vddc = 0;

sys/dev/drm/radeon/si_dpm.c

6946

pi->min_vddc_in_table = 0;

sys/dev/drm/radeon/si_dpm.c

6947

pi->max_vddc_in_table = 0;

sys/dev/drm/radeon/si_dpm.c

6985

pi->ref_div = dividers.ref_div + 1;

sys/dev/drm/radeon/si_dpm.c

6987

pi->ref_div = R600_REFERENCEDIVIDER_DFLT;

sys/dev/drm/radeon/si_dpm.c

6991

pi->mclk_strobe_mode_threshold = 40000;

sys/dev/drm/radeon/si_dpm.c

6993

pi->mclk_stutter_mode_threshold = 0;

sys/dev/drm/radeon/si_dpm.c

6995

pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;

sys/dev/drm/radeon/si_dpm.c

6996

pi->mclk_edc_enable_threshold = 40000;

sys/dev/drm/radeon/si_dpm.c

7001

pi->voltage_control =

sys/dev/drm/radeon/si_dpm.c

7004

if (!pi->voltage_control) {

sys/dev/drm/radeon/si_dpm.c

7013

pi->mvdd_control =

sys/dev/drm/radeon/si_dpm.c

7031

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/radeon/si_dpm.c

7032

pi->pasi = CYPRESS_HASI_DFLT;

sys/dev/drm/radeon/si_dpm.c

7033

pi->vrc = SISLANDS_VRC_DFLT;

sys/dev/drm/radeon/si_dpm.c

7035

pi->gfx_clock_gating = true;

sys/dev/drm/radeon/si_dpm.c

7041

pi->thermal_protection = true;

sys/dev/drm/radeon/si_dpm.c

7043

pi->thermal_protection = false;

sys/dev/drm/radeon/sumo_dpm.c

1010

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1019

if (!pi->enable_sclk_ds)

sys/dev/drm/radeon/sumo_dpm.c

1034

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1037

for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {

sys/dev/drm/radeon/sumo_dpm.c

1038

if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)

sys/dev/drm/radeon/sumo_dpm.c

1039

return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;

sys/dev/drm/radeon/sumo_dpm.c

1042

return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;

sys/dev/drm/radeon/sumo_dpm.c

1049

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1050

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/sumo_dpm.c

1059

current_vddc = pi->boot_pl.vddc_index;

sys/dev/drm/radeon/sumo_dpm.c

1060

current_sclk = pi->boot_pl.sclk;

sys/dev/drm/radeon/sumo_dpm.c

1095

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1097

u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */

sys/dev/drm/radeon/sumo_dpm.c

1098

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/sumo_dpm.c

1104

if (pi->enable_boost) {

sys/dev/drm/radeon/sumo_dpm.c

1187

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1189

pi->current_rps = *rps;

sys/dev/drm/radeon/sumo_dpm.c

1190

pi->current_ps = *new_ps;

sys/dev/drm/radeon/sumo_dpm.c

1191

pi->current_rps.ps_priv = &pi->current_ps;

sys/dev/drm/radeon/sumo_dpm.c

1198

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1200

pi->requested_rps = *rps;

sys/dev/drm/radeon/sumo_dpm.c

1201

pi->requested_ps = *new_ps;

sys/dev/drm/radeon/sumo_dpm.c

1202

pi->requested_rps.ps_priv = &pi->requested_ps;

sys/dev/drm/radeon/sumo_dpm.c

1207

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1218

if (pi->enable_auto_thermal_throttling) {

sys/dev/drm/radeon/sumo_dpm.c

1230

if (pi->enable_sclk_ds)

sys/dev/drm/radeon/sumo_dpm.c

1232

if (pi->enable_boost)

sys/dev/drm/radeon/sumo_dpm.c

1262

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1267

if (pi->enable_sclk_ds)

sys/dev/drm/radeon/sumo_dpm.c

1285

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1291

if (pi->enable_dynamic_patch_ps)

sys/dev/drm/radeon/sumo_dpm.c

1293

&pi->requested_rps,

sys/dev/drm/radeon/sumo_dpm.c

1294

&pi->current_rps);

sys/dev/drm/radeon/sumo_dpm.c

1301

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1302

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/sumo_dpm.c

1303

struct radeon_ps *old_ps = &pi->current_rps;

sys/dev/drm/radeon/sumo_dpm.c

1305

if (pi->enable_dpm)

sys/dev/drm/radeon/sumo_dpm.c

1307

if (pi->enable_boost) {

sys/dev/drm/radeon/sumo_dpm.c

1311

if (pi->enable_dpm) {

sys/dev/drm/radeon/sumo_dpm.c

1327

if (pi->enable_boost)

sys/dev/drm/radeon/sumo_dpm.c

1329

if (pi->enable_dpm)

sys/dev/drm/radeon/sumo_dpm.c

1337

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1338

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/sumo_dpm.c

1359

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1362

pi->fw_version = sumo_get_running_fw_version(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1363

DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);

sys/dev/drm/radeon/sumo_dpm.c

1398

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1402

ps->levels[0] = pi->boot_pl;

sys/dev/drm/radeon/sumo_dpm.c

1436

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1449

if (pi->enable_sclk_ds) {

sys/dev/drm/radeon/sumo_dpm.c

1563

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1564

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);

sys/dev/drm/radeon/sumo_dpm.c

1659

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1676

pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);

sys/dev/drm/radeon/sumo_dpm.c

1677

pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);

sys/dev/drm/radeon/sumo_dpm.c

1678

pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);

sys/dev/drm/radeon/sumo_dpm.c

1679

pi->sys_info.bootup_nb_voltage_index =

sys/dev/drm/radeon/sumo_dpm.c

1682

pi->sys_info.htc_tmp_lmt = 203;

sys/dev/drm/radeon/sumo_dpm.c

1684

pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;

sys/dev/drm/radeon/sumo_dpm.c

1686

pi->sys_info.htc_hyst_lmt = 5;

sys/dev/drm/radeon/sumo_dpm.c

1688

pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;

sys/dev/drm/radeon/sumo_dpm.c

1689

if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {

sys/dev/drm/radeon/sumo_dpm.c

1693

pi->sys_info.csr_m3_arb_cntl_default[i] =

sys/dev/drm/radeon/sumo_dpm.c

1695

pi->sys_info.csr_m3_arb_cntl_uvd[i] =

sys/dev/drm/radeon/sumo_dpm.c

1697

pi->sys_info.csr_m3_arb_cntl_fs3d[i] =

sys/dev/drm/radeon/sumo_dpm.c

1700

pi->sys_info.sclk_dpm_boost_margin =

sys/dev/drm/radeon/sumo_dpm.c

1702

pi->sys_info.sclk_dpm_throttle_margin =

sys/dev/drm/radeon/sumo_dpm.c

1704

pi->sys_info.sclk_dpm_tdp_limit_pg =

sys/dev/drm/radeon/sumo_dpm.c

1706

pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);

sys/dev/drm/radeon/sumo_dpm.c

1707

pi->sys_info.sclk_dpm_tdp_limit_boost =

sys/dev/drm/radeon/sumo_dpm.c

1709

pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);

sys/dev/drm/radeon/sumo_dpm.c

1710

pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;

sys/dev/drm/radeon/sumo_dpm.c

1712

pi->sys_info.enable_boost = true;

sys/dev/drm/radeon/sumo_dpm.c

1714

pi->sys_info.enable_boost = false;

sys/dev/drm/radeon/sumo_dpm.c

1716

&pi->sys_info.disp_clk_voltage_mapping_table,

sys/dev/drm/radeon/sumo_dpm.c

1719

&pi->sys_info.sclk_voltage_mapping_table,

sys/dev/drm/radeon/sumo_dpm.c

1721

sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,

sys/dev/drm/radeon/sumo_dpm.c

1730

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1732

pi->boot_pl.sclk = pi->sys_info.bootup_sclk;

sys/dev/drm/radeon/sumo_dpm.c

1733

pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;

sys/dev/drm/radeon/sumo_dpm.c

1734

pi->boot_pl.ds_divider_index = 0;

sys/dev/drm/radeon/sumo_dpm.c

1735

pi->boot_pl.ss_divider_index = 0;

sys/dev/drm/radeon/sumo_dpm.c

1736

pi->boot_pl.allow_gnb_slow = 1;

sys/dev/drm/radeon/sumo_dpm.c

1737

pi->acpi_pl = pi->boot_pl;

sys/dev/drm/radeon/sumo_dpm.c

1738

pi->current_ps.num_levels = 1;

sys/dev/drm/radeon/sumo_dpm.c

1739

pi->current_ps.levels[0] = pi->boot_pl;

sys/dev/drm/radeon/sumo_dpm.c

1744

struct sumo_power_info *pi;

sys/dev/drm/radeon/sumo_dpm.c

1748

pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);

sys/dev/drm/radeon/sumo_dpm.c

1749

if (pi == NULL)

sys/dev/drm/radeon/sumo_dpm.c

1751

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/sumo_dpm.c

1753

pi->driver_nbps_policy_disable = false;

sys/dev/drm/radeon/sumo_dpm.c

1755

pi->disable_gfx_power_gating_in_uvd = true;

sys/dev/drm/radeon/sumo_dpm.c

1757

pi->disable_gfx_power_gating_in_uvd = false;

sys/dev/drm/radeon/sumo_dpm.c

1758

pi->enable_alt_vddnb = true;

sys/dev/drm/radeon/sumo_dpm.c

1759

pi->enable_sclk_ds = true;

sys/dev/drm/radeon/sumo_dpm.c

1760

pi->enable_dynamic_m3_arbiter = false;

sys/dev/drm/radeon/sumo_dpm.c

1761

pi->enable_dynamic_patch_ps = true;

sys/dev/drm/radeon/sumo_dpm.c

1766

pi->enable_gfx_power_gating = false;

sys/dev/drm/radeon/sumo_dpm.c

1768

pi->enable_gfx_power_gating = true;

sys/dev/drm/radeon/sumo_dpm.c

1769

pi->enable_gfx_clock_gating = true;

sys/dev/drm/radeon/sumo_dpm.c

1770

pi->enable_mg_clock_gating = true;

sys/dev/drm/radeon/sumo_dpm.c

1771

pi->enable_auto_thermal_throttling = true;

sys/dev/drm/radeon/sumo_dpm.c

1787

pi->pasi = CYPRESS_HASI_DFLT;

sys/dev/drm/radeon/sumo_dpm.c

1788

pi->asi = RV770_ASI_DFLT;

sys/dev/drm/radeon/sumo_dpm.c

1789

pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;

sys/dev/drm/radeon/sumo_dpm.c

1790

pi->enable_boost = pi->sys_info.enable_boost;

sys/dev/drm/radeon/sumo_dpm.c

1791

pi->enable_dpm = true;

sys/dev/drm/radeon/sumo_dpm.c

1817

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1818

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/sumo_dpm.c

1826

pl = &pi->boost_pl;

sys/dev/drm/radeon/sumo_dpm.c

1844

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1845

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/sumo_dpm.c

1853

pl = &pi->boost_pl;

sys/dev/drm/radeon/sumo_dpm.c

1865

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1867

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/radeon/sumo_dpm.c

1885

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1886

struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);

sys/dev/drm/radeon/sumo_dpm.c

1896

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1898

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/radeon/sumo_dpm.c

1904

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

1905

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/sumo_dpm.c

1913

if (pi->enable_boost)

sys/dev/drm/radeon/sumo_dpm.c

1925

if (pi->enable_boost)

sys/dev/drm/radeon/sumo_dpm.c

1940

if (pi->enable_boost)

sys/dev/drm/radeon/sumo_dpm.c

289

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

291

if (pi->enable_gfx_clock_gating)

sys/dev/drm/radeon/sumo_dpm.c

293

if (pi->enable_gfx_power_gating)

sys/dev/drm/radeon/sumo_dpm.c

295

if (pi->enable_mg_clock_gating)

sys/dev/drm/radeon/sumo_dpm.c

297

if (pi->enable_gfx_clock_gating)

sys/dev/drm/radeon/sumo_dpm.c

299

if (pi->enable_gfx_power_gating)

sys/dev/drm/radeon/sumo_dpm.c

307

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

309

if (pi->enable_gfx_clock_gating)

sys/dev/drm/radeon/sumo_dpm.c

311

if (pi->enable_gfx_power_gating)

sys/dev/drm/radeon/sumo_dpm.c

313

if (pi->enable_mg_clock_gating)

sys/dev/drm/radeon/sumo_dpm.c

320

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

323

pi->pasi = 65535 * 100 / high_clk;

sys/dev/drm/radeon/sumo_dpm.c

324

pi->asi = 65535 * 100 / high_clk;

sys/dev/drm/radeon/sumo_dpm.c

326

r600_calculate_u_and_p(pi->asi,

sys/dev/drm/radeon/sumo_dpm.c

327

xclk, 16, &pi->bsp, &pi->bsu);

sys/dev/drm/radeon/sumo_dpm.c

329

r600_calculate_u_and_p(pi->pasi,

sys/dev/drm/radeon/sumo_dpm.c

330

xclk, 16, &pi->pbsp, &pi->pbsu);

sys/dev/drm/radeon/sumo_dpm.c

332

pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);

sys/dev/drm/radeon/sumo_dpm.c

333

pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);

sys/dev/drm/radeon/sumo_dpm.c

338

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

340

WREG32(CG_BSP_0, pi->psp);

sys/dev/drm/radeon/sumo_dpm.c

347

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

353

highest_engine_clock = pi->boost_pl.sclk;

sys/dev/drm/radeon/sumo_dpm.c

358

WREG32(CG_BSP_0 + (i * 4), pi->dsp);

sys/dev/drm/radeon/sumo_dpm.c

360

WREG32(CG_BSP_0 + (i * 4), pi->psp);

sys/dev/drm/radeon/sumo_dpm.c

363

WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);

sys/dev/drm/radeon/sumo_dpm.c

390

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

412

asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;

sys/dev/drm/radeon/sumo_dpm.c

422

asi = pi->pasi;

sys/dev/drm/radeon/sumo_dpm.c

424

m_a = asi * pi->boost_pl.sclk / 100;

sys/dev/drm/radeon/sumo_dpm.c

499

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

501

if (pi->enable_sclk_ds) {

sys/dev/drm/radeon/sumo_dpm.c

513

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

515

if (pi->enable_sclk_ds) {

sys/dev/drm/radeon/sumo_dpm.c

535

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

539

if (pi->driver_nbps_policy_disable)

sys/dev/drm/radeon/sumo_dpm.c

552

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

579

if (pi->enable_boost)

sys/dev/drm/radeon/sumo_dpm.c

669

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

673

pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];

sys/dev/drm/radeon/sumo_dpm.c

674

pi->boost_pl.sclk = pi->sys_info.boost_sclk;

sys/dev/drm/radeon/sumo_dpm.c

675

pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;

sys/dev/drm/radeon/sumo_dpm.c

676

pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;

sys/dev/drm/radeon/sumo_dpm.c

758

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

773

sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);

sys/dev/drm/radeon/sumo_dpm.c

788

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

793

pi->acpi_pl.sclk,

sys/dev/drm/radeon/sumo_dpm.c

804

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

808

sumo_program_power_level(rdev, &pi->boot_pl, 0);

sys/dev/drm/radeon/sumo_dpm.c

821

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

823

if (pi->enable_gfx_power_gating) {

sys/dev/drm/radeon/sumo_dpm.c

829

if (pi->enable_gfx_power_gating) {

sys/dev/drm/radeon/sumo_dpm.c

830

if (!pi->disable_gfx_power_gating_in_uvd ||

sys/dev/drm/radeon/sumo_dpm.c

86

struct sumo_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/sumo_dpm.c

88

return pi;

sys/dev/drm/radeon/sumo_dpm.c

946

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

949

cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);

sys/dev/drm/radeon/sumo_dpm.c

990

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_dpm.c

993

if (!pi->driver_nbps_policy_disable) {

sys/dev/drm/radeon/sumo_smc.c

102

if (pi->fw_version >= 0x00010C00)

sys/dev/drm/radeon/sumo_smc.c

146

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_smc.c

158

WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);

sys/dev/drm/radeon/sumo_smc.c

159

WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);

sys/dev/drm/radeon/sumo_smc.c

160

WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);

sys/dev/drm/radeon/sumo_smc.c

161

WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);

sys/dev/drm/radeon/sumo_smc.c

74

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_smc.c

77

if (!pi->enable_dynamic_m3_arbiter)

sys/dev/drm/radeon/sumo_smc.c

82

pi->sys_info.csr_m3_arb_cntl_default[i]);

sys/dev/drm/radeon/sumo_smc.c

86

pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);

sys/dev/drm/radeon/sumo_smc.c

90

pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);

sys/dev/drm/radeon/sumo_smc.c

95

struct sumo_power_info *pi = sumo_get_pi(rdev);

sys/dev/drm/radeon/sumo_smc.c

98

if (!pi->enable_alt_vddnb)

sys/dev/drm/radeon/trinity_dpm.c

1012

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1016

value |= HT((pi->thermal_auto_throttling + 49) * 8);

sys/dev/drm/radeon/trinity_dpm.c

1017

value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8);

sys/dev/drm/radeon/trinity_dpm.c

1076

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1078

pi->current_rps = *rps;

sys/dev/drm/radeon/trinity_dpm.c

1079

pi->current_ps = *new_ps;

sys/dev/drm/radeon/trinity_dpm.c

1080

pi->current_rps.ps_priv = &pi->current_ps;

sys/dev/drm/radeon/trinity_dpm.c

1087

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1089

pi->requested_rps = *rps;

sys/dev/drm/radeon/trinity_dpm.c

1090

pi->requested_ps = *new_ps;

sys/dev/drm/radeon/trinity_dpm.c

1091

pi->requested_rps.ps_priv = &pi->requested_ps;

sys/dev/drm/radeon/trinity_dpm.c

1096

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1098

if (pi->enable_bapm) {

sys/dev/drm/radeon/trinity_dpm.c

1107

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1119

if (pi->enable_auto_thermal_throttling) {

sys/dev/drm/radeon/trinity_dpm.c

1182

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1184

pi->min_sclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1191

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1195

if (pi->sys_info.nb_dpm_enable) {

sys/dev/drm/radeon/trinity_dpm.c

1209

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1210

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/trinity_dpm.c

1239

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1246

&pi->requested_rps,

sys/dev/drm/radeon/trinity_dpm.c

1247

&pi->current_rps);

sys/dev/drm/radeon/trinity_dpm.c

1254

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1255

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/trinity_dpm.c

1256

struct radeon_ps *old_ps = &pi->current_rps;

sys/dev/drm/radeon/trinity_dpm.c

1259

if (pi->enable_dpm) {

sys/dev/drm/radeon/trinity_dpm.c

1260

if (pi->enable_bapm)

sys/dev/drm/radeon/trinity_dpm.c

1280

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1281

struct radeon_ps *new_ps = &pi->requested_rps;

sys/dev/drm/radeon/trinity_dpm.c

1298

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1301

if (pi->enable_dpm) {

sys/dev/drm/radeon/trinity_dpm.c

1316

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1317

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);

sys/dev/drm/radeon/trinity_dpm.c

1331

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1336

ps->levels[0] = pi->boot_pl;

sys/dev/drm/radeon/trinity_dpm.c

1348

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1350

pi->boot_pl.sclk = pi->sys_info.bootup_sclk;

sys/dev/drm/radeon/trinity_dpm.c

1351

pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;

sys/dev/drm/radeon/trinity_dpm.c

1352

pi->boot_pl.ds_divider_index = 0;

sys/dev/drm/radeon/trinity_dpm.c

1353

pi->boot_pl.ss_divider_index = 0;

sys/dev/drm/radeon/trinity_dpm.c

1354

pi->boot_pl.allow_gnb_slow = 1;

sys/dev/drm/radeon/trinity_dpm.c

1355

pi->boot_pl.force_nbp_state = 0;

sys/dev/drm/radeon/trinity_dpm.c

1356

pi->boot_pl.display_wm = 0;

sys/dev/drm/radeon/trinity_dpm.c

1357

pi->boot_pl.vce_wm = 0;

sys/dev/drm/radeon/trinity_dpm.c

1358

pi->current_ps.num_levels = 1;

sys/dev/drm/radeon/trinity_dpm.c

1359

pi->current_ps.levels[0] = pi->boot_pl;

sys/dev/drm/radeon/trinity_dpm.c

1365

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1374

if (!pi->enable_sclk_ds)

sys/dev/drm/radeon/trinity_dpm.c

1389

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1392

for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {

sys/dev/drm/radeon/trinity_dpm.c

1393

if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)

sys/dev/drm/radeon/trinity_dpm.c

1394

return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;

sys/dev/drm/radeon/trinity_dpm.c

1397

if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries)

sys/dev/drm/radeon/trinity_dpm.c

1407

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1408

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/trinity_dpm.c

1417

current_vddc = pi->boot_pl.vddc_index;

sys/dev/drm/radeon/trinity_dpm.c

1418

current_sclk = pi->boot_pl.sclk;

sys/dev/drm/radeon/trinity_dpm.c

1459

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1463

if ((rps->vclk == pi->sys_info.uvd_clock_table_entries[i].vclk) &&

sys/dev/drm/radeon/trinity_dpm.c

1464

(rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))

sys/dev/drm/radeon/trinity_dpm.c

1479

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1483

if (pi->uvd_dpm && r600_is_uvd_state(rps->class, rps->class2)) {

sys/dev/drm/radeon/trinity_dpm.c

1499

pi->sys_info.uvd_clock_table_entries[high_index].vclk_did;

sys/dev/drm/radeon/trinity_dpm.c

1501

pi->sys_info.uvd_clock_table_entries[high_index].dclk_did;

sys/dev/drm/radeon/trinity_dpm.c

1503

pi->sys_info.uvd_clock_table_entries[low_index].vclk_did;

sys/dev/drm/radeon/trinity_dpm.c

1505

pi->sys_info.uvd_clock_table_entries[low_index].dclk_did;

sys/dev/drm/radeon/trinity_dpm.c

1545

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1547

u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */

sys/dev/drm/radeon/trinity_dpm.c

1548

u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */

sys/dev/drm/radeon/trinity_dpm.c

1603

if (pi->sys_info.nb_dpm_enable) {

sys/dev/drm/radeon/trinity_dpm.c

1613

(pi->sys_info.uma_channel_number == 1)));

sys/dev/drm/radeon/trinity_dpm.c

1632

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1634

if (pi->voltage_drop_in_dce)

sys/dev/drm/radeon/trinity_dpm.c

1657

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1659

if (pi->voltage_drop_in_dce)

sys/dev/drm/radeon/trinity_dpm.c

1716

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1728

if (pi->enable_sclk_ds) {

sys/dev/drm/radeon/trinity_dpm.c

1833

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1847

return ((pi->sys_info.dentist_vco_freq * 100) + (divider - 1)) / divider;

sys/dev/drm/radeon/trinity_dpm.c

1852

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

1869

pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock);

sys/dev/drm/radeon/trinity_dpm.c

1870

pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock);

sys/dev/drm/radeon/trinity_dpm.c

1871

pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock);

sys/dev/drm/radeon/trinity_dpm.c

1872

pi->sys_info.dentist_vco_freq = le32_to_cpu(igp_info->info_7.ulDentistVCOFreq);

sys/dev/drm/radeon/trinity_dpm.c

1873

pi->sys_info.bootup_nb_voltage_index =

sys/dev/drm/radeon/trinity_dpm.c

1876

pi->sys_info.htc_tmp_lmt = 203;

sys/dev/drm/radeon/trinity_dpm.c

1878

pi->sys_info.htc_tmp_lmt = igp_info->info_7.ucHtcTmpLmt;

sys/dev/drm/radeon/trinity_dpm.c

1880

pi->sys_info.htc_hyst_lmt = 5;

sys/dev/drm/radeon/trinity_dpm.c

1882

pi->sys_info.htc_hyst_lmt = igp_info->info_7.ucHtcHystLmt;

sys/dev/drm/radeon/trinity_dpm.c

1883

if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {

sys/dev/drm/radeon/trinity_dpm.c

1887

if (pi->enable_nbps_policy)

sys/dev/drm/radeon/trinity_dpm.c

1888

pi->sys_info.nb_dpm_enable = igp_info->info_7.ucNBDPMEnable;

sys/dev/drm/radeon/trinity_dpm.c

1890

pi->sys_info.nb_dpm_enable = 0;

sys/dev/drm/radeon/trinity_dpm.c

1893

pi->sys_info.nbp_mclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateMemclkFreq[i]);

sys/dev/drm/radeon/trinity_dpm.c

1894

pi->sys_info.nbp_nclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateNClkFreq[i]);

sys/dev/drm/radeon/trinity_dpm.c

1897

pi->sys_info.nbp_voltage_index[0] = le16_to_cpu(igp_info->info_7.usNBP0Voltage);

sys/dev/drm/radeon/trinity_dpm.c

1898

pi->sys_info.nbp_voltage_index[1] = le16_to_cpu(igp_info->info_7.usNBP1Voltage);

sys/dev/drm/radeon/trinity_dpm.c

1899

pi->sys_info.nbp_voltage_index[2] = le16_to_cpu(igp_info->info_7.usNBP2Voltage);

sys/dev/drm/radeon/trinity_dpm.c

1900

pi->sys_info.nbp_voltage_index[3] = le16_to_cpu(igp_info->info_7.usNBP3Voltage);

sys/dev/drm/radeon/trinity_dpm.c

1902

if (!pi->sys_info.nb_dpm_enable) {

sys/dev/drm/radeon/trinity_dpm.c

1904

pi->sys_info.nbp_mclk[i] = pi->sys_info.nbp_mclk[0];

sys/dev/drm/radeon/trinity_dpm.c

1905

pi->sys_info.nbp_nclk[i] = pi->sys_info.nbp_nclk[0];

sys/dev/drm/radeon/trinity_dpm.c

1906

pi->sys_info.nbp_voltage_index[i] = pi->sys_info.nbp_voltage_index[0];

sys/dev/drm/radeon/trinity_dpm.c

1910

pi->sys_info.uma_channel_number = igp_info->info_7.ucUMAChannelNumber;

sys/dev/drm/radeon/trinity_dpm.c

1913

&pi->sys_info.sclk_voltage_mapping_table,

sys/dev/drm/radeon/trinity_dpm.c

1915

sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,

sys/dev/drm/radeon/trinity_dpm.c

1918

pi->sys_info.uvd_clock_table_entries[0].vclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1920

pi->sys_info.uvd_clock_table_entries[1].vclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1922

pi->sys_info.uvd_clock_table_entries[2].vclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1924

pi->sys_info.uvd_clock_table_entries[3].vclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1927

pi->sys_info.uvd_clock_table_entries[0].dclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1929

pi->sys_info.uvd_clock_table_entries[1].dclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1931

pi->sys_info.uvd_clock_table_entries[2].dclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1933

pi->sys_info.uvd_clock_table_entries[3].dclk_did =

sys/dev/drm/radeon/trinity_dpm.c

1937

pi->sys_info.uvd_clock_table_entries[i].vclk =

sys/dev/drm/radeon/trinity_dpm.c

1939

pi->sys_info.uvd_clock_table_entries[i].vclk_did);

sys/dev/drm/radeon/trinity_dpm.c

1940

pi->sys_info.uvd_clock_table_entries[i].dclk =

sys/dev/drm/radeon/trinity_dpm.c

1942

pi->sys_info.uvd_clock_table_entries[i].dclk_did);

sys/dev/drm/radeon/trinity_dpm.c

1953

struct trinity_power_info *pi;

sys/dev/drm/radeon/trinity_dpm.c

1956

pi = kzalloc(sizeof(struct trinity_power_info), GFP_KERNEL);

sys/dev/drm/radeon/trinity_dpm.c

1957

if (pi == NULL)

sys/dev/drm/radeon/trinity_dpm.c

1959

rdev->pm.dpm.priv = pi;

sys/dev/drm/radeon/trinity_dpm.c

1962

pi->at[i] = TRINITY_AT_DFLT;

sys/dev/drm/radeon/trinity_dpm.c

1972

pi->enable_bapm = true;

sys/dev/drm/radeon/trinity_dpm.c

1974

pi->enable_bapm = false;

sys/dev/drm/radeon/trinity_dpm.c

1976

pi->enable_bapm = false;

sys/dev/drm/radeon/trinity_dpm.c

1978

pi->enable_bapm = true;

sys/dev/drm/radeon/trinity_dpm.c

1980

pi->enable_nbps_policy = true;

sys/dev/drm/radeon/trinity_dpm.c

1981

pi->enable_sclk_ds = true;

sys/dev/drm/radeon/trinity_dpm.c

1982

pi->enable_gfx_power_gating = true;

sys/dev/drm/radeon/trinity_dpm.c

1983

pi->enable_gfx_clock_gating = true;

sys/dev/drm/radeon/trinity_dpm.c

1984

pi->enable_mg_clock_gating = false;

sys/dev/drm/radeon/trinity_dpm.c

1985

pi->enable_gfx_dynamic_mgpg = false;

sys/dev/drm/radeon/trinity_dpm.c

1986

pi->override_dynamic_mgpg = false;

sys/dev/drm/radeon/trinity_dpm.c

1987

pi->enable_auto_thermal_throttling = true;

sys/dev/drm/radeon/trinity_dpm.c

1988

pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */

sys/dev/drm/radeon/trinity_dpm.c

1989

pi->uvd_dpm = true; /* ??? */

sys/dev/drm/radeon/trinity_dpm.c

2009

pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;

sys/dev/drm/radeon/trinity_dpm.c

2010

pi->enable_dpm = true;

sys/dev/drm/radeon/trinity_dpm.c

2036

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

2037

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/trinity_dpm.c

2057

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

2058

struct radeon_ps *rps = &pi->current_rps;

sys/dev/drm/radeon/trinity_dpm.c

2075

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

2077

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/radeon/trinity_dpm.c

2096

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

2097

struct trinity_ps *requested_state = trinity_get_ps(&pi->requested_rps);

sys/dev/drm/radeon/trinity_dpm.c

2107

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

2109

return pi->sys_info.bootup_uma_clk;

sys/dev/drm/radeon/trinity_dpm.c

362

struct trinity_power_info *pi = rdev->pm.dpm.priv;

sys/dev/drm/radeon/trinity_dpm.c

364

return pi;

sys/dev/drm/radeon/trinity_dpm.c

369

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

397

if (pi->override_dynamic_mgpg && (hw_rev == 0))

sys/dev/drm/radeon/trinity_dpm.c

552

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

554

if (pi->enable_gfx_clock_gating)

sys/dev/drm/radeon/trinity_dpm.c

556

if (pi->enable_mg_clock_gating)

sys/dev/drm/radeon/trinity_dpm.c

558

if (pi->enable_gfx_power_gating)

sys/dev/drm/radeon/trinity_dpm.c

560

if (pi->enable_mg_clock_gating) {

sys/dev/drm/radeon/trinity_dpm.c

564

if (pi->enable_gfx_clock_gating)

sys/dev/drm/radeon/trinity_dpm.c

566

if (pi->enable_gfx_dynamic_mgpg)

sys/dev/drm/radeon/trinity_dpm.c

568

if (pi->enable_gfx_power_gating)

sys/dev/drm/radeon/trinity_dpm.c

574

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

576

if (pi->enable_gfx_power_gating)

sys/dev/drm/radeon/trinity_dpm.c

578

if (pi->enable_gfx_dynamic_mgpg)

sys/dev/drm/radeon/trinity_dpm.c

580

if (pi->enable_gfx_clock_gating)

sys/dev/drm/radeon/trinity_dpm.c

582

if (pi->enable_mg_clock_gating) {

sys/dev/drm/radeon/trinity_dpm.c

643

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

644

u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid);

sys/dev/drm/radeon/trinity_dpm.c

722

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

735

trinity_set_at(rdev, index, pi->at[index]);

sys/dev/drm/radeon/trinity_dpm.c

864

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

867

trinity_program_power_level(rdev, &pi->boot_pl, 0);

sys/dev/drm/radeon/trinity_dpm.c

930

struct trinity_power_info *pi = trinity_get_pi(rdev);

sys/dev/drm/radeon/trinity_dpm.c

932

if (pi->enable_gfx_power_gating) {

sys/dev/drm/radeon/trinity_dpm.c

936

if (pi->uvd_dpm) {

sys/dev/drm/radeon/trinity_dpm.c

962

if (pi->enable_gfx_power_gating) {

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

1317

TRGT_POWER_INFO *pi;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

1330

pi = ee->ee_trgtPwr_11a;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

1337

pi = ee->ee_trgtPwr_11g;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

1344

pi = ee->ee_trgtPwr_11b;

sys/dev/netif/ath/ath_hal/ar5211/ar5211_reset.c

1362

ar5211SetRateTable(ah, rep, pi, nchan, chan);

sys/dev/netif/bce/if_bce.c

4334

struct pktinfo pi0, *pi = NULL;

sys/dev/netif/bce/if_bce.c

4474

pi = bce_rss_pktinfo(&pi0, status, l2fhdr);

sys/dev/netif/bce/if_bce.c

4475

if (pi != NULL &&

sys/dev/netif/bce/if_bce.c

4496

ifp->if_input(ifp, m, pi, cpuid);

sys/dev/netif/bce/if_bce.c

7143

bce_rss_pktinfo(struct pktinfo *pi, uint32_t status,

sys/dev/netif/bce/if_bce.c

7160

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/bce/if_bce.c

7166

pi->pi_l3proto = IPPROTO_UDP;

sys/dev/netif/bce/if_bce.c

7170

pi->pi_netisr = NETISR_IP;

sys/dev/netif/bce/if_bce.c

7171

pi->pi_flags = 0;

sys/dev/netif/bce/if_bce.c

7173

return pi;

sys/dev/netif/bnx/if_bnx.c

2800

struct pktinfo pi0, *pi = NULL;

sys/dev/netif/bnx/if_bnx.c

2867

pi = bnx_rss_info(&pi0, cur_rx);

sys/dev/netif/bnx/if_bnx.c

2868

if (pi != NULL &&

sys/dev/netif/bnx/if_bnx.c

2881

ifp->if_input(ifp, m, pi, cpuid);

sys/dev/netif/bnx/if_bnx.c

6112

bnx_rss_info(struct pktinfo *pi, const struct bge_rx_bd *cur_rx)

sys/dev/netif/bnx/if_bnx.c

6132

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/bnx/if_bnx.c

6134

pi->pi_l3proto = IPPROTO_UDP;

sys/dev/netif/bnx/if_bnx.c

6135

pi->pi_netisr = NETISR_IP;

sys/dev/netif/bnx/if_bnx.c

6136

pi->pi_flags = 0;

sys/dev/netif/bnx/if_bnx.c

6138

return pi;

sys/dev/netif/emx/if_emx.c

3353

struct pktinfo *pi = NULL, pi0;

sys/dev/netif/emx/if_emx.c

3433

pi = emx_rssinfo(m, &pi0, mrq,

sys/dev/netif/emx/if_emx.c

3453

ifp->if_input(ifp, m, pi, cpuid);

sys/dev/netif/emx/if_emx.c

472

emx_rssinfo(struct mbuf *m, struct pktinfo *pi,

sys/dev/netif/emx/if_emx.c

477

pi->pi_netisr = NETISR_IP;

sys/dev/netif/emx/if_emx.c

478

pi->pi_flags = 0;

sys/dev/netif/emx/if_emx.c

479

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/emx/if_emx.c

483

pi->pi_netisr = NETISR_IPV6;

sys/dev/netif/emx/if_emx.c

484

pi->pi_flags = 0;

sys/dev/netif/emx/if_emx.c

485

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/emx/if_emx.c

495

pi->pi_netisr = NETISR_IP;

sys/dev/netif/emx/if_emx.c

496

pi->pi_flags = 0;

sys/dev/netif/emx/if_emx.c

497

pi->pi_l3proto = IPPROTO_UDP;

sys/dev/netif/emx/if_emx.c

506

return pi;

sys/dev/netif/igb/if_igb.c

2727

struct pktinfo *pi = NULL, pi0;

sys/dev/netif/igb/if_igb.c

2796

pi = igb_rssinfo(m, &pi0,

sys/dev/netif/igb/if_igb.c

2820

ifp->if_input(ifp, m, pi, cpuid);

sys/dev/netif/igb/if_igb.c

386

igb_rssinfo(struct mbuf *m, struct pktinfo *pi,

sys/dev/netif/igb/if_igb.c

391

pi->pi_netisr = NETISR_IP;

sys/dev/netif/igb/if_igb.c

392

pi->pi_flags = 0;

sys/dev/netif/igb/if_igb.c

393

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/igb/if_igb.c

403

pi->pi_netisr = NETISR_IP;

sys/dev/netif/igb/if_igb.c

404

pi->pi_flags = 0;

sys/dev/netif/igb/if_igb.c

405

pi->pi_l3proto = IPPROTO_UDP;

sys/dev/netif/igb/if_igb.c

414

return pi;

sys/dev/netif/ix/if_ix.c

2891

ix_rssinfo(struct mbuf *m, struct pktinfo *pi,

sys/dev/netif/ix/if_ix.c

2896

pi->pi_netisr = NETISR_IP;

sys/dev/netif/ix/if_ix.c

2897

pi->pi_flags = 0;

sys/dev/netif/ix/if_ix.c

2898

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/ix/if_ix.c

2906

pi->pi_netisr = NETISR_IP;

sys/dev/netif/ix/if_ix.c

2907

pi->pi_flags = 0;

sys/dev/netif/ix/if_ix.c

2908

pi->pi_l3proto = IPPROTO_UDP;

sys/dev/netif/ix/if_ix.c

2916

return pi;

sys/dev/netif/ix/if_ix.c

2959

struct pktinfo *pi = NULL, pi0;

sys/dev/netif/ix/if_ix.c

3077

pi = ix_rssinfo(sendmp, &pi0,

sys/dev/netif/ix/if_ix.c

3089

ifp->if_input(ifp, sendmp, pi, cpuid);

sys/dev/netif/jme/if_jme.c

2279

jme_pktinfo(struct pktinfo *pi, uint32_t flags)

sys/dev/netif/jme/if_jme.c

2282

pi->pi_netisr = NETISR_IP;

sys/dev/netif/jme/if_jme.c

2284

pi->pi_netisr = NETISR_IPV6;

sys/dev/netif/jme/if_jme.c

2288

pi->pi_flags = 0;

sys/dev/netif/jme/if_jme.c

2289

pi->pi_l3proto = IPPROTO_UNKNOWN;

sys/dev/netif/jme/if_jme.c

2292

pi->pi_flags |= PKTINFO_FLAG_FRAG;

sys/dev/netif/jme/if_jme.c

2294

pi->pi_l3proto = IPPROTO_TCP;

sys/dev/netif/jme/if_jme.c

2296

pi->pi_l3proto = IPPROTO_UDP;

sys/dev/netif/jme/if_jme.c

2298

pi = NULL;

sys/dev/netif/jme/if_jme.c

2299

return pi;

sys/dev/netif/jme/if_jme.c

2399

struct pktinfo pi0, *pi;

sys/dev/netif/jme/if_jme.c

2452

pi = jme_pktinfo(&pi0, flags);

sys/dev/netif/jme/if_jme.c

2454

pi = NULL;

sys/dev/netif/jme/if_jme.c

2456

if (pi != NULL &&

sys/dev/netif/jme/if_jme.c

2464

if (pi != NULL) {

sys/dev/netif/jme/if_jme.c

2467

pi->pi_netisr, pi->pi_flags,

sys/dev/netif/jme/if_jme.c

2468

pi->pi_l3proto,

sys/dev/netif/jme/if_jme.c

2474

ifp->if_input(ifp, m, pi, cpuid);

sys/dev/raid/aac/aac.c

2125

u_int32_t pi, ci;

sys/dev/raid/aac/aac.c

2136

pi = sc->aac_queues->qt_qindex[queue][AAC_PRODUCER_INDEX];

sys/dev/raid/aac/aac.c

2140

if (pi >= aac_qinfo[queue].size)

sys/dev/raid/aac/aac.c

2141

pi = 0;

sys/dev/raid/aac/aac.c

2144

if ((pi + 1) == ci) {

sys/dev/raid/aac/aac.c

2156

(sc->aac_qentries[queue] + pi)->aq_fib_size = fib_size;

sys/dev/raid/aac/aac.c

2157

(sc->aac_qentries[queue] + pi)->aq_fib_addr = fib_addr;

sys/dev/raid/aac/aac.c

2160

sc->aac_queues->qt_qindex[queue][AAC_PRODUCER_INDEX] = pi + 1;

sys/dev/raid/aac/aac.c

2180

u_int32_t pi, ci;

sys/dev/raid/aac/aac.c

2188

pi = sc->aac_queues->qt_qindex[queue][AAC_PRODUCER_INDEX];

sys/dev/raid/aac/aac.c

2192

if (ci == pi) {

sys/dev/raid/aac/aac.c

2198

if (pi >= aac_qinfo[queue].size)

sys/dev/raid/aac/aac.c

2199

pi = 0;

sys/dev/raid/aac/aac.c

2202

if (ci == pi + 1)

sys/dev/raid/aac/aac.c

2275

u_int32_t pi, ci;

sys/dev/raid/aac/aac.c

2288

pi = sc->aac_queues->qt_qindex[queue][AAC_PRODUCER_INDEX];

sys/dev/raid/aac/aac.c

2292

if (pi >= aac_qinfo[queue].size)

sys/dev/raid/aac/aac.c

2293

pi = 0;

sys/dev/raid/aac/aac.c

2296

if ((pi + 1) == ci) {

sys/dev/raid/aac/aac.c

2302

(sc->aac_qentries[queue] + pi)->aq_fib_size = fib_size;

sys/dev/raid/aac/aac.c

2303

(sc->aac_qentries[queue] + pi)->aq_fib_addr = fib_addr;

sys/dev/raid/aac/aac.c

2306

sc->aac_queues->qt_qindex[queue][AAC_PRODUCER_INDEX] = pi + 1;

sys/dev/raid/mfi/mfi.c

1216

uint32_t pi, ci, context;

sys/dev/raid/mfi/mfi.c

1224

pi = sc->mfi_comms->hw_pi;

sys/dev/raid/mfi/mfi.c

1227

while (ci != pi) {

sys/dev/raid/mfi/mfi.c

1253

if (pi != sc->mfi_comms->hw_pi)

sys/kern/sys_generic.c

1438

uint64_t pi;

sys/kern/sys_generic.c

1448

pi = (uint64_t)(uintptr_t)kevp[i].udata -

sys/kern/sys_generic.c

1450

if (pi >= pkap->nfds) {

sys/kern/sys_generic.c

1455

kev.data = pi; /* uniquifier */

sys/kern/sys_generic.c

1461

"serial %ju\n", (uintmax_t)pi,

sys/kern/sys_generic.c

1470

pfd = &pkap->fds[pi];

sys/kern/sys_generic.c

1519

(uintmax_t)pi, pfd->fd,

sys/kern/sys_generic.c

1593

"revents %08x\n", (uintmax_t)pi, pkap->nfds,

sys/kern/sys_generic.c

1609

(uintmax_t)pi, (uintmax_t)kevp[i].ident,

sys/kern/sysv_shm.c

574

vm_pindex_t pi, pmax;

sys/kern/sysv_shm.c

581

for (pi = 0; pi < pmax; ++pi) {

sys/kern/sysv_shm.c

582

m = vm_page_grab(shm_handle->shm_object, pi,

sys/kern/sysv_shm.c

587

vm_pager_get_page(shm_handle->shm_object, pi, &m, 1);

sys/kern/vfs_bio.c

3118

vm_pindex_t pi;

sys/kern/vfs_bio.c

3121

pi = OFF_TO_IDX(bp->b_loffset) +

sys/kern/vfs_bio.c

3130

m = vm_page_lookup_busy_try(obj, pi, FALSE,

sys/kern/vfs_bio.c

3143

m = bio_page_alloc(bp, obj, pi,

sys/kern/vfs_bio.c

3187

vm_pindex_t pi;

sys/kern/vfs_bio.c

3192

pi = ((bp->b_loffset & PAGE_MASK) + toff) >>

sys/kern/vfs_bio.c

3200

bp->b_xio.xio_pages[pi]

sys/kern/vfs_vm.c

435

vm_pindex_t pi;

sys/kern/vfs_vm.c

486

pi = OFF_TO_IDX(length + PAGE_MASK);

sys/kern/vfs_vm.c

487

while (pi < nobjsize) {

sys/kern/vfs_vm.c

488

m = vm_page_lookup_busy_wait(object, pi, FALSE, "vmpg");

sys/kern/vfs_vm.c

493

++pi;

sys/libkern/qsort.c

50

TYPE *pi = (TYPE *) (parmi); \

sys/libkern/qsort.c

53

TYPE t = *pi; \

sys/libkern/qsort.c

54

*pi++ = *pj; \

sys/libprop/prop_array.c

154

prop_object_iterator_t pi;

sys/libprop/prop_array.c

170

pi = _prop_array_iterator_locked(pa);

sys/libprop/prop_array.c

171

if (pi == NULL)

sys/libprop/prop_array.c

177

while ((po = _prop_array_iterator_next_object_locked(pi)) != NULL) {

sys/libprop/prop_array.c

179

prop_object_iterator_release(pi);

sys/libprop/prop_array.c

184

prop_object_iterator_release(pi);

sys/libprop/prop_array.c

540

prop_object_iterator_t pi;

sys/libprop/prop_array.c

543

pi = _prop_array_iterator_locked(pa);

sys/libprop/prop_array.c

545

return (pi);

sys/libprop/prop_dictionary.c

432

prop_object_iterator_t pi;

sys/libprop/prop_dictionary.c

447

pi = _prop_dictionary_iterator_locked(pd);

sys/libprop/prop_dictionary.c

448

if (pi == NULL)

sys/libprop/prop_dictionary.c

454

while ((pdk = _prop_dictionary_iterator_next_object_locked(pi))

sys/libprop/prop_dictionary.c

463

prop_object_iterator_release(pi);

sys/libprop/prop_dictionary.c

468

prop_object_iterator_release(pi);

sys/libprop/prop_dictionary.c

830

prop_object_iterator_t pi;

sys/libprop/prop_dictionary.c

833

pi = _prop_dictionary_iterator_locked(pd);

sys/libprop/prop_dictionary.c

835

return (pi);

sys/libprop/prop_object.c

1197

prop_object_iterator_next(prop_object_iterator_t pi)

sys/libprop/prop_object.c

1200

return ((*pi->pi_next_object)(pi));

sys/libprop/prop_object.c

1209

prop_object_iterator_reset(prop_object_iterator_t pi)

sys/libprop/prop_object.c

1212

(*pi->pi_reset)(pi);

sys/libprop/prop_object.c

1220

prop_object_iterator_release(prop_object_iterator_t pi)

sys/libprop/prop_object.c

1223

prop_object_release(pi->pi_obj);

sys/libprop/prop_object.c

1224

_PROP_FREE(pi, M_TEMP);

sys/net/if_ethersubr.c

1489

ether_input(struct ifnet *ifp, struct mbuf *m, const struct pktinfo *pi,

sys/net/if_ethersubr.c

1536

if (pi != NULL && (m->m_flags & M_HASH)) {

sys/net/if_ethersubr.c

1540

netisr_hashcheck(pi->pi_netisr, m, pi);

sys/net/if_ethersubr.c

1542

ether_dispatch(ifp, pi->pi_netisr, m, cpuid);

sys/net/if_ethersubr.c

1552

if (pi == NULL)

sys/net/if_var.h

356

const struct pktinfo *pi, int cpuid);

sys/net/ipfw/ip_fw2.c

3026

struct inpcbinfo *pi;

sys/net/ipfw/ip_fw2.c

3032

pi = &tcbinfo[mycpuid];

sys/net/ipfw/ip_fw2.c

3035

pi = &udbinfo[mycpuid];

sys/net/ipfw/ip_fw2.c

3046

pcb = in_pcblookup_hash(pi,

sys/net/ipfw/ip_fw2.c

3051

pcb = in_pcblookup_hash(pi,

sys/net/ipfw3_layer4/ip_fw3_layer4.c

100

struct inpcbinfo *pi;

sys/net/ipfw3_layer4/ip_fw3_layer4.c

106

pi = &tcbinfo[mycpuid];

sys/net/ipfw3_layer4/ip_fw3_layer4.c

109

pi = &udbinfo[mycpuid];

sys/net/ipfw3_layer4/ip_fw3_layer4.c

120

pcb = in_pcblookup_hash(pi,

sys/net/ipfw3_layer4/ip_fw3_layer4.c

125

pcb = in_pcblookup_hash(pi,

sys/net/netisr.c

825

netisr_nohashck(struct mbuf *m, const struct pktinfo *pi __unused)

sys/net/netisr.c

831

netisr_hashcheck(int num, struct mbuf *m, const struct pktinfo *pi)

sys/net/netisr.c

845

ni->ni_hashck(m, pi);

sys/net/netisr.h

176

const struct pktinfo *pi);

sys/net/netmap/netmap_generic.c

594

const struct pktinfo *pi, int cpuid)

sys/net/pf/pf.c

3366

struct inpcbinfo *pi;

sys/net/pf/pf.c

3394

pi = &tcbinfo[pi_cpu];

sys/net/pf/pf.c

3425

msg->nm_pcbinfo = pi;

sys/net/pf/pf.c

3445

pi = &udbinfo[mycpuid];

sys/net/pf/pf.c

3470

inp = in6_pcblookup_hash(pi, &saddr->v6, sport,

sys/net/pf/pf.c

3485

inp = in_pcblookup_hash(pi, saddr->v4, sport, daddr->v4,

sys/net/pf/pf_ioctl.c

1797

struct pfioc_if *pi = (struct pfioc_if *)addr;

sys/net/pf/pf_ioctl.c

1799

if (pi->ifname[0] == 0) {

sys/net/pf/pf_ioctl.c

1803

strlcpy(pf_status.ifname, pi->ifname, IFNAMSIZ);

sys/netinet/ip_demux.c

341

ip_hashcheck(struct mbuf *m, const struct pktinfo *pi)

sys/netinet/ip_demux.c

345

switch (pi->pi_l3proto) {

sys/netinet6/in6_src.c

128

struct in6_pktinfo *pi = NULL;

sys/netinet6/in6_src.c

143

if (opts && (pi = opts->ip6po_pktinfo) &&

sys/netinet6/in6_src.c

144

!IN6_IS_ADDR_UNSPECIFIED(&pi->ipi6_addr)) {

sys/netinet6/in6_src.c

145

jsin6.sin6_addr = pi->ipi6_addr;

sys/netinet6/in6_src.c

150

return (&pi->ipi6_addr);

sys/netinet6/in6_src.c

173

if (pi && pi->ipi6_ifindex) {

sys/netinet6/in6_src.c

175

ia6 = in6_ifawithscope(ifindex2ifnet[pi->ipi6_ifindex],

sys/netinet6/in6_src.c

559

struct in6_pktinfo *pi;

sys/netinet6/in6_src.c

566

(pi = in6p->in6p_outputopts->ip6po_pktinfo) &&

sys/netinet6/in6_src.c

567

pi->ipi6_ifindex) {

sys/netinet6/in6_src.c

568

ifp = ifindex2ifnet[pi->ipi6_ifindex];

sys/netinet6/in6_src.c

569

in6->s6_addr16[1] = htons(pi->ipi6_ifindex);

sys/netinet6/nd6_rtr.c

293

struct nd_opt_prefix_info *pi = NULL;

sys/netinet6/nd6_rtr.c

302

pi = (struct nd_opt_prefix_info *)pt;

sys/netinet6/nd6_rtr.c

304

if (pi->nd_opt_pi_len != 4) {

sys/netinet6/nd6_rtr.c

308

"ignored\n", pi->nd_opt_pi_len));

sys/netinet6/nd6_rtr.c

312

if (128 < pi->nd_opt_pi_prefix_len) {

sys/netinet6/nd6_rtr.c

316

"ignored\n", pi->nd_opt_pi_prefix_len));

sys/netinet6/nd6_rtr.c

320

if (IN6_IS_ADDR_MULTICAST(&pi->nd_opt_pi_prefix)

sys/netinet6/nd6_rtr.c

321

|| IN6_IS_ADDR_LINKLOCAL(&pi->nd_opt_pi_prefix)) {

sys/netinet6/nd6_rtr.c

325

ip6_sprintf(&pi->nd_opt_pi_prefix)));

sys/netinet6/nd6_rtr.c

332

pr.ndpr_prefix.sin6_addr = pi->nd_opt_pi_prefix;

sys/netinet6/nd6_rtr.c

335

pr.ndpr_raf_onlink = (pi->nd_opt_pi_flags_reserved &

sys/netinet6/nd6_rtr.c

337

pr.ndpr_raf_auto = (pi->nd_opt_pi_flags_reserved &

sys/netinet6/nd6_rtr.c

339

pr.ndpr_plen = pi->nd_opt_pi_prefix_len;

sys/netinet6/nd6_rtr.c

340

pr.ndpr_vltime = ntohl(pi->nd_opt_pi_valid_time);

sys/netinet6/nd6_rtr.c

341

pr.ndpr_pltime = ntohl(pi->nd_opt_pi_preferred_time);

sys/netinet6/raw_ip6.c

341

struct in6_pktinfo *pi;

sys/netinet6/raw_ip6.c

347

if (optp && (pi = optp->ip6po_pktinfo) && pi->ipi6_ifindex) {

sys/netinet6/raw_ip6.c

348

ip6->ip6_dst.s6_addr16[1] = htons(pi->ipi6_ifindex);

sys/netinet6/raw_ip6.c

349

oifp = ifindex2ifnet[pi->ipi6_ifindex];

sys/vfs/isofs/cd9660/cd9660_node.c

343

cd9660_tstamp_conv7(u_char *pi, struct timespec *pu, enum ISO_FTYPE ftype)

sys/vfs/isofs/cd9660/cd9660_node.c

348

y = pi[0] + 1900;

sys/vfs/isofs/cd9660/cd9660_node.c

349

m = pi[1];

sys/vfs/isofs/cd9660/cd9660_node.c

350

d = pi[2];

sys/vfs/isofs/cd9660/cd9660_node.c

351

hour = pi[3];

sys/vfs/isofs/cd9660/cd9660_node.c

352

minute = pi[4];

sys/vfs/isofs/cd9660/cd9660_node.c

353

second = pi[5];

sys/vfs/isofs/cd9660/cd9660_node.c

355

tz = ((signed char *)pi)[6]; /* Timezone value is signed. */

sys/vfs/isofs/cd9660/cd9660_node.c

400

cd9660_tstamp_conv17(u_char *pi, struct timespec *pu)

sys/vfs/isofs/cd9660/cd9660_node.c

405

buf[0] = cd9660_chars2ui(pi,4) - 1900;

sys/vfs/isofs/cd9660/cd9660_node.c

408

buf[1] = cd9660_chars2ui(pi + 4,2);

sys/vfs/isofs/cd9660/cd9660_node.c

411

buf[2] = cd9660_chars2ui(pi + 6,2);

sys/vfs/isofs/cd9660/cd9660_node.c

414

buf[3] = cd9660_chars2ui(pi + 8,2);

sys/vfs/isofs/cd9660/cd9660_node.c

417

buf[4] = cd9660_chars2ui(pi + 10,2);

sys/vfs/isofs/cd9660/cd9660_node.c

420

buf[5] = cd9660_chars2ui(pi + 12,2);

sys/vfs/isofs/cd9660/cd9660_node.c

423

buf[6] = pi[16];

sys/vfs/ntfs/ntfs_vfsops.c

394

int pi[3] = { NTFS_MFTINO, NTFS_ROOTINO, NTFS_BITMAPINO };

sys/vfs/ntfs/ntfs_vfsops.c

397

pi[i], &(ntmp->ntm_sysvn[pi[i]]));

sys/vfs/ntfs/ntfs_vfsops.c

400

vsetflags(ntmp->ntm_sysvn[pi[i]], VSYSTEM);

sys/vfs/ntfs/ntfs_vfsops.c

401

vref(ntmp->ntm_sysvn[pi[i]]);

sys/vfs/ntfs/ntfs_vfsops.c

402

vput(ntmp->ntm_sysvn[pi[i]]);

sys/vm/vm_object.c

1155

vm_pindex_t pi;

sys/vm/vm_object.c

1160

pi = p->pindex;

sys/vm/vm_object.c

1161

page_base = pi % BLIST_MAX_ALLOC;

sys/vm/vm_object.c

1169

tp = vm_page_lookup_busy_try(object, pi - page_base + ib,

sys/vm/vm_object.c

1198

pi - page_base + is < object->size) {

sys/vm/vm_object.c

1201

tp = vm_page_lookup_busy_try(object, pi - page_base + is,

tools/regression/lib/libm/test-invctrig.c

200

testall_tol(cacosh, zero, CMPLXL(0.0, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

201

testall_tol(cacosh, -zero, CMPLXL(0.0, -pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

202

testall_tol(cacos, zero, CMPLXL(pi / 2, -0.0), 1);

tools/regression/lib/libm/test-invctrig.c

203

testall_tol(cacos, -zero, CMPLXL(pi / 2, 0.0), 1);

tools/regression/lib/libm/test-invctrig.c

263

testall_tol(catanh, z, CMPLXL(0.0, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

274

testall_odd_tol(catan, z, CMPLXL(pi / 2, 0.0), 1);

tools/regression/lib/libm/test-invctrig.c

279

testall_even_tol(cacos, z, CMPLXL(pi / 2, NAN), 1);

tools/regression/lib/libm/test-invctrig.c

308

testall_tol(cacosh, z, CMPLXL(INFINITY, pi / 4), 1);

tools/regression/lib/libm/test-invctrig.c

310

testall_tol(cacos, z, CMPLXL(pi / 4, -INFINITY), 1);

tools/regression/lib/libm/test-invctrig.c

312

testall_odd_tol(casinh, z, CMPLXL(INFINITY, pi / 4), 1);

tools/regression/lib/libm/test-invctrig.c

313

testall_odd_tol(casin, z, CMPLXL(pi / 4, INFINITY), 1);

tools/regression/lib/libm/test-invctrig.c

314

testall_odd_tol(catanh, z, CMPLXL(0, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

315

testall_odd_tol(catan, z, CMPLXL(pi / 2, 0), 1);

tools/regression/lib/libm/test-invctrig.c

320

testall_tol(cacosh, -z, CMPLXL(INFINITY, -pi), 1);

tools/regression/lib/libm/test-invctrig.c

322

testall_tol(cacos, -z, CMPLXL(pi, INFINITY), 1);

tools/regression/lib/libm/test-invctrig.c

324

testall_odd_tol(casin, z, CMPLXL(pi / 2, INFINITY), 1);

tools/regression/lib/libm/test-invctrig.c

325

testall_odd_tol(catanh, z, CMPLXL(0, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

326

testall_odd_tol(catan, z, CMPLXL(pi / 2, 0), 1);

tools/regression/lib/libm/test-invctrig.c

329

testall_tol(cacosh, z, CMPLXL(INFINITY, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

330

testall_tol(cacosh, -z, CMPLXL(INFINITY, -pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

331

testall_tol(cacos, z, CMPLXL(pi / 2, -INFINITY), 1);

tools/regression/lib/libm/test-invctrig.c

332

testall_tol(cacos, -z, CMPLXL(pi / 2, INFINITY), 1);

tools/regression/lib/libm/test-invctrig.c

333

testall_odd_tol(casinh, z, CMPLXL(INFINITY, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

336

testall_odd_tol(catanh, z, CMPLXL(0, pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

337

testall_odd_tol(catan, z, CMPLXL(pi / 2, 0), 1);

tools/regression/lib/libm/test-invctrig.c

361

(nums[i] < 0) ? pi : 0), 1);

tools/regression/lib/libm/test-invctrig.c

363

CMPLXL((nums[i] < 0) ? pi : 0,

tools/regression/lib/libm/test-invctrig.c

366

CMPLXL(copysign(pi / 2, nums[i]),

tools/regression/lib/libm/test-invctrig.c

369

CMPLXL(atanh(1 / nums[i]), pi / 2), 1);

tools/regression/lib/libm/test-invctrig.c

394

CMPLXL(pi / 4, -0.34657359027997265470861606072908828L),

tools/regression/lib/libm/test-invctrig.c

395

CMPLXL(pi / 4, 0.34657359027997265470861606072908828L),

tools/regression/lib/libm/test-invtrig.c

143

testall(acos, 0.0, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

146

testall(acos, -0.0, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

151

testall(atan, INFINITY, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

154

testall(atan, -INFINITY, -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

171

testall2(atan2, 0.0, -0.0, pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

172

testall2(atan2, -0.0, -0.0, -pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

178

testall2(atan2, INFINITY, INFINITY, pi / 4, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

179

testall2(atan2, -INFINITY, INFINITY, -pi / 4, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

186

test2(atan2f, 0.0, ldexpf(-z, e), (float)pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

187

test2(atan2f, -0.0, ldexpf(-z, e), (float)-pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

188

test2(atan2f, ldexpf(z, e), 0.0, (float)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

189

test2(atan2f, ldexpf(z, e), -0.0, (float)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

190

test2(atan2f, ldexpf(-z, e), 0.0, (float)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

191

test2(atan2f, ldexpf(-z, e), -0.0, (float)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

196

test2(atan2, 0.0, ldexp(-z, e), (double)pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

197

test2(atan2, -0.0, ldexp(-z, e), (double)-pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

198

test2(atan2, ldexp(z, e), 0.0, (double)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

199

test2(atan2, ldexp(z, e), -0.0, (double)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

200

test2(atan2, ldexp(-z, e), 0.0, (double)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

201

test2(atan2, ldexp(-z, e), -0.0, (double)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

206

test2(atan2l, 0.0, ldexpl(-z, e), pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

207

test2(atan2l, -0.0, ldexpl(-z, e), -pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

208

test2(atan2l, ldexpl(z, e), 0.0, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

209

test2(atan2l, ldexpl(z, e), -0.0, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

210

test2(atan2l, ldexpl(-z, e), 0.0, -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

211

test2(atan2l, ldexpl(-z, e), -0.0, -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

218

test2(atan2f, ldexpf(z, e), -INFINITY, (float)pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

219

test2(atan2f, ldexpf(-z,e), -INFINITY, (float)-pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

220

test2(atan2f, INFINITY, ldexpf(z,e), (float)pi/2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

221

test2(atan2f, INFINITY, ldexpf(-z,e), (float)pi/2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

222

test2(atan2f, -INFINITY, ldexpf(z,e), (float)-pi/2,FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

223

test2(atan2f, -INFINITY, ldexpf(-z,e),(float)-pi/2,FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

228

test2(atan2, ldexp(z, e), -INFINITY, (double)pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

229

test2(atan2, ldexp(-z,e), -INFINITY, (double)-pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

230

test2(atan2, INFINITY, ldexp(z,e), (double)pi/2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

231

test2(atan2, INFINITY, ldexp(-z,e), (double)pi/2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

232

test2(atan2, -INFINITY, ldexp(z,e), (double)-pi/2,FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

233

test2(atan2, -INFINITY, ldexp(-z,e),(double)-pi/2,FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

238

test2(atan2l, ldexpl(z, e), -INFINITY, pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

239

test2(atan2l, ldexpl(-z,e), -INFINITY, -pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

240

test2(atan2l, INFINITY, ldexpl(z, e), pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

241

test2(atan2l, INFINITY, ldexpl(-z, e), pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

242

test2(atan2l, -INFINITY, ldexpl(z, e), -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

243

test2(atan2l, -INFINITY, ldexpl(-z, e), -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

256

testall(asin, 1.0, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

258

testall(atan, 1.0, pi / 4, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

259

testall(asin, -1.0, -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

260

testall(acos, -1.0, pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

261

testall(atan, -1.0, -pi / 4, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

269

testall_tol(asin, sqrtl(2) / 2, pi / 4, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

270

testall_tol(acos, sqrtl(2) / 2, pi / 4, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

271

testall_tol(asin, -sqrtl(2) / 2, -pi / 4, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

281

testall_tol(atan, sqrt2m1, pi / 8, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

282

testall_tol(atan, -sqrt2m1, -pi / 8, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

293

testall2(atan2, 1.0, 1.0, pi / 4, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

295

testall2(atan2, -1.0, 1.0, -pi / 4, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

298

testall2_tol(atan2, sqrt2m1 * 2, 2.0, pi / 8, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

300

testall2_tol(atan2, -sqrt2m1 * 2, 2.0, -pi / 8, 1, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

318

testall(acos, tiny, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

322

testall(acos, -tiny, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

334

test2(atan2f, 0x1.0p-100, -0x1.0p100, (float)pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

335

test2(atan2, 0x1.0p-1000, -0x1.0p1000, (double)pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

337

-ldexpl(1.0, LDBL_MAX_EXP - 100), pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

338

test2(atan2f, -0x1.0p-100, -0x1.0p100, (float)-pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

339

test2(atan2, -0x1.0p-1000, -0x1.0p1000, (double)-pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

341

-ldexpl(1.0, LDBL_MAX_EXP - 100), -pi, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

352

testall(atan, huge, pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

353

testall(atan, -huge, -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

356

test2(atan2f, 0x1.0p100, 0x1.0p-100, (float)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

357

test2(atan2, 0x1.0p1000, 0x1.0p-1000, (double)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

359

ldexpl(1.0, 100 - LDBL_MAX_EXP), pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

360

test2(atan2f, -0x1.0p100, 0x1.0p-100, (float)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

361

test2(atan2, -0x1.0p1000, 0x1.0p-1000, (double)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

363

ldexpl(1.0, 100 - LDBL_MAX_EXP), -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

365

test2(atan2f, 0x1.0p100, -0x1.0p-100, (float)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

366

test2(atan2, 0x1.0p1000, -0x1.0p-1000, (double)pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

368

-ldexpl(1.0, 100 - LDBL_MAX_EXP), pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

369

test2(atan2f, -0x1.0p100, -0x1.0p-100, (float)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

370

test2(atan2, -0x1.0p1000, -0x1.0p-1000, (double)-pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

372

-ldexpl(1.0, 100 - LDBL_MAX_EXP), -pi / 2, FE_INEXACT);

tools/regression/lib/libm/test-invtrig.c

98

pi = 3.14159265358979323846264338327950280e+00L,

tools/tools/net80211/wesside/wesside/wesside.c

1696

void send_fragment(int tx, struct frag_state* fs, struct prga_info *pi) {

tools/tools/net80211/wesside/wesside/wesside.c

1711

memcpy(body, &pi->iv, 3);

tools/tools/net80211/wesside/wesside/wesside.c

1719

if ( (fragsize + 4) > pi->len) {

tools/tools/net80211/wesside/wesside/wesside.c

1720

fragsize = pi->len - 4;

tools/tools/net80211/wesside/wesside/wesside.c

1736

body[i] ^= pi->prga[i];

usr.bin/fstat/fstat.c

803

pipetrans(struct pipe *pi, int i, int flag)

usr.bin/fstat/fstat.c

813

if ((intptr_t)pi & 1) {

usr.bin/fstat/fstat.c

824

pi = (void *)((intptr_t)pi & ~(intptr_t)1);

usr.bin/fstat/fstat.c

827

if (!kread(pi, &pip, sizeof(struct pipe))) {

usr.bin/fstat/fstat.c

828

dprintf(stderr, "can't read pipe at %p\n", (void *)pi);

usr.bin/fstat/fstat.c

832

printf("* pipe %8lx (%c<->%c)", (u_long)pi, side1, side2);

usr.sbin/mld6query/mld6query.c

162

struct in6_pktinfo *pi;

usr.sbin/mld6query/mld6query.c

199

pi = (struct in6_pktinfo *)CMSG_DATA(cmsgp);

usr.sbin/mld6query/mld6query.c

200

pi->ipi6_ifindex = idx;

usr.sbin/mld6query/mld6query.c

201

memset(&pi->ipi6_addr, 0, sizeof(pi->ipi6_addr));

usr.sbin/pciconf/pciconf.c

735

struct pci_io pi;

usr.sbin/pciconf/pciconf.c

737

pi.pi_sel = *sel;

usr.sbin/pciconf/pciconf.c

738

pi.pi_reg = reg;

usr.sbin/pciconf/pciconf.c

739

pi.pi_width = width;

usr.sbin/pciconf/pciconf.c

741

if (ioctl(fd, PCIOCREAD, &pi) < 0)

usr.sbin/pciconf/pciconf.c

744

return (pi.pi_data);

usr.sbin/pciconf/pciconf.c

829

struct pci_io pi;

usr.sbin/pciconf/pciconf.c

831

pi.pi_sel = getsel(name);

usr.sbin/pciconf/pciconf.c

832

pi.pi_reg = strtoul(reg, (char **)0, 0); /* XXX error check */

usr.sbin/pciconf/pciconf.c

833

pi.pi_width = width;

usr.sbin/pciconf/pciconf.c

834

pi.pi_data = strtoul(data, (char **)0, 0); /* XXX error check */

usr.sbin/pciconf/pciconf.c

840

if (ioctl(fd, PCIOCWRITE, &pi) < 0)

usr.sbin/pciconf/pciconf.c

848

struct pci_io pi;

usr.sbin/pciconf/pciconf.c

850

pi.pi_sel = getsel(name);

usr.sbin/pciconf/pciconf.c

856

if (ioctl(fd, PCIOCATTACHED, &pi) < 0)

usr.sbin/pciconf/pciconf.c

859

exitstatus = pi.pi_data ? 0 : 2; /* exit(2), if NOT attached */

usr.sbin/pciconf/pciconf.c

860

printf("%s: %s%s\n", name, pi.pi_data == 0 ? "not " : "", "attached");

usr.sbin/pfctl/pfctl.c

1779

struct pfioc_if pi;

usr.sbin/pfctl/pfctl.c

1781

memset(&pi, 0, sizeof(pi));

usr.sbin/pfctl/pfctl.c

1782

if (ifname && strlcpy(pi.ifname, ifname,

usr.sbin/pfctl/pfctl.c

1783

sizeof(pi.ifname)) >= sizeof(pi.ifname)) {

usr.sbin/pfctl/pfctl.c

1787

if (ioctl(pf->dev, DIOCSETSTATUSIF, &pi)) {

usr.sbin/pfctl/pfctl.c

1867

struct pfioc_iface pi;

usr.sbin/pfctl/pfctl.c

1872

bzero(&pi, sizeof(pi));

usr.sbin/pfctl/pfctl.c

1874

pi.pfiio_flags = flags;

usr.sbin/pfctl/pfctl.c

1876

if (strlcpy(pi.pfiio_name, ifname, sizeof(pi.pfiio_name)) >=

usr.sbin/pfctl/pfctl.c

1877

sizeof(pi.pfiio_name))

usr.sbin/pfctl/pfctl.c

1882

if (ioctl(pf->dev, DIOCCLRIFFLAG, &pi))

usr.sbin/pfctl/pfctl.c

1885

if (ioctl(pf->dev, DIOCSETIFFLAG, &pi))

usr.sbin/pfctl/pfctl.c

288

struct pfioc_iface pi;

usr.sbin/pfctl/pfctl.c

291

bzero(&pi, sizeof(pi));

usr.sbin/pfctl/pfctl.c

292

pi.pfiio_flags = PFI_IFLAG_SKIP;

usr.sbin/pfctl/pfctl.c

294

if (ioctl(dev, DIOCCLRIFFLAG, &pi))

usr.sbin/route6d/route6d.c

1004

struct in6_pktinfo *pi;

usr.sbin/route6d/route6d.c

1031

pi = (struct in6_pktinfo *)(CMSG_DATA(cm));

usr.sbin/route6d/route6d.c

1032

idx = pi->ipi6_ifindex;

usr.sbin/route6d/route6d.c

938

struct in6_pktinfo *pi;

usr.sbin/route6d/route6d.c

971

pi = (struct in6_pktinfo *)CMSG_DATA(cm);

usr.sbin/route6d/route6d.c

972

memset(&pi->ipi6_addr, 0, sizeof(pi->ipi6_addr)); /*::*/

usr.sbin/route6d/route6d.c

973

pi->ipi6_ifindex = idx;

usr.sbin/rrenumd/rrenumd.c

309

struct in6_pktinfo *pi;

usr.sbin/rrenumd/rrenumd.c

325

pi = (struct in6_pktinfo *)CMSG_DATA(cm);

usr.sbin/rrenumd/rrenumd.c

326

memset(&pi->ipi6_addr, 0, sizeof(pi->ipi6_addr)); /*XXX*/

usr.sbin/rrenumd/rrenumd.c

327

pi->ipi6_ifindex = sin6->sin6_scope_id;

usr.sbin/rtadvd/rrenum.c

437

rr_input(int len, struct icmp6_router_renum *rr, struct in6_pktinfo *pi,

usr.sbin/rtadvd/rrenum.c

447

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rrenum.c

457

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rrenum.c

469

if (IN6_IS_ADDR_MULTICAST(&pi->ipi6_addr) && !IN6_ARE_ADDR_EQUAL(

usr.sbin/rtadvd/rrenum.c

470

&sin6_sitelocal_allrouters.sin6_addr, &pi->ipi6_addr)) {

usr.sbin/rtadvd/rrenum.c

478

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rrenum.c

482

rr_rcvifindex = pi->ipi6_ifindex;

usr.sbin/rtadvd/rtadvd.c

1075

struct in6_pktinfo *pi, struct sockaddr_in6 *from)

usr.sbin/rtadvd/rtadvd.c

1089

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

1103

sizeof(ntopbuf)), if_indextoname(pi->ipi6_ifindex,

usr.sbin/rtadvd/rtadvd.c

1111

ifi = if_indextoifinfo(pi->ipi6_ifindex);

usr.sbin/rtadvd/rtadvd.c

1118

sizeof(ntopbuf)), if_indextoname(pi->ipi6_ifindex,

usr.sbin/rtadvd/rtadvd.c

120

struct nd_opt_prefix_info *pi;

usr.sbin/rtadvd/rtadvd.c

128

#define opt_pi nd_opt_each.pi

usr.sbin/rtadvd/rtadvd.c

1657

struct in6_pktinfo *pi;

usr.sbin/rtadvd/rtadvd.c

1738

pi = (struct in6_pktinfo *)CMSG_DATA(cm);

usr.sbin/rtadvd/rtadvd.c

1739

memset(&pi->ipi6_addr, 0, sizeof(pi->ipi6_addr)); /*XXX*/

usr.sbin/rtadvd/rtadvd.c

1740

pi->ipi6_ifindex = ifi->ifi_ifindex;

usr.sbin/rtadvd/rtadvd.c

725

struct in6_pktinfo *pi = NULL;

usr.sbin/rtadvd/rtadvd.c

752

pi = (struct in6_pktinfo *)(CMSG_DATA(cm));

usr.sbin/rtadvd/rtadvd.c

753

ifindex = pi->ipi6_ifindex;

usr.sbin/rtadvd/rtadvd.c

754

dst = pi->ipi6_addr;

usr.sbin/rtadvd/rtadvd.c

774

ifi = if_indextoifinfo(pi->ipi6_ifindex);

usr.sbin/rtadvd/rtadvd.c

815

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

825

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

834

if_indextoname(pi->ipi6_ifindex, ifnamebuf), i);

usr.sbin/rtadvd/rtadvd.c

837

rs_input(i, (struct nd_router_solicit *)icp, pi, &rcvfrom);

usr.sbin/rtadvd/rtadvd.c

850

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

860

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

870

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

879

if_indextoname(pi->ipi6_ifindex, ifnamebuf), i);

usr.sbin/rtadvd/rtadvd.c

882

ra_input(i, (struct nd_router_advert *)icp, pi, &rcvfrom);

usr.sbin/rtadvd/rtadvd.c

890

rr_input(i, (struct icmp6_router_renum *)icp, pi, &rcvfrom,

usr.sbin/rtadvd/rtadvd.c

909

struct in6_pktinfo *pi, struct sockaddr_in6 *from)

usr.sbin/rtadvd/rtadvd.c

922

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

935

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

949

__func__, if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtadvd/rtadvd.c

953

ifi = if_indextoifinfo(pi->ipi6_ifindex);

usr.sbin/rtadvd/rtadvd.c

957

__func__, pi->ipi6_ifindex);

usr.sbin/rtadvd/rtadvd.c

965

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtsold/probe.c

150

struct in6_pktinfo *pi;

usr.sbin/rtsold/probe.c

168

pi = (struct in6_pktinfo *)CMSG_DATA(cm);

usr.sbin/rtsold/probe.c

169

memset(&pi->ipi6_addr, 0, sizeof(pi->ipi6_addr)); /*XXX*/

usr.sbin/rtsold/probe.c

170

pi->ipi6_ifindex = ifindex;

usr.sbin/rtsold/rtsol.c

188

struct in6_pktinfo *pi;

usr.sbin/rtsold/rtsol.c

199

pi = (struct in6_pktinfo *)CMSG_DATA(cm);

usr.sbin/rtsold/rtsol.c

200

memset(&pi->ipi6_addr, 0, sizeof(pi->ipi6_addr)); /*XXX*/

usr.sbin/rtsold/rtsol.c

201

pi->ipi6_ifindex = ifinfo->sdl->sdl_index;

usr.sbin/rtsold/rtsol.c

242

struct in6_pktinfo *pi = NULL;

usr.sbin/rtsold/rtsol.c

259

pi = (struct in6_pktinfo *)(CMSG_DATA(cm));

usr.sbin/rtsold/rtsol.c

260

ifindex = pi->ipi6_ifindex;

usr.sbin/rtsold/rtsol.c

292

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtsold/rtsol.c

301

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtsold/rtsol.c

311

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtsold/rtsol.c

315

if (pi && !IN6_IS_ADDR_LINKLOCAL(&from.sin6_addr)) {

usr.sbin/rtsold/rtsol.c

320

if_indextoname(pi->ipi6_ifindex, ifnamebuf));

usr.sbin/rtsold/rtsol.c

326

if ((ifi = find_ifinfo(pi->ipi6_ifindex)) == NULL) {

usr.sbin/rtsold/rtsol.c

331

if_indextoname(pi->ipi6_ifindex, ifnamebuf));