sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

533

low = lower_32_bits(queue_address >> 8);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

845

lower_32_bits(page_table_base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1035

lower_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1039

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1046

lower_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1050

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

473

lower_32_bits(guessed_wptr));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

477

lower_32_bits((uintptr_t)wptr));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

577

lower_32_bits(data64));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

645

low = lower_32_bits(queue_address >> 8);

sys/dev/drm/amd/amdgpu/amdgpu_fence.c

362

return lower_32_bits(emitted);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

156

cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

212

cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);

sys/dev/drm/amd/amdgpu/amdgpu_psp.c

216

cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);

sys/dev/drm/amd/amdgpu/amdgpu_uvd.c

827

lower_32_bits(start));

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

1039

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/amdgpu_vce.c

656

amdgpu_set_ib_value(p, ib_idx, lo, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

253

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

254

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

260

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

261

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

315

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/atom.c

694

ctx->ctx->divmul[0] = lower_32_bits(val64);

sys/dev/drm/amd/amdgpu/atom.c

815

ctx->ctx->divmul[0] = lower_32_bits(val64);

sys/dev/drm/amd/amdgpu/cik_ih.c

135

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/cik_sdma.c

1333

ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1335

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1355

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/cik_sdma.c

196

(lower_32_bits(ring->wptr) << 2) & 0x3fffc);

sys/dev/drm/amd/amdgpu/cik_sdma.c

227

cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);

sys/dev/drm/amd/amdgpu/cik_sdma.c

278

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/cik_sdma.c

280

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/cik_sdma.c

286

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/cik_sdma.c

484

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/cik_sdma.c

637

amdgpu_ring_write(ring, lower_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/cik_sdma.c

698

ib.ptr[1] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/cik_sdma.c

753

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/amd/amdgpu/cik_sdma.c

755

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/cik_sdma.c

778

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/cik_sdma.c

782

ib->ptr[ib->length_dw++] = lower_32_bits(value);

sys/dev/drm/amd/amdgpu/cik_sdma.c

806

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

sys/dev/drm/amd/amdgpu/cik_sdma.c

808

ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */

sys/dev/drm/amd/amdgpu/cik_sdma.c

810

ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */

sys/dev/drm/amd/amdgpu/cz_ih.c

137

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2295

lower_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/drm/amd/amdgpu/dce_v10_0.c

248

lower_32_bits(crtc_base));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2374

lower_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/drm/amd/amdgpu/dce_v11_0.c

266

lower_32_bits(crtc_base));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

193

lower_32_bits(crtc_base));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2196

lower_32_bits(amdgpu_crtc->cursor_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2175

amdgpu_ring_write(ring, lower_32_bits(seq - 1));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2187

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2216

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2597

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2601

WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2642

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2657

adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2658

WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2988

mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3966

WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1679

ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1705

ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1731

ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4361

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4365

WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4369

WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4449

amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4470

amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4472

amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4519

mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6083

adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6084

WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6086

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6197

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6255

adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6256

WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6374

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6388

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6390

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6447

amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6479

amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7204

amdgpu_ring_write(ring, lower_32_bits(ce_payload_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7221

de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7226

de_payload.regular.gds_backup_addrlo = lower_32_bits(gds_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7237

amdgpu_ring_write(ring, lower_32_bits(de_payload_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

904

ib.ptr[2] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1611

base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1619

base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

1627

base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2692

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2697

WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2701

WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2841

amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2865

amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2867

amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2896

lower_32_bits(ring->mqd_gpu_addr

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4042

WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4102

lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4119

lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4151

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4153

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4165

lower_32_bits(addr), upper_32_bits(addr),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4323

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4325

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4358

amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4371

de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4380

amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4429

amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4460

amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

461

ib.ptr[2] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

239

lower_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/gfxhub_v1_0.c

43

lower_32_bits(value));

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

438

lower_32_bits(pd_addr));

sys/dev/drm/amd/amdgpu/iceland_ih.c

137

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

258

lower_32_bits(adev->vm_manager.max_pfn - 1));

sys/dev/drm/amd/amdgpu/mmhub_v1_0.c

60

lower_32_bits(value));

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

108

lower_32_bits(adev->doorbell.base));

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

103

lower_32_bits(adev->doorbell.base));

sys/dev/drm/amd/amdgpu/psp_v10_0.c

168

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

214

psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

315

write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

317

write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

236

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

282

psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

380

write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

382

write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

286

cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

332

psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

435

write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

437

write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1217

ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1219

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1239

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

223

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

252

sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

257

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

308

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

310

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

316

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

452

lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

460

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

571

amdgpu_ring_write(ring, lower_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

632

ib.ptr[1] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

691

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

693

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

720

ib->ptr[ib->length_dw++] = lower_32_bits(value);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

744

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

746

ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

748

ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1015

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1017

ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1019

ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1656

ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1658

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1678

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

389

WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

390

WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

394

WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

396

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

426

sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

431

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

482

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

484

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

490

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

691

lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

713

lower_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

843

amdgpu_ring_write(ring, lower_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

904

ib.ptr[1] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

962

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

964

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

987

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

991

ib->ptr[ib->length_dw++] = lower_32_bits(value);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1015

amdgpu_ring_write(ring, lower_32_bits(gpu_addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1076

ib.ptr[1] = lower_32_bits(gpu_addr);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1135

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1137

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1162

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1166

ib->ptr[ib->length_dw++] = lower_32_bits(value);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1191

ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1193

ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1195

ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1780

ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1782

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1802

ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

406

lower_32_bits(ring->wptr << 2),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

418

lower_32_bits(ring->wptr << 2),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

421

WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

452

sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

457

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

532

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

534

amdgpu_ring_write(ring, lower_32_bits(seq));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

542

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

722

lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

735

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

775

lower_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/tonga_ih.c

143

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

364

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

90

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

262

lower_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

413

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

421

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

542

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

87

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1014

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1034

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1071

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1100

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

142

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

158

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

161

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

594

lower_32_bits(adev->uvd.inst->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

836

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

844

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

850

WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

851

WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

857

WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

858

WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1084

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1093

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1099

WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1100

WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1106

WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1107

WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1314

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1336

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1386

data1 = lower_32_bits(pd_addr);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

140

WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1428

lower_32_bits(pd_addr), 0xffffffff);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

156

adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

157

WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

163

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

166

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

681

lower_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

692

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

699

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

729

WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

814

lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

820

lower_32_bits(adev->uvd.inst[i].gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

831

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

838

lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

244

WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

245

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

251

WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

252

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

94

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

96

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

154

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

156

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

158

WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

282

WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

283

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

289

WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

290

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

296

WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

297

WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

845

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

868

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

108

adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

109

WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

115

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

118

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

121

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

163

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

234

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

337

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

338

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

345

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

346

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

353

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

354

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

959

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

999

lower_32_bits(pd_addr), 0xffffffff);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1082

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1093

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1283

lower_32_bits(ring->wptr) | 0x80000000);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1285

WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1382

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1421

data1 = lower_32_bits(pd_addr);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1489

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1492

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1533

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1557

lower_32_bits(pd_addr), 0xffffffff);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1608

WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1674

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1698

amdgpu_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1745

amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1757

amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1820

data1 = lower_32_bits(pd_addr);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

1882

val = lower_32_bits(ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

297

lower_32_bits(adev->vcn.gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

309

lower_32_bits(adev->vcn.gpu_addr + offset));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

317

lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

367

lower_32_bits(adev->vcn.gpu_addr), 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

379

lower_32_bits(adev->vcn.gpu_addr + offset), 0xFFFFFFFF, 0);

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

389

lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

909

lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

920

lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

926

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

927

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

933

WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

934

WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vcn_v1_0.c

943

WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vega10_ih.c

131

WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3544

plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3550

= lower_32_bits(afb->address);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3555

= lower_32_bits(chroma_addr);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4321

attributes.address.low_part = lower_32_bits(address);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4442

addr.address.grph.addr.low_part = lower_32_bits(afb->address);

sys/dev/drm/amd/powerplay/amd_powerplay.c

160

lower_32_bits((unsigned long)cpu_ptr),

sys/dev/drm/amd/powerplay/amd_powerplay.c

162

lower_32_bits(gpu_addr),

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

132

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu10_smumgr.c

164

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

320

entry->image_addr_low = lower_32_bits(info.mc_addr);

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

361

lower_32_bits(smu_data->smu_buffer.mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu7_smumgr.c

427

smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

211

reg_data = lower_32_bits(info.mc_addr) &

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

354

task->addr.low = lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr);

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

391

task->addr.low = lower_32_bits(smu8_smu->driver_buffer[i].mc_addr);

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

624

lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

651

lower_32_bits(smu8_smu->scratch_buffer[i].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/smu8_smumgr.c

685

lower_32_bits(smu8_smu->toc_buffer.mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

135

lower_32_bits(priv->smu_tables.entry[TOOLSTABLE].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

52

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega10_smumgr.c

83

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

101

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

193

lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));

sys/dev/drm/amd/powerplay/smumgr/vega12_smumgr.c

58

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr)) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

184

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

227

lower_32_bits(priv->smu_tables.entry[table_id].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

255

lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

280

lower_32_bits(priv->smu_tables.entry[TABLE_ACTIVITY_MONITOR_COEFF].mc_addr))) == 0,

sys/dev/drm/amd/powerplay/smumgr/vega20_smumgr.c

366

lower_32_bits(priv->smu_tables.entry[TABLE_PMSTATUSLOG].mc_addr));

sys/dev/drm/i915/i915_drv.c

526

lower_32_bits(rman_get_start(dev_priv->mch_res)));

sys/dev/drm/i915/i915_gem_execbuffer.c

1290

*batch++ = lower_32_bits(addr);

sys/dev/drm/i915/i915_gem_execbuffer.c

1292

*batch++ = lower_32_bits(target_offset);

sys/dev/drm/i915/i915_gem_execbuffer.c

1297

*batch++ = lower_32_bits(addr);

sys/dev/drm/i915/i915_gem_execbuffer.c

1302

*batch++ = lower_32_bits(addr);

sys/dev/drm/i915/i915_gem_execbuffer.c

1304

*batch++ = lower_32_bits(target_offset);

sys/dev/drm/i915/i915_gem_execbuffer.c

1334

lower_32_bits(target_offset),

sys/dev/drm/i915/i915_gem_execbuffer.c

2265

in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));

sys/dev/drm/i915/i915_gem_fence_reg.c

111

I915_WRITE(fence_reg_lo, lower_32_bits(val));

sys/dev/drm/i915/i915_gem_gtt.c

1318

I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));

sys/dev/drm/i915/i915_gem_gtt.c

1327

I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));

sys/dev/drm/i915/i915_gem_gtt.c

2394

lower_32_bits(fault_addr),

sys/dev/drm/i915/i915_gem_gtt.c

3234

I915_WRITE(GEN8_PRIVATE_PAT_LO, lower_32_bits(pat));

sys/dev/drm/i915/i915_gem_render_state.c

98

s = lower_32_bits(r);

sys/dev/drm/i915/i915_gpu_error.c

384

lower_32_bits(err->gtt_offset),

sys/dev/drm/i915/i915_gpu_error.c

494

upper_32_bits(start), lower_32_bits(start),

sys/dev/drm/i915/i915_gpu_error.c

495

upper_32_bits(end), lower_32_bits(end));

sys/dev/drm/i915/i915_gpu_error.c

505

lower_32_bits(ee->faddr));

sys/dev/drm/i915/i915_gpu_error.c

578

lower_32_bits(obj->gtt_offset));

sys/dev/drm/i915/i915_gpu_error.c

782

lower_32_bits(obj->gtt_offset));

sys/dev/drm/i915/i915_perf.c

1277

lower_32_bits(ce->lrc_desc) >> 12;

sys/dev/drm/i915/i915_vma.h

208

return lower_32_bits(vma->node.start);

sys/dev/drm/i915/intel_engine_cs.c

1321

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/drm/i915/intel_engine_cs.c

1324

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/drm/i915/intel_engine_cs.c

1333

upper_32_bits(addr), lower_32_bits(addr));

sys/dev/drm/i915/intel_engine_cs.c

1417

rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u,

sys/dev/drm/i915/intel_guc_fw.c

169

I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));

sys/dev/drm/i915/intel_guc_submission.c

387

lrc->context_desc = lower_32_bits(ce->lrc_desc);

sys/dev/drm/i915/intel_guc_submission.c

522

u32 ctx_desc = lower_32_bits(rq->hw_context->lrc_desc);

sys/dev/drm/i915/intel_guc_submission.c

589

guc_wq_item_append(client, engine->guc_id, lower_32_bits(ce->lrc_desc),

sys/dev/drm/i915/intel_huc_fw.c

123

I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));

sys/dev/drm/i915/intel_lrc.c

2041

*cs++ = lower_32_bits(pd_daddr);

sys/dev/drm/i915/intel_lrc.c

2100

*cs++ = lower_32_bits(offset);

sys/dev/drm/i915/intel_lrc.c

462

writel(lower_32_bits(desc), execlists->submit_reg + port * 2);

sys/dev/drm/i915/intel_lrc.c

466

writel(lower_32_bits(desc), execlists->submit_reg);

sys/dev/drm/i915/intel_lrc_reg.h

53

(reg_state__)[CTX_PDP ## n ## _LDW + 1] = lower_32_bits(addr__); \

sys/dev/drm/i915/intel_lrc_reg.h

60

(reg_state__)[CTX_PDP0_LDW + 1] = lower_32_bits(addr__); \

sys/dev/drm/i915/intel_ringbuffer.c

389

addr = lower_32_bits(phys);

sys/dev/drm/include/drm/drm_fixed.h

69

return lower_32_bits(tmp);

sys/dev/drm/radeon/cik.c

3646

radeon_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/radeon/cik.c

3708

radeon_ring_write(ring, lower_32_bits(src_offset));

sys/dev/drm/radeon/cik.c

3710

radeon_ring_write(ring, lower_32_bits(dst_offset));

sys/dev/drm/radeon/cik.c

6646

WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));

sys/dev/drm/radeon/cik_sdma.c

206

radeon_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/radeon/cik_sdma.c

612

radeon_ring_write(ring, lower_32_bits(src_offset));

sys/dev/drm/radeon/cik_sdma.c

614

radeon_ring_write(ring, lower_32_bits(dst_offset));

sys/dev/drm/radeon/cik_sdma.c

668

radeon_ring_write(ring, lower_32_bits(gpu_addr));

sys/dev/drm/radeon/cik_sdma.c

726

ib.ptr[1] = lower_32_bits(gpu_addr);

sys/dev/drm/radeon/cik_sdma.c

815

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/radeon/cik_sdma.c

817

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/radeon/evergreen.c

4270

dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));

sys/dev/drm/radeon/ni.c

1429

radeon_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/radeon/ni_dma.c

327

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/radeon/ni_dma.c

328

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/radeon/r100.c

3866

WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));

sys/dev/drm/radeon/r100.c

696

gtt[i] = cpu_to_le32(lower_32_bits(entry));

sys/dev/drm/radeon/r300.c

1336

WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));

sys/dev/drm/radeon/r300.c

99

addr = (lower_32_bits(addr) >> 8) |

sys/dev/drm/radeon/r520.c

155

WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base));

sys/dev/drm/radeon/r600.c

2897

radeon_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/radeon/r600.c

2947

radeon_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/radeon/r600.c

3012

radeon_ring_write(ring, lower_32_bits(src_offset));

sys/dev/drm/radeon/r600.c

3014

radeon_ring_write(ring, lower_32_bits(dst_offset));

sys/dev/drm/radeon/r600_dma.c

253

radeon_ring_write(ring, lower_32_bits(gpu_addr));

sys/dev/drm/radeon/r600_dma.c

295

radeon_ring_write(ring, lower_32_bits(fence->seq));

sys/dev/drm/radeon/r600_dma.c

358

ib.ptr[1] = lower_32_bits(gpu_addr);

sys/dev/drm/radeon/radeon_cursor.c

100

lower_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_cursor.c

116

lower_32_bits(radeon_crtc->cursor_addr));

sys/dev/drm/radeon/radeon_fence.c

91

seq = lower_32_bits(atomic64_read(&drv->last_seq));

sys/dev/drm/radeon/rs400.c

217

entry = (lower_32_bits(addr) & LINUX_PAGE_MASK) |

sys/dev/drm/radeon/rs400.c

232

gtt[i] = cpu_to_le32(lower_32_bits(entry));

sys/dev/drm/radeon/rv515.c

486

WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));

sys/dev/drm/radeon/si.c

3381

radeon_ring_write(ring, lower_32_bits(addr));

sys/dev/drm/radeon/si_dma.c

264

radeon_ring_write(ring, lower_32_bits(dst_offset));

sys/dev/drm/radeon/si_dma.c

265

radeon_ring_write(ring, lower_32_bits(src_offset));

sys/dev/drm/radeon/si_dma.c

81

ib->ptr[ib->length_dw++] = lower_32_bits(pe);

sys/dev/drm/radeon/si_dma.c

82

ib->ptr[ib->length_dw++] = lower_32_bits(src);

sys/dev/drm/radeon/uvd_v2_2.c

48

radeon_ring_write(ring, lower_32_bits(addr));