sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1582

union lane_status lane_status;

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1600

lane_status.raw = get_nibble_at_index(

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1604

if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1605

!lane_status.bits.CR_DONE_0 ||

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

1606

!lane_status.bits.SYMBOL_LOCKED_0) {

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

256

union lane_status *dpcd_lane_status)

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

270

union lane_status *dpcd_lane_status,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

427

union lane_status *ln_status,

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

615

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

705

union lane_status *dpcd_lane_status)

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

729

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };

sys/dev/drm/amd/display/dc/core/dc_link_dp.c

793

union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

sys/dev/drm/amd/display/dc/dc_dp_types.h

345

union lane_status lane01_status;/* 202h */

sys/dev/drm/amd/display/dc/dc_dp_types.h

346

union lane_status lane23_status;/* 203h */

sys/dev/drm/drm_dp_helper.c

64

u8 lane_status;

sys/dev/drm/drm_dp_helper.c

72

lane_status = dp_get_lane_status(link_status, lane);

sys/dev/drm/drm_dp_helper.c

73

if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)

sys/dev/drm/drm_dp_helper.c

84

u8 lane_status;

sys/dev/drm/drm_dp_helper.c

87

lane_status = dp_get_lane_status(link_status, lane);

sys/dev/drm/drm_dp_helper.c

88

if ((lane_status & DP_LANE_CR_DONE) == 0)