sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2271

struct dcp_gsl_params gsl_params = { 0 };

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2279

gsl_params.gsl_group = 0;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2280

gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2284

grouped_pipes[i]->stream_res.tg, &gsl_params);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2292

gsl_params.gsl_group);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2316

struct dcp_gsl_params gsl_params = { 0 };

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2319

gsl_params.gsl_group = 0;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2320

gsl_params.gsl_master = grouped_pipes[0]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2324

grouped_pipes[i]->stream_res.tg, &gsl_params);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2331

gsl_params.gsl_master,

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1216

const struct dcp_gsl_params *gsl_params)

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1232

gsl_params->gsl_master == tg->inst,

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1252

gsl_params->gsl_master,

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.h

171

const struct dcp_gsl_params *gsl_params);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

617

const struct dcp_gsl_params *gsl_params)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

257

const struct dcp_gsl_params *gsl_params)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

276

FD(DCP0_DCP_GSL_CONTROL__DCP_GSL_MASTER_EN), gsl_params->gsl_master == tg->inst,

sys/dev/drm/amd/display/dc/inc/hw/timing_generator.h

178

const struct dcp_gsl_params *gsl_params);