crypto/libressl/crypto/asn1/a_pkey.c
91
ENGINE_finish(ret->engine);
crypto/libressl/crypto/asn1/a_pkey.c
92
ret->engine = NULL;
crypto/libressl/crypto/cmac/cm_pmeth.c
146
if (!CMAC_Init(cmctx, NULL, 0, p2, ctx->engine))
crypto/libressl/crypto/dh/dh_lib.c
103
ENGINE_finish(dh->engine);
crypto/libressl/crypto/dh/dh_lib.c
104
dh->engine = NULL;
crypto/libressl/crypto/dh/dh_lib.c
119
DH_new_method(ENGINE *engine)
crypto/libressl/crypto/dh/dh_lib.c
131
if (engine) {
crypto/libressl/crypto/dh/dh_lib.c
132
if (!ENGINE_init(engine)) {
crypto/libressl/crypto/dh/dh_lib.c
137
ret->engine = engine;
crypto/libressl/crypto/dh/dh_lib.c
139
ret->engine = ENGINE_get_default_DH();
crypto/libressl/crypto/dh/dh_lib.c
140
if(ret->engine) {
crypto/libressl/crypto/dh/dh_lib.c
141
ret->meth = ENGINE_get_DH(ret->engine);
crypto/libressl/crypto/dh/dh_lib.c
144
ENGINE_finish(ret->engine);
crypto/libressl/crypto/dh/dh_lib.c
169
ENGINE_finish(ret->engine);
crypto/libressl/crypto/dh/dh_lib.c
192
ENGINE_finish(r->engine);
crypto/libressl/crypto/dh/dh_lib.c
264
return dh->engine;
crypto/libressl/crypto/dh/dh_local.h
103
ENGINE *engine;
crypto/libressl/crypto/dsa/dsa_lib.c
114
ENGINE_finish(dsa->engine);
crypto/libressl/crypto/dsa/dsa_lib.c
115
dsa->engine = NULL;
crypto/libressl/crypto/dsa/dsa_lib.c
124
DSA_new_method(ENGINE *engine)
crypto/libressl/crypto/dsa/dsa_lib.c
135
if (engine) {
crypto/libressl/crypto/dsa/dsa_lib.c
136
if (!ENGINE_init(engine)) {
crypto/libressl/crypto/dsa/dsa_lib.c
141
ret->engine = engine;
crypto/libressl/crypto/dsa/dsa_lib.c
143
ret->engine = ENGINE_get_default_DSA();
crypto/libressl/crypto/dsa/dsa_lib.c
144
if (ret->engine) {
crypto/libressl/crypto/dsa/dsa_lib.c
145
ret->meth = ENGINE_get_DSA(ret->engine);
crypto/libressl/crypto/dsa/dsa_lib.c
148
ENGINE_finish(ret->engine);
crypto/libressl/crypto/dsa/dsa_lib.c
173
ENGINE_finish(ret->engine);
crypto/libressl/crypto/dsa/dsa_lib.c
198
ENGINE_finish(r->engine);
crypto/libressl/crypto/dsa/dsa_lib.c
418
return d->engine;
crypto/libressl/crypto/dsa/dsa_locl.h
110
ENGINE *engine;
crypto/libressl/crypto/ec/ec_key.c
117
ENGINE_finish(r->engine);
crypto/libressl/crypto/ec/ec_key.c
143
if (ENGINE_finish(dest->engine) == 0)
crypto/libressl/crypto/ec/ec_key.c
145
dest->engine = NULL;
crypto/libressl/crypto/ec/ec_key.c
203
if (src->engine != NULL && ENGINE_init(src->engine) == 0)
crypto/libressl/crypto/ec/ec_key.c
205
dest->engine = src->engine;
crypto/libressl/crypto/ec/ec_key.c
222
if ((ret = EC_KEY_new_method(ec_key->engine)) == NULL)
crypto/libressl/crypto/ec/ec_kmeth.c
126
ENGINE_finish(key->engine);
crypto/libressl/crypto/ec/ec_kmeth.c
127
key->engine = NULL;
crypto/libressl/crypto/ec/ec_kmeth.c
137
EC_KEY_new_method(ENGINE *engine)
crypto/libressl/crypto/ec/ec_kmeth.c
147
if (engine != NULL) {
crypto/libressl/crypto/ec/ec_kmeth.c
148
if (!ENGINE_init(engine)) {
crypto/libressl/crypto/ec/ec_kmeth.c
152
ret->engine = engine;
crypto/libressl/crypto/ec/ec_kmeth.c
154
ret->engine = ENGINE_get_default_EC();
crypto/libressl/crypto/ec/ec_kmeth.c
155
if (ret->engine) {
crypto/libressl/crypto/ec/ec_kmeth.c
156
ret->meth = ENGINE_get_EC(ret->engine);
crypto/libressl/crypto/ec/ec_lcl.h
253
ENGINE *engine;
crypto/libressl/crypto/ecdh/ech_lib.c
112
ENGINE_finish(ecdh->engine);
crypto/libressl/crypto/ecdh/ech_lib.c
113
ecdh->engine = NULL;
crypto/libressl/crypto/ecdh/ech_lib.c
120
ECDH_DATA_new_method(ENGINE *engine)
crypto/libressl/crypto/ecdh/ech_lib.c
133
ret->engine = engine;
crypto/libressl/crypto/ecdh/ech_lib.c
135
if (!ret->engine)
crypto/libressl/crypto/ecdh/ech_lib.c
136
ret->engine = ENGINE_get_default_ECDH();
crypto/libressl/crypto/ecdh/ech_lib.c
137
if (ret->engine) {
crypto/libressl/crypto/ecdh/ech_lib.c
138
ret->meth = ENGINE_get_ECDH(ret->engine);
crypto/libressl/crypto/ecdh/ech_lib.c
141
ENGINE_finish(ret->engine);
crypto/libressl/crypto/ecdh/ech_lib.c
177
ENGINE_finish(r->engine);
crypto/libressl/crypto/ecdh/ech_locl.h
83
ENGINE *engine;
crypto/libressl/crypto/ecdsa/ecs_lib.c
100
ecdsa->engine = NULL;
crypto/libressl/crypto/ecdsa/ecs_lib.c
108
ECDSA_DATA_new_method(ENGINE *engine)
crypto/libressl/crypto/ecdsa/ecs_lib.c
121
ret->engine = engine;
crypto/libressl/crypto/ecdsa/ecs_lib.c
123
if (!ret->engine)
crypto/libressl/crypto/ecdsa/ecs_lib.c
124
ret->engine = ENGINE_get_default_ECDSA();
crypto/libressl/crypto/ecdsa/ecs_lib.c
125
if (ret->engine) {
crypto/libressl/crypto/ecdsa/ecs_lib.c
126
ret->meth = ENGINE_get_ECDSA(ret->engine);
crypto/libressl/crypto/ecdsa/ecs_lib.c
129
ENGINE_finish(ret->engine);
crypto/libressl/crypto/ecdsa/ecs_lib.c
165
ENGINE_finish(r->engine);
crypto/libressl/crypto/ecdsa/ecs_lib.c
99
ENGINE_finish(ecdsa->engine);
crypto/libressl/crypto/ecdsa/ecs_locl.h
70
ENGINE *engine;
crypto/libressl/crypto/evp/digest.c
144
if (ctx->engine && ctx->digest && (!type ||
crypto/libressl/crypto/evp/digest.c
151
ENGINE_finish(ctx->engine);
crypto/libressl/crypto/evp/digest.c
174
ctx->engine = impl;
crypto/libressl/crypto/evp/digest.c
176
ctx->engine = NULL;
crypto/libressl/crypto/evp/digest.c
271
if (in->engine && !ENGINE_init(in->engine)) {
crypto/libressl/crypto/evp/digest.c
401
ENGINE_finish(ctx->engine);
crypto/libressl/crypto/evp/evp_enc.c
102
if (ctx->engine && ctx->cipher &&
crypto/libressl/crypto/evp/evp_enc.c
139
ctx->engine = impl;
crypto/libressl/crypto/evp/evp_enc.c
141
ctx->engine = NULL;
crypto/libressl/crypto/evp/evp_enc.c
614
ENGINE_finish(c->engine);
crypto/libressl/crypto/evp/evp_enc.c
689
if (in->engine && !ENGINE_init(in->engine)) {
crypto/libressl/crypto/evp/evp_locl.h
127
ENGINE *engine; /* functional reference if 'digest' is ENGINE-provided */
crypto/libressl/crypto/evp/evp_locl.h
156
ENGINE *engine; /* functional reference if 'cipher' is ENGINE-provided */
crypto/libressl/crypto/evp/evp_locl.h
193
ENGINE *engine;
crypto/libressl/crypto/evp/evp_locl.h
85
ENGINE *engine;
crypto/libressl/crypto/evp/p_lib.c
213
ret->engine = NULL;
crypto/libressl/crypto/evp/p_lib.c
249
ENGINE_finish(pkey->engine);
crypto/libressl/crypto/evp/p_lib.c
250
pkey->engine = NULL;
crypto/libressl/crypto/evp/p_lib.c
267
pkey->engine = e;
crypto/libressl/crypto/evp/p_lib.c
532
ENGINE_finish(x->engine);
crypto/libressl/crypto/evp/p_lib.c
533
x->engine = NULL;
crypto/libressl/crypto/evp/pmeth_lib.c
172
if (pkey && pkey->engine)
crypto/libressl/crypto/evp/pmeth_lib.c
173
e = pkey->engine;
crypto/libressl/crypto/evp/pmeth_lib.c
206
ret->engine = e;
crypto/libressl/crypto/evp/pmeth_lib.c
291
if (pctx->engine && !ENGINE_init(pctx->engine)) {
crypto/libressl/crypto/evp/pmeth_lib.c
302
rctx->engine = pctx->engine;
crypto/libressl/crypto/evp/pmeth_lib.c
350
ENGINE_finish(ctx->engine);
crypto/libressl/crypto/hmac/hm_pmeth.c
207
ctx->engine))
crypto/libressl/crypto/rand/rand_lib.c
47
RAND_set_rand_engine(ENGINE *engine)
crypto/libressl/crypto/rsa/rsa_lib.c
121
ENGINE_finish(rsa->engine);
crypto/libressl/crypto/rsa/rsa_lib.c
122
rsa->engine = NULL;
crypto/libressl/crypto/rsa/rsa_lib.c
131
RSA_new_method(ENGINE *engine)
crypto/libressl/crypto/rsa/rsa_lib.c
143
if (engine != NULL) {
crypto/libressl/crypto/rsa/rsa_lib.c
144
if (!ENGINE_init(engine)) {
crypto/libressl/crypto/rsa/rsa_lib.c
148
ret->engine = engine;
crypto/libressl/crypto/rsa/rsa_lib.c
150
ret->engine = ENGINE_get_default_RSA();
crypto/libressl/crypto/rsa/rsa_lib.c
153
if (ret->engine != NULL) {
crypto/libressl/crypto/rsa/rsa_lib.c
154
if ((ret->meth = ENGINE_get_RSA(ret->engine)) == NULL) {
crypto/libressl/crypto/rsa/rsa_lib.c
176
ENGINE_finish(ret->engine);
crypto/libressl/crypto/rsa/rsa_lib.c
198
ENGINE_finish(r->engine);
crypto/libressl/crypto/rsa/rsa_locl.h
56
ENGINE *engine;
crypto/libressl/include/openssl/dh.h
135
DH *DH_new_method(ENGINE *engine);
crypto/libressl/include/openssl/dsa.h
138
DSA * DSA_new_method(ENGINE *engine);
crypto/libressl/include/openssl/ec.h
989
EC_KEY *EC_KEY_new_method(ENGINE *engine);
crypto/libressl/include/openssl/rand.h
87
int RAND_set_rand_engine(ENGINE *engine);
crypto/libressl/include/openssl/rsa.h
239
RSA *RSA_new_method(ENGINE *engine);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c
448
int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c
459
switch (engine) {
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c
470
pr_err("Invalid engine in IB submission: %d\n", engine);
sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.h
119
int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3998
cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
sys/dev/drm/amd/display/dc/core/dc_link.c
1578
cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
sys/dev/drm/amd/display/dc/core/dc_link_ddc.c
420
.engine = DDC_I2C_COMMAND_ENGINE,
sys/dev/drm/amd/display/dc/core/dc_link_ddc.c
612
.engine = DDC_I2C_COMMAND_ENGINE,
sys/dev/drm/amd/display/dc/dc_ddc_types.h
104
enum i2c_command_engine engine;
sys/dev/drm/amd/display/dc/dce/dce_aux.c
158
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
161
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
250
static int read_channel_reply(struct aux_engine *engine, uint32_t size,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
254
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
303
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
310
bytes_replied = read_channel_reply(engine, reply->length, reply->data,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
356
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
359
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
36
engine->ctx->logger
sys/dev/drm/amd/display/dc/dce/dce_aux.c
418
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
421
engine->funcs->process_channel_reply(engine, &ctx->reply);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
481
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
486
engine->funcs->submit_channel_request(engine, &ctx->request);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
488
operation_result = engine->funcs->get_channel_status(
sys/dev/drm/amd/display/dc/dce/dce_aux.c
489
engine, &ctx->returned_byte);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
504
process_read_reply(engine, ctx);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
54
struct aux_engine *engine)
sys/dev/drm/amd/display/dc/dce/dce_aux.c
543
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
56
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
58
dal_ddc_close(engine->ddc);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
586
process_read_request(engine, &ctx);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
592
msleep(engine->delay);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
60
engine->ddc = NULL;
sys/dev/drm/amd/display/dc/dce/dce_aux.c
607
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
610
engine->funcs->process_channel_reply(engine, &ctx->reply);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
675
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
680
engine->funcs->submit_channel_request(engine, &ctx->request);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
682
operation_result = engine->funcs->get_channel_status(
sys/dev/drm/amd/display/dc/dce/dce_aux.c
683
engine, &ctx->returned_byte);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
69
struct aux_engine *engine)
sys/dev/drm/amd/display/dc/dce/dce_aux.c
693
process_write_reply(engine, ctx);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
71
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
731
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
769
(engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
sys/dev/drm/amd/display/dc/dce/dce_aux.c
770
engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
sys/dev/drm/amd/display/dc/dce/dce_aux.c
776
process_write_request(engine, &ctx);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
782
msleep(engine->delay);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
796
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
82
struct aux_engine *engine)
sys/dev/drm/amd/display/dc/dce/dce_aux.c
824
return read_command(engine, &dummy_request, false);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
826
return write_command(engine, &dummy_request, false);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
831
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
84
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
841
result = read_command(engine, request, mot_used);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
844
result = write_command(engine, request, mot_used);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
856
end_of_transaction_command(engine, request);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
865
const struct aux_engine *engine)
sys/dev/drm/amd/display/dc/dce/dce_aux.c
871
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/dce/dce_aux.c
877
if (engine->funcs->is_engine_available) {
sys/dev/drm/amd/display/dc/dce/dce_aux.c
879
if (!engine->funcs->is_engine_available(engine))
sys/dev/drm/amd/display/dc/dce/dce_aux.c
889
if (!engine->funcs->acquire_engine(engine)) {
sys/dev/drm/amd/display/dc/dce/dce_aux.c
894
engine->ddc = ddc;
sys/dev/drm/amd/display/dc/dce/dce_aux.c
913
void dce110_engine_destroy(struct aux_engine **engine)
sys/dev/drm/amd/display/dc/dce/dce_aux.c
916
struct aux_engine_dce110 *engine110 = FROM_AUX_ENGINE(*engine);
sys/dev/drm/amd/display/dc/dce/dce_aux.c
919
*engine = NULL;
sys/dev/drm/amd/display/dc/dce/dce_aux.h
106
void dce110_engine_destroy(struct aux_engine **engine);
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
366
struct dce_i2c_sw *engine,
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
371
engine->speed = speed ? speed : DCE_I2C_DEFAULT_I2C_SW_SPEED;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
373
engine->clock_delay = 1000 / engine->speed;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
375
if (engine->clock_delay < 12)
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
376
engine->clock_delay = 12;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
381
struct dce_i2c_sw *engine,
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
392
engine->ddc = ddc;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
426
struct dce_i2c_sw *engine,
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
429
struct ddc *ddc = engine->ddc;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
430
uint16_t clock_delay_div_4 = engine->clock_delay >> 2;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
434
bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4);
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
442
result = i2c_write_sw(engine->ctx, ddc, clock_delay_div_4,
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
447
result = i2c_read_sw(engine->ctx, ddc, clock_delay_div_4,
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
461
if (!stop_sync_sw(engine->ctx, ddc, clock_delay_div_4))
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
470
struct dce_i2c_sw *engine,
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
489
dce_i2c_sw_engine_submit_channel_request(engine, &request);
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
533
struct dce_i2c_sw *engine = NULL;
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
536
engine = pool->sw_i2cs[line];
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
538
if (!engine)
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
541
if (!dce_i2c_engine_acquire_sw(engine, ddc))
sys/dev/drm/amd/display/dc/dce/dce_i2c_sw.c
544
return engine;
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
1347
enum engine_id engine,
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
1353
if (engine != ENGINE_ID_UNKNOWN) {
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
1358
field |= get_frontend_source(engine);
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
1360
field &= ~get_frontend_source(engine);
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
453
enum engine_id engine)
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.c
455
switch (engine) {
sys/dev/drm/amd/display/dc/dce/dce_link_encoder.h
255
enum engine_id engine,
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
1266
enum engine_id engine,
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
1272
if (engine != ENGINE_ID_UNKNOWN) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
1277
field |= get_frontend_source(engine);
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
1279
field &= ~get_frontend_source(engine);
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
420
enum engine_id engine)
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
422
switch (engine) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
320
enum engine_id engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
120
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
123
engine->funcs->process_channel_reply(engine, &ctx->reply);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
184
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
189
engine->funcs->submit_channel_request(engine, &ctx->request);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
191
operation_result = engine->funcs->get_channel_status(
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
192
engine, &ctx->returned_byte);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
207
process_read_reply(engine, ctx);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
246
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
289
process_read_request(engine, &ctx);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
295
msleep(engine->delay);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
335
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
338
engine->funcs->process_channel_reply(engine, &ctx->reply);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
404
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
409
engine->funcs->submit_channel_request(engine, &ctx->request);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
411
operation_result = engine->funcs->get_channel_status(
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
412
engine, &ctx->returned_byte);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
422
process_write_reply(engine, ctx);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
460
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
498
(engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
499
engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
505
process_write_request(engine, &ctx);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
511
msleep(engine->delay);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
526
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
553
return read_command(engine, &dummy_request, false);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
555
return write_command(engine, &dummy_request, false);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
561
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
565
struct aux_engine *aux_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
594
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
597
dal_i2caux_construct_engine(&engine->base, ctx);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
598
engine->delay = 0;
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
599
engine->max_defer_write_retry = 0;
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
60
engine->base.ctx->logger
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
603
struct aux_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
605
dal_i2caux_destruct_engine(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
63
const struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
69
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
72
struct aux_engine *aux_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.c
93
engine->ddc = ddc;
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
37
struct aux_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
39
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
42
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
45
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
48
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
54
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
57
struct aux_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
61
struct engine base;
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
71
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
75
struct aux_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
77
struct engine *ptr,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
81
struct engine *ptr,
sys/dev/drm/amd/display/dc/i2caux/aux_engine.h
84
const struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
100
struct aux_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
102
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
113
struct aux_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
115
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
189
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
192
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
277
EVENT_LOG_AUX_REQ(engine->base.ddc->pin_data->en, EVENT_LOG_AUX_ORIGIN_NATIVE,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
281
static int read_channel_reply(struct aux_engine *engine, uint32_t size,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
285
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
334
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
341
bytes_replied = read_channel_reply(engine, reply->length, reply->data,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
343
EVENT_LOG_AUX_REP(engine->base.ddc->pin_data->en,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
390
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
393
struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
469
struct aux_engine_dce110 *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
472
dal_aux_engine_construct(&engine->base, aux_init_data->ctx);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
473
engine->base.base.funcs = &engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
474
engine->base.funcs = &aux_engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
476
engine->timeout_period = aux_init_data->timeout_period;
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
477
engine->regs = aux_init_data->regs;
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
481
struct aux_engine_dce110 *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
483
dal_aux_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
489
struct aux_engine_dce110 *engine;
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
496
engine = kzalloc(sizeof(*engine), GFP_KERNEL);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
498
if (!engine) {
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
503
construct(engine, aux_init_data);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
504
return &engine->base;
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
74
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
76
struct aux_engine_dce110 *aux110 = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
82
struct aux_engine_dce110 *engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
87
struct aux_engine_dce110 *engine = FROM_AUX_ENGINE(*aux_engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
89
destruct(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c
91
kfree(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
109
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
111
struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
224
static inline void reset_hw_engine(struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
226
struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
234
static bool is_hw_busy(struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
236
struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
243
reset_hw_engine(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
367
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
372
if (!process_transaction(FROM_I2C_ENGINE(engine), request))
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
375
if (is_hw_busy(&engine->base)) {
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
380
execute_transaction(FROM_I2C_ENGINE(engine));
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
384
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
391
FROM_I2C_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
442
const struct i2c_hw_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
445
FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
449
const struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
452
uint32_t speed = engine->base.funcs->get_speed(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
464
(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c
465
(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
100
return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
74
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
79
struct i2c_sw_engine_dce110 *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
81
dal_i2c_sw_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
85
struct i2c_engine **engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
87
struct i2c_sw_engine_dce110 *sw_engine = FROM_I2C_ENGINE(*engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
93
*engine = NULL;
sys/dev/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c
97
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
102
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
106
engine->base.funcs->acquire(&engine->base, ddc)) {
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
108
return engine;
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
116
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
120
if (engine->funcs->get_engine_type(engine) ==
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
124
dal_i2caux_release_engine(i2caux, engine);
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
85
struct i2c_engine *engine = NULL;
sys/dev/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c
99
engine = i2caux->i2c_hw_engines[line];
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
102
ctx = engine->base.base.base.ctx;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
116
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
118
struct i2c_hw_engine_dce80 *hw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
132
value = dm_read_reg(engine->ctx, mmDC_I2C_ARBITRATION);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
140
dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
147
value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
157
value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
172
dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
181
struct i2c_hw_engine_dce80 *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
183
dal_i2c_hw_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
189
struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(*i2c_engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
191
destruct(engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
193
kfree(engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
202
struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
242
engine->engine_id,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
251
const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
300
const struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
302
const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
317
engine->reference_frequency / pre_scale :
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
318
engine->base.default_speed;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
325
struct i2c_hw_engine_dce80 *engine = FROM_I2C_ENGINE(i2c_engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
328
const uint32_t addr = engine->addr.DC_I2C_DDCX_SPEED;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
334
engine->reference_frequency / speed,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
348
static inline void reset_hw_engine(struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
350
uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_CONTROL);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
364
dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
367
static bool is_hw_busy(struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
371
uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
381
reset_hw_engine(engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
383
value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
405
struct i2c_hw_engine_dce80 *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
416
ctx = engine->base.base.base.ctx;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
420
transaction_addr[engine->transaction_count];
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
436
if ((engine->transaction_count == 3) ||
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
492
if (engine->transaction_count == 0) {
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
531
++engine->transaction_count;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
532
engine->buffer_used_bytes += length + 1;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
538
struct i2c_hw_engine_dce80 *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
543
ctx = engine->base.base.base.ctx;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
546
const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
614
engine->transaction_count - 1,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
638
engine->transaction_count = 0;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
639
engine->buffer_used_bytes = 0;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
643
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
648
if (!process_transaction(FROM_I2C_ENGINE(engine), request))
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
651
if (is_hw_busy(&engine->base)) {
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
656
execute_transaction(FROM_I2C_ENGINE(engine));
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
660
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
687
dm_write_reg(engine->base.ctx, mmDC_I2C_DATA, value);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
695
value = dm_read_reg(engine->base.ctx, mmDC_I2C_DATA);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
707
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
711
uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
737
const struct i2c_hw_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
740
FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
744
const struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
747
uint32_t speed = engine->base.funcs->get_speed(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
759
(FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) +
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
760
(FROM_I2C_HW_ENGINE(engine)->transaction_count << 1);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
828
struct i2c_hw_engine_dce80 *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
831
dal_i2c_hw_engine_construct(&engine->base, arg->ctx);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
833
engine->base.base.base.funcs = &engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
834
engine->base.base.funcs = &i2c_engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
835
engine->base.funcs = &i2c_hw_engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
836
engine->base.default_speed = arg->default_speed;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
837
engine->addr.DC_I2C_DDCX_SETUP =
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
839
engine->addr.DC_I2C_DDCX_SPEED =
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
842
engine->engine_id = arg->engine_id;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
843
engine->reference_frequency = arg->reference_frequency;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
844
engine->buffer_used_bytes = 0;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
845
engine->transaction_count = 0;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
846
engine->engine_keep_power_up_count = 1;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
852
struct i2c_hw_engine_dce80 *engine;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
866
engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
868
if (!engine) {
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
873
construct(engine, arg);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
874
return &engine->base.base;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
95
struct i2c_hw_engine_dce80 *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c
97
const uint32_t addr = engine->addr.DC_I2C_DDCX_SETUP;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
102
struct i2c_engine **engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
104
struct i2c_sw_engine_dce80 *sw_engine = FROM_I2C_ENGINE(*engine);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
110
*engine = NULL;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
114
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
117
return dal_i2caux_i2c_sw_engine_acquire_engine(engine, ddc_handle);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
139
struct i2c_sw_engine_dce80 *engine,
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
147
dal_i2c_sw_engine_construct(&engine->base, &arg_base);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
149
engine->base.base.base.funcs = &engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
150
engine->base.base.funcs = &i2c_engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
151
engine->base.default_speed = arg->default_speed;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
152
engine->engine_id = arg->engine_id;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
158
struct i2c_sw_engine_dce80 *engine;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
165
engine = kzalloc(sizeof(struct i2c_sw_engine_dce80), GFP_KERNEL);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
167
if (!engine) {
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
172
construct(engine, arg);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
173
return &engine->base.base;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
90
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
96
struct i2c_sw_engine_dce80 *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c
98
dal_i2c_sw_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
115
struct i2c_engine *engine = NULL;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
126
engine = i2caux->i2c_hw_engines[line];
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
130
if (!engine) {
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
132
engine = i2caux->i2c_generic_hw_engine;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
135
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
140
engine->base.funcs->acquire(&engine->base, ddc)) {
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
142
return engine;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
145
if (engine->base.funcs->acquire(&engine->base, ddc))
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
146
return engine;
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
154
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
156
if (engine->funcs->get_engine_type(engine) ==
sys/dev/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c
160
dal_i2caux_release_engine(i2caux, engine);
sys/dev/drm/amd/display/dc/i2caux/engine.h
105
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/engine.h
109
struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/engine.h
81
struct engine;
sys/dev/drm/amd/display/dc/i2caux/engine.h
85
const struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/engine.h
87
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/engine.h
90
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/engine.h
94
struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/engine_base.c
40
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/engine_base.c
43
engine->ddc = NULL;
sys/dev/drm/amd/display/dc/i2caux/engine_base.c
44
engine->ctx = ctx;
sys/dev/drm/amd/display/dc/i2caux/engine_base.c
48
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
100
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
107
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
110
dal_i2caux_construct_engine(&engine->base, ctx);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
111
engine->timeout_delay = 0;
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
115
struct i2c_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
117
dal_i2caux_destruct_engine(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
52
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
55
struct i2c_engine *i2c_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
76
engine->funcs->release_engine(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
85
struct i2c_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.c
93
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
101
struct i2c_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
104
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
108
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
112
struct engine *ptr,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
65
const struct i2c_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
67
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
70
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
73
struct i2c_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
75
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
78
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
81
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
86
struct engine base;
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
94
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_engine.h
98
struct i2c_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
257
const struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
260
const struct i2c_engine *base = &engine->base;
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
274
struct i2c_generic_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
277
dal_i2c_hw_engine_construct(&engine->base, ctx);
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
281
struct i2c_generic_hw_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
283
dal_i2c_hw_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
75
const struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
88
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c
92
struct i2c_generic_hw_engine *hw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
41
struct i2c_generic_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
44
struct i2c_generic_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
48
struct i2c_generic_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
53
struct i2c_generic_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
63
struct i2c_generic_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
67
struct i2c_generic_hw_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
69
const struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
71
struct engine *ptr,
sys/dev/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h
75
const struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
184
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
196
engine->base.ddc = ddc;
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
198
current_speed = engine->funcs->get_speed(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
201
FROM_I2C_ENGINE(engine)->original_speed = current_speed;
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
213
struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
224
result = engine->base.funcs->get_channel_status(
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
225
&engine->base, NULL);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
239
struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
242
dal_i2c_engine_construct(&engine->base, ctx);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
243
engine->original_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
244
engine->default_speed = I2CAUX_DEFAULT_I2C_HW_SPEED;
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
248
struct i2c_hw_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
250
dal_i2c_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
67
const struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
73
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.c
77
struct i2c_hw_engine *hw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
37
const struct i2c_hw_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
39
struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
43
const struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
57
struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
61
struct i2c_hw_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
64
struct i2c_hw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
69
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
73
struct engine *ptr,
sys/dev/drm/amd/display/dc/i2caux/i2c_hw_engine.h
78
const struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
362
const struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
368
struct engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
372
struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
441
const struct i2c_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
443
return FROM_I2C_ENGINE(engine)->speed;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
447
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
450
struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
463
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
474
engine->base.ddc = ddc;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
480
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
483
struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
485
struct ddc *ddc = engine->base.ddc;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
490
bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
498
result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
503
result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
517
if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
526
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
534
struct i2c_sw_engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
536
dal_i2c_engine_destruct(&engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
560
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
573
struct i2c_sw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
576
dal_i2c_engine_construct(&engine->base, arg->ctx);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
577
dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
578
engine->base.funcs = &i2c_engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
579
engine->base.base.funcs = &engine_funcs;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
585
struct i2c_sw_engine *engine;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
592
engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
594
if (!engine) {
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
599
dal_i2c_sw_engine_construct(engine, arg);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.c
600
return &engine->base;
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
52
struct i2c_sw_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
56
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
60
struct i2c_sw_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
65
const struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
67
struct engine *ptr,
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
71
const struct i2c_engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2c_sw_engine.h
79
struct i2c_engine *engine,
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
114
struct i2c_engine *engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
135
switch (cmd->engine) {
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
140
engine = i2caux->funcs->acquire_i2c_sw_engine(i2caux, ddc);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
142
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
143
engine = i2caux->funcs->acquire_i2c_hw_engine(
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
150
engine = i2caux->funcs->acquire_i2c_hw_engine(i2caux, ddc);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
152
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
153
engine = i2caux->funcs->acquire_i2c_sw_engine(
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
157
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
160
engine->funcs->set_speed(engine, cmd->speed);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
182
if (!engine->base.funcs->submit_request(
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
183
&engine->base, &request, mot)) {
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
191
i2caux->funcs->release_engine(i2caux, &engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
201
struct aux_engine *engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
216
engine = i2caux->funcs->acquire_aux_engine(i2caux, ddc);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
218
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
221
engine->delay = cmd->defer_delay;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
222
engine->max_defer_write_retry = cmd->max_defer_write_retry;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
255
if (!engine->base.funcs->submit_request(
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
256
&engine->base, &request, mot)) {
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
264
i2caux->funcs->release_engine(i2caux, &engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
300
struct aux_engine *engine =
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
303
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
306
engine->funcs->configure(engine, cfg);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
308
i2caux->funcs->release_engine(i2caux, &engine->base);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
382
struct i2c_engine *engine = NULL;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
385
engine = i2caux->i2c_sw_engines[line];
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
387
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
388
engine = i2caux->i2c_generic_sw_engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
390
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
393
if (!engine->base.funcs->acquire(&engine->base, ddc))
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
396
return engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
404
struct aux_engine *engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
409
engine = i2caux->aux_engines[line];
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
411
if (!engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
414
if (!engine->base.funcs->acquire(&engine->base, ddc))
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
417
return engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
422
struct engine *engine)
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
424
engine->funcs->release_engine(engine);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
426
dal_ddc_close(engine->ddc);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
428
engine->ddc = NULL;
sys/dev/drm/amd/display/dc/i2caux/i2caux.h
106
struct engine *engine);
sys/dev/drm/amd/display/dc/i2caux/i2caux.h
34
struct engine;
sys/dev/drm/amd/display/dc/i2caux/i2caux.h
49
struct engine *engine);
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
146
struct aux_engine *engine);
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
148
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
151
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
154
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
157
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
163
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
165
bool (*is_engine_available)(struct aux_engine *engine);
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
167
const struct aux_engine *engine);
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
169
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
172
struct aux_engine *engine,
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
176
struct aux_engine *engine);
sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h
178
struct aux_engine **engine);
sys/dev/drm/amd/display/dc/inc/hw/link_encoder.h
150
enum engine_id engine,
sys/dev/drm/amd/display/dc/virtual/virtual_link_encoder.c
76
enum engine_id engine,
sys/dev/drm/amd/include/kgd_kfd_interface.h
432
int (*submit_ib)(struct kgd_dev *kgd, enum kgd_engine_type engine,
sys/dev/drm/i915/i915_cmd_parser.c
1001
mask = engine->get_cmd_length_mask(cmd_header);
sys/dev/drm/i915/i915_cmd_parser.c
1030
find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr)
sys/dev/drm/i915/i915_cmd_parser.c
1032
const struct drm_i915_reg_table *table = engine->reg_tables;
sys/dev/drm/i915/i915_cmd_parser.c
1033
int count = engine->reg_table_count;
sys/dev/drm/i915/i915_cmd_parser.c
1128
static bool check_cmd(const struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
1160
find_reg(engine, is_master, reg_addr);
sys/dev/drm/i915/i915_cmd_parser.c
1164
reg_addr, *cmd, engine->name);
sys/dev/drm/i915/i915_cmd_parser.c
1217
*cmd, engine->name);
sys/dev/drm/i915/i915_cmd_parser.c
1229
dword, engine->name);
sys/dev/drm/i915/i915_cmd_parser.c
1255
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
1294
desc = find_cmd(engine, *cmd, desc, &default_desc);
sys/dev/drm/i915/i915_cmd_parser.c
1326
if (!check_cmd(engine, desc, cmd, length, is_master)) {
sys/dev/drm/i915/i915_cmd_parser.c
1354
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_cmd_parser.c
1359
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_cmd_parser.c
1360
if (intel_engine_needs_cmd_parser(engine)) {
sys/dev/drm/i915/i915_cmd_parser.c
711
static bool validate_cmds_sorted(const struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
734
engine->name, engine->id,
sys/dev/drm/i915/i915_cmd_parser.c
746
static bool check_sorted(const struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
760
engine->name, engine->id,
sys/dev/drm/i915/i915_cmd_parser.c
771
static bool validate_regs_sorted(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_cmd_parser.c
776
for (i = 0; i < engine->reg_table_count; i++) {
sys/dev/drm/i915/i915_cmd_parser.c
777
table = &engine->reg_tables[i];
sys/dev/drm/i915/i915_cmd_parser.c
778
if (!check_sorted(engine, table->regs, table->num_regs))
sys/dev/drm/i915/i915_cmd_parser.c
813
static int init_hash_table(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
819
hash_init(engine->cmd_hash);
sys/dev/drm/i915/i915_cmd_parser.c
834
hash_add(engine->cmd_hash, &desc_node->node,
sys/dev/drm/i915/i915_cmd_parser.c
842
static void fini_hash_table(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_cmd_parser.c
848
hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
sys/dev/drm/i915/i915_cmd_parser.c
862
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_cmd_parser.c
868
if (!IS_GEN7(engine->i915))
sys/dev/drm/i915/i915_cmd_parser.c
871
switch (engine->id) {
sys/dev/drm/i915/i915_cmd_parser.c
873
if (IS_HASWELL(engine->i915)) {
sys/dev/drm/i915/i915_cmd_parser.c
882
if (IS_HASWELL(engine->i915)) {
sys/dev/drm/i915/i915_cmd_parser.c
883
engine->reg_tables = hsw_render_reg_tables;
sys/dev/drm/i915/i915_cmd_parser.c
884
engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
sys/dev/drm/i915/i915_cmd_parser.c
886
engine->reg_tables = ivb_render_reg_tables;
sys/dev/drm/i915/i915_cmd_parser.c
887
engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
sys/dev/drm/i915/i915_cmd_parser.c
890
engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
sys/dev/drm/i915/i915_cmd_parser.c
895
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
sys/dev/drm/i915/i915_cmd_parser.c
898
if (IS_HASWELL(engine->i915)) {
sys/dev/drm/i915/i915_cmd_parser.c
906
if (IS_HASWELL(engine->i915)) {
sys/dev/drm/i915/i915_cmd_parser.c
907
engine->reg_tables = hsw_blt_reg_tables;
sys/dev/drm/i915/i915_cmd_parser.c
908
engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
sys/dev/drm/i915/i915_cmd_parser.c
910
engine->reg_tables = ivb_blt_reg_tables;
sys/dev/drm/i915/i915_cmd_parser.c
911
engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
sys/dev/drm/i915/i915_cmd_parser.c
914
engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
sys/dev/drm/i915/i915_cmd_parser.c
920
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
sys/dev/drm/i915/i915_cmd_parser.c
923
MISSING_CASE(engine->id);
sys/dev/drm/i915/i915_cmd_parser.c
927
if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) {
sys/dev/drm/i915/i915_cmd_parser.c
929
engine->name);
sys/dev/drm/i915/i915_cmd_parser.c
932
if (!validate_regs_sorted(engine)) {
sys/dev/drm/i915/i915_cmd_parser.c
933
DRM_ERROR("%s: registers are not sorted\n", engine->name);
sys/dev/drm/i915/i915_cmd_parser.c
937
ret = init_hash_table(engine, cmd_tables, cmd_table_count);
sys/dev/drm/i915/i915_cmd_parser.c
939
DRM_ERROR("%s: initialised failed!\n", engine->name);
sys/dev/drm/i915/i915_cmd_parser.c
940
fini_hash_table(engine);
sys/dev/drm/i915/i915_cmd_parser.c
944
engine->flags |= I915_ENGINE_NEEDS_CMD_PARSER;
sys/dev/drm/i915/i915_cmd_parser.c
954
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_cmd_parser.c
956
if (!intel_engine_needs_cmd_parser(engine))
sys/dev/drm/i915/i915_cmd_parser.c
959
fini_hash_table(engine);
sys/dev/drm/i915/i915_cmd_parser.c
963
find_cmd_in_table(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
968
hash_for_each_possible(engine->cmd_hash, desc_node, node,
sys/dev/drm/i915/i915_cmd_parser.c
987
find_cmd(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_cmd_parser.c
997
desc = find_cmd_in_table(engine, cmd_header);
sys/dev/drm/i915/i915_drv.c
2403
struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_drv.c
2405
return intel_gpu_reset(dev_priv, intel_engine_flag(engine));
sys/dev/drm/i915/i915_drv.c
2421
int i915_reset_engine(struct intel_engine_cs *engine, const char *msg)
sys/dev/drm/i915/i915_drv.c
2423
struct i915_gpu_error *error = &engine->i915->gpu_error;
sys/dev/drm/i915/i915_drv.c
2427
GEM_TRACE("%s flags=%lx\n", engine->name, error->flags);
sys/dev/drm/i915/i915_drv.c
2428
GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &error->flags));
sys/dev/drm/i915/i915_drv.c
2430
active_request = i915_gem_reset_prepare_engine(engine);
sys/dev/drm/i915/i915_drv.c
2438
dev_notice(engine->i915->drm.dev,
sys/dev/drm/i915/i915_drv.c
2439
"Resetting %s for %s\n", engine->name, msg);
sys/dev/drm/i915/i915_drv.c
2440
error->reset_engine_count[engine->id]++;
sys/dev/drm/i915/i915_drv.c
2442
if (!engine->i915->guc.execbuf_client)
sys/dev/drm/i915/i915_drv.c
2443
ret = intel_gt_reset_engine(engine->i915, engine);
sys/dev/drm/i915/i915_drv.c
2445
ret = intel_guc_reset_engine(&engine->i915->guc, engine);
sys/dev/drm/i915/i915_drv.c
2449
engine->i915->guc.execbuf_client ? "GuC " : "",
sys/dev/drm/i915/i915_drv.c
2450
engine->name, ret);
sys/dev/drm/i915/i915_drv.c
2459
i915_gem_reset_engine(engine, active_request, true);
sys/dev/drm/i915/i915_drv.c
2466
ret = engine->init_hw(engine);
sys/dev/drm/i915/i915_drv.c
2471
intel_engine_cancel_stop_cs(engine);
sys/dev/drm/i915/i915_drv.c
2472
i915_gem_reset_finish_engine(engine);
sys/dev/drm/i915/i915_drv.c
343
value = !!dev_priv->engine[VCS];
sys/dev/drm/i915/i915_drv.c
346
value = !!dev_priv->engine[BCS];
sys/dev/drm/i915/i915_drv.c
349
value = !!dev_priv->engine[VECS];
sys/dev/drm/i915/i915_drv.c
352
value = !!dev_priv->engine[VCS2];
sys/dev/drm/i915/i915_drv.c
888
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_drv.c
891
for_each_engine(engine, i915, id)
sys/dev/drm/i915/i915_drv.c
892
kfree(engine);
sys/dev/drm/i915/i915_drv.h
1662
struct intel_engine_cs *engine[I915_NUM_ENGINES];
sys/dev/drm/i915/i915_drv.h
2113
void (*cleanup_engine)(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
2221
for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
sys/dev/drm/i915/i915_drv.h
2227
((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
sys/dev/drm/i915/i915_drv.h
2780
extern int i915_reset_engine(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_drv.h
2786
struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
2787
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
3175
i915_gem_find_active_request(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
3203
struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_drv.h
3205
return READ_ONCE(error->reset_engine_count[engine->id]);
sys/dev/drm/i915/i915_drv.h
3209
i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
3213
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
3217
void i915_gem_reset_engine(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_drv.h
3314
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_drv.h
3410
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
3411
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_drv.h
3412
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_drv.h
3768
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/i915_drv.h
3807
if (engine->irq_seqno_barrier &&
sys/dev/drm/i915/i915_drv.h
3808
test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
sys/dev/drm/i915/i915_drv.h
3809
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/i915_drv.h
3823
engine->irq_seqno_barrier(engine);
sys/dev/drm/i915/i915_gem.c
3401
i915_gem_find_active_request(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem.c
3417
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3418
list_for_each_entry(request, &engine->timeline.requests, link) {
sys/dev/drm/i915/i915_gem.c
3425
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3435
i915_gem_reset_prepare_engine(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem.c
3446
intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
sys/dev/drm/i915/i915_gem.c
3448
request = engine->reset.prepare(engine);
sys/dev/drm/i915/i915_gem.c
3457
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
3462
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_gem.c
3463
request = i915_gem_reset_prepare_engine(engine);
sys/dev/drm/i915/i915_gem.c
3469
engine->hangcheck.active_request = request;
sys/dev/drm/i915/i915_gem.c
3480
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/i915_gem.c
3485
GEM_BUG_ON(timeline == &engine->timeline);
sys/dev/drm/i915/i915_gem.c
3487
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3490
list_for_each_entry_continue(request, &engine->timeline.requests, link)
sys/dev/drm/i915/i915_gem.c
3498
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3503
i915_gem_reset_request(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gem.c
3530
engine->name, request->global_seqno,
sys/dev/drm/i915/i915_gem.c
3532
intel_engine_get_seqno(engine));
sys/dev/drm/i915/i915_gem.c
3549
request = i915_gem_find_active_request(engine);
sys/dev/drm/i915/i915_gem.c
3557
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3559
if (&request->link == &engine->timeline.requests)
sys/dev/drm/i915/i915_gem.c
3561
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3568
void i915_gem_reset_engine(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gem.c
3577
smp_store_mb(engine->irq_posted, 0);
sys/dev/drm/i915/i915_gem.c
3580
request = i915_gem_reset_request(engine, request, stalled);
sys/dev/drm/i915/i915_gem.c
3583
engine->reset.reset(engine, request);
sys/dev/drm/i915/i915_gem.c
3589
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
3596
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_gem.c
3599
i915_gem_reset_engine(engine,
sys/dev/drm/i915/i915_gem.c
3600
engine->hangcheck.active_request,
sys/dev/drm/i915/i915_gem.c
3602
ce = fetch_and_zero(&engine->last_retired_context);
sys/dev/drm/i915/i915_gem.c
3616
if (intel_engine_is_idle(engine)) {
sys/dev/drm/i915/i915_gem.c
3619
rq = i915_request_alloc(engine,
sys/dev/drm/i915/i915_gem.c
3629
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem.c
3631
engine->reset.finish(engine);
sys/dev/drm/i915/i915_gem.c
3633
intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
sys/dev/drm/i915/i915_gem.c
3638
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
3643
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_gem.c
3644
engine->hangcheck.active_request = NULL;
sys/dev/drm/i915/i915_gem.c
3645
i915_gem_reset_finish_engine(engine);
sys/dev/drm/i915/i915_gem.c
3652
request->engine->name,
sys/dev/drm/i915/i915_gem.c
3664
request->engine->name,
sys/dev/drm/i915/i915_gem.c
3668
spin_lock_irqsave(&request->engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3670
intel_engine_init_global_seqno(request->engine, request->global_seqno);
sys/dev/drm/i915/i915_gem.c
3671
spin_unlock_irqrestore(&request->engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3676
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
3684
for_each_engine(engine, i915, id)
sys/dev/drm/i915/i915_gem.c
3685
intel_engine_dump(engine, &p, "%s\n", engine->name);
sys/dev/drm/i915/i915_gem.c
3696
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
3697
i915_gem_reset_prepare_engine(engine);
sys/dev/drm/i915/i915_gem.c
3699
engine->submit_request = nop_submit_request;
sys/dev/drm/i915/i915_gem.c
3700
engine->schedule = NULL;
sys/dev/drm/i915/i915_gem.c
3715
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
3717
engine->cancel_requests(engine);
sys/dev/drm/i915/i915_gem.c
3723
engine->submit_request = nop_complete_submit_request;
sys/dev/drm/i915/i915_gem.c
3733
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
3741
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3742
intel_engine_init_global_seqno(engine,
sys/dev/drm/i915/i915_gem.c
3743
intel_engine_last_submit(engine));
sys/dev/drm/i915/i915_gem.c
3744
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_gem.c
3746
i915_gem_reset_finish_engine(engine);
sys/dev/drm/i915/i915_gem.c
3916
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
3923
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
3924
GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline.last_request));
sys/dev/drm/i915/i915_gem.c
3925
GEM_BUG_ON(engine->last_retired_context !=
sys/dev/drm/i915/i915_gem.c
3926
to_intel_context(i915->kernel_context, engine));
sys/dev/drm/i915/i915_gem.c
4232
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
4235
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
4236
struct i915_timeline *tl = &engine->timeline;
sys/dev/drm/i915/i915_gem.c
4941
return flag(rq->engine->uabi_id);
sys/dev/drm/i915/i915_gem.c
5671
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
5675
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
5676
err = engine->init_hw(engine);
sys/dev/drm/i915/i915_gem.c
5679
engine->name, err);
sys/dev/drm/i915/i915_gem.c
5774
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
5791
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
5794
rq = i915_request_alloc(engine, ctx);
sys/dev/drm/i915/i915_gem.c
5801
if (engine->init_context)
sys/dev/drm/i915/i915_gem.c
5802
err = engine->init_context(rq);
sys/dev/drm/i915/i915_gem.c
5830
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
5834
GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count);
sys/dev/drm/i915/i915_gem.c
5836
state = to_intel_context(ctx, engine)->state;
sys/dev/drm/i915/i915_gem.c
5856
engine->default_state = i915_gem_object_get(state->obj);
sys/dev/drm/i915/i915_gem.c
5859
vaddr = i915_gem_object_pin_map(engine->default_state,
sys/dev/drm/i915/i915_gem.c
5866
i915_gem_object_unpin_map(engine->default_state);
sys/dev/drm/i915/i915_gem.c
5876
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem.c
5877
unsigned int bit = BIT(engine->uabi_class);
sys/dev/drm/i915/i915_gem.c
5878
unsigned int expected = engine->default_state ? bit : 0;
sys/dev/drm/i915/i915_gem.c
5882
engine->uabi_class, engine->name);
sys/dev/drm/i915/i915_gem.c
603
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
609
engine = rq->engine;
sys/dev/drm/i915/i915_gem.c
613
if (engine->schedule)
sys/dev/drm/i915/i915_gem.c
614
engine->schedule(rq, attr);
sys/dev/drm/i915/i915_gem.c
6169
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem.c
6172
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/i915_gem.c
6173
dev_priv->gt.cleanup_engine(engine);
sys/dev/drm/i915/i915_gem_batch_pool.c
108
i915_retire_requests(pool->engine->i915);
sys/dev/drm/i915/i915_gem_batch_pool.c
133
obj = i915_gem_object_create_internal(pool->engine->i915, size);
sys/dev/drm/i915/i915_gem_batch_pool.c
34
struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem_batch_pool.c
38
pool->engine = engine;
sys/dev/drm/i915/i915_gem_batch_pool.c
54
lockdep_assert_held(&pool->engine->i915->drm.struct_mutex);
sys/dev/drm/i915/i915_gem_batch_pool.c
89
lockdep_assert_held(&pool->engine->i915->drm.struct_mutex);
sys/dev/drm/i915/i915_gem_batch_pool.h
15
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_batch_pool.h
20
struct intel_engine_cs *engine);
sys/dev/drm/i915/i915_gem_context.c
584
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_context.c
589
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/i915_gem_context.c
590
intel_engine_lost_context(engine);
sys/dev/drm/i915/i915_gem_context.c
647
struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem_context.c
651
GEM_BUG_ON(timeline == &engine->timeline);
sys/dev/drm/i915/i915_gem_context.c
654
&engine->i915->drm.struct_mutex);
sys/dev/drm/i915/i915_gem_context.c
655
if (rq && rq->engine == engine) {
sys/dev/drm/i915/i915_gem_context.c
657
timeline->name, engine->name,
sys/dev/drm/i915/i915_gem_context.c
666
static bool engine_has_kernel_context_barrier(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem_context.c
668
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/i915_gem_context.c
670
to_intel_context(i915->kernel_context, engine);
sys/dev/drm/i915/i915_gem_context.c
679
rq = last_request_on_engine(ring->timeline, engine);
sys/dev/drm/i915/i915_gem_context.c
716
return engine->last_retired_context == ce;
sys/dev/drm/i915/i915_gem_context.c
721
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_context.c
731
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem_context.c
735
GEM_BUG_ON(!to_intel_context(i915->kernel_context, engine));
sys/dev/drm/i915/i915_gem_context.c
736
if (engine_has_kernel_context_barrier(engine))
sys/dev/drm/i915/i915_gem_context.c
739
GEM_TRACE("emit barrier on %s\n", engine->name);
sys/dev/drm/i915/i915_gem_context.c
741
rq = i915_request_alloc(engine, i915->kernel_context);
sys/dev/drm/i915/i915_gem_context.c
749
prev = last_request_on_engine(ring->timeline, engine);
sys/dev/drm/i915/i915_gem_context.c
757
engine->name,
sys/dev/drm/i915/i915_gem_context.h
297
const struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem_context.h
299
return &ctx->__engine[engine->id];
sys/dev/drm/i915/i915_gem_context.h
303
intel_context_pin(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem_context.h
305
return engine->context_pin(engine, ctx);
sys/dev/drm/i915/i915_gem_evict.c
42
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_evict.c
48
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_gem_evict.c
49
if (!intel_engine_has_kernel_context(engine))
sys/dev/drm/i915/i915_gem_execbuffer.c
1153
obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
sys/dev/drm/i915/i915_gem_execbuffer.c
1179
rq = i915_request_alloc(eb->engine, eb->ctx);
sys/dev/drm/i915/i915_gem_execbuffer.c
1189
err = eb->engine->emit_bb_start(rq,
sys/dev/drm/i915/i915_gem_execbuffer.c
1242
if (!intel_engine_can_store_dword(eb->engine))
sys/dev/drm/i915/i915_gem_execbuffer.c
1913
if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) {
sys/dev/drm/i915/i915_gem_execbuffer.c
1939
shadow_batch_obj = i915_gem_batch_pool_get(&eb->engine->batch_pool,
sys/dev/drm/i915/i915_gem_execbuffer.c
1944
err = intel_engine_cmd_parser(eb->engine,
sys/dev/drm/i915/i915_gem_execbuffer.c
1995
err = eb->engine->emit_bb_start(eb->request,
sys/dev/drm/i915/i915_gem_execbuffer.c
2040
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_execbuffer.c
2069
engine = dev_priv->engine[_VCS(bsd_idx)];
sys/dev/drm/i915/i915_gem_execbuffer.c
2071
engine = dev_priv->engine[user_ring_map[user_ring_id]];
sys/dev/drm/i915/i915_gem_execbuffer.c
2074
if (!engine) {
sys/dev/drm/i915/i915_gem_execbuffer.c
2079
return engine;
sys/dev/drm/i915/i915_gem_execbuffer.c
2260
eb.engine = eb_select_engine(eb.i915, file, args);
sys/dev/drm/i915/i915_gem_execbuffer.c
2261
if (!eb.engine)
sys/dev/drm/i915/i915_gem_execbuffer.c
2384
eb.request = i915_request_alloc(eb.engine, eb.ctx);
sys/dev/drm/i915/i915_gem_execbuffer.c
239
struct intel_engine_cs *engine; /** engine to queue the request to */
sys/dev/drm/i915/i915_gem_execbuffer.c
314
return intel_engine_needs_cmd_parser(eb->engine) && eb->batch_len;
sys/dev/drm/i915/i915_gem_gtt.c
1790
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_gtt.c
1793
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_gem_gtt.c
1796
I915_WRITE(RING_MODE_GEN7(engine),
sys/dev/drm/i915/i915_gem_gtt.c
1803
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_gtt.c
1819
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_gem_gtt.c
1821
I915_WRITE(RING_MODE_GEN7(engine),
sys/dev/drm/i915/i915_gem_gtt.c
2354
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_gem_gtt.c
2358
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_gem_gtt.c
2359
fault = I915_READ(RING_FAULT_REG(engine));
sys/dev/drm/i915/i915_gem_object.h
469
struct intel_engine_cs *engine = NULL;
sys/dev/drm/i915/i915_gem_object.h
477
engine = to_request(fence)->engine;
sys/dev/drm/i915/i915_gem_object.h
480
return engine;
sys/dev/drm/i915/i915_gem_render_state.c
182
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/i915_gem_render_state.c
186
so.rodata = render_state_get_rodata(engine);
sys/dev/drm/i915/i915_gem_render_state.c
193
so.obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
sys/dev/drm/i915/i915_gem_render_state.c
197
so.vma = i915_vma_instance(so.obj, &engine->i915->ggtt.vm, NULL);
sys/dev/drm/i915/i915_gem_render_state.c
211
err = engine->emit_bb_start(rq,
sys/dev/drm/i915/i915_gem_render_state.c
218
err = engine->emit_bb_start(rq,
sys/dev/drm/i915/i915_gem_render_state.c
43
render_state_get_rodata(const struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gem_render_state.c
45
if (engine->id != RCS)
sys/dev/drm/i915/i915_gem_render_state.c
48
switch (INTEL_GEN(engine->i915)) {
sys/dev/drm/i915/i915_gpu_error.c
1032
return request ? request->engine->id : -1;
sys/dev/drm/i915/i915_gpu_error.c
1044
err->engine = __active_get_engine_id(&obj->frontbuffer_write);
sys/dev/drm/i915/i915_gpu_error.c
1102
if (error->engine[i].hangcheck_stalled) {
sys/dev/drm/i915/i915_gpu_error.c
1106
return error->engine[i].ipehr ^
sys/dev/drm/i915/i915_gpu_error.c
1107
error->engine[i].instdone.instdone;
sys/dev/drm/i915/i915_gpu_error.c
1133
static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gpu_error.c
1136
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/i915_gpu_error.c
1138
ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1139
ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1142
I915_READ(RING_SYNC_2(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1145
static void error_record_engine_waiters(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gpu_error.c
1148
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/i915_gpu_error.c
1199
struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gpu_error.c
1202
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/i915_gpu_error.c
1205
ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1209
gen6_record_semaphore_state(engine, ee);
sys/dev/drm/i915/i915_gpu_error.c
1210
ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
sys/dev/drm/i915/i915_gpu_error.c
1215
ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1216
ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1217
ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1218
ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1219
ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1221
ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
sys/dev/drm/i915/i915_gpu_error.c
1222
ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
sys/dev/drm/i915/i915_gpu_error.c
1224
ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1231
intel_engine_get_instdone(engine, &ee->instdone);
sys/dev/drm/i915/i915_gpu_error.c
1233
ee->waiting = intel_engine_has_waiter(engine);
sys/dev/drm/i915/i915_gpu_error.c
1234
ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
sys/dev/drm/i915/i915_gpu_error.c
1235
ee->acthd = intel_engine_get_active_head(engine);
sys/dev/drm/i915/i915_gpu_error.c
1236
ee->seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/i915_gpu_error.c
1237
ee->last_seqno = intel_engine_last_submit(engine);
sys/dev/drm/i915/i915_gpu_error.c
1238
ee->start = I915_READ_START(engine);
sys/dev/drm/i915/i915_gpu_error.c
1239
ee->head = I915_READ_HEAD(engine);
sys/dev/drm/i915/i915_gpu_error.c
1240
ee->tail = I915_READ_TAIL(engine);
sys/dev/drm/i915/i915_gpu_error.c
1241
ee->ctl = I915_READ_CTL(engine);
sys/dev/drm/i915/i915_gpu_error.c
1243
ee->mode = I915_READ_MODE(engine);
sys/dev/drm/i915/i915_gpu_error.c
1249
switch (engine->id) {
sys/dev/drm/i915/i915_gpu_error.c
1264
} else if (IS_GEN6(engine->i915)) {
sys/dev/drm/i915/i915_gpu_error.c
1265
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
sys/dev/drm/i915/i915_gpu_error.c
1268
mmio = RING_HWS_PGA(engine->mmio_base);
sys/dev/drm/i915/i915_gpu_error.c
1274
ee->idle = intel_engine_is_idle(engine);
sys/dev/drm/i915/i915_gpu_error.c
1275
ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
sys/dev/drm/i915/i915_gpu_error.c
1276
ee->hangcheck_action = engine->hangcheck.action;
sys/dev/drm/i915/i915_gpu_error.c
1277
ee->hangcheck_stalled = engine->hangcheck.stalled;
sys/dev/drm/i915/i915_gpu_error.c
1279
engine);
sys/dev/drm/i915/i915_gpu_error.c
1284
ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
sys/dev/drm/i915/i915_gpu_error.c
1288
I915_READ(RING_PP_DIR_BASE_READ(engine));
sys/dev/drm/i915/i915_gpu_error.c
1291
I915_READ(RING_PP_DIR_BASE(engine));
sys/dev/drm/i915/i915_gpu_error.c
1295
I915_READ(GEN8_RING_PDP_UDW(engine, i));
sys/dev/drm/i915/i915_gpu_error.c
1298
I915_READ(GEN8_RING_PDP_LDW(engine, i));
sys/dev/drm/i915/i915_gpu_error.c
1322
static void engine_record_requests(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gpu_error.c
1331
list_for_each_entry_from(request, &engine->timeline.requests, link)
sys/dev/drm/i915/i915_gpu_error.c
1344
list_for_each_entry_from(request, &engine->timeline.requests, link) {
sys/dev/drm/i915/i915_gpu_error.c
1369
static void error_record_engine_execlists(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gpu_error.c
1372
const struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/i915_gpu_error.c
1471
struct intel_engine_cs *engine = i915->engine[i];
sys/dev/drm/i915/i915_gpu_error.c
1472
struct drm_i915_error_engine *ee = &error->engine[i];
sys/dev/drm/i915/i915_gpu_error.c
1477
if (!engine)
sys/dev/drm/i915/i915_gpu_error.c
1482
error_record_engine_registers(error, engine, ee);
sys/dev/drm/i915/i915_gpu_error.c
1483
error_record_engine_waiters(engine, ee);
sys/dev/drm/i915/i915_gpu_error.c
1484
error_record_engine_execlists(engine, ee);
sys/dev/drm/i915/i915_gpu_error.c
1486
request = i915_gem_find_active_request(engine);
sys/dev/drm/i915/i915_gpu_error.c
1525
engine_record_requests(engine, request, ee);
sys/dev/drm/i915/i915_gpu_error.c
1530
engine->status_page.vma);
sys/dev/drm/i915/i915_gpu_error.c
1532
ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
sys/dev/drm/i915/i915_gpu_error.c
1534
ee->default_state = capture_object(i915, engine->default_state);
sys/dev/drm/i915/i915_gpu_error.c
1567
BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
sys/dev/drm/i915/i915_gpu_error.c
1572
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
sys/dev/drm/i915/i915_gpu_error.c
1573
struct drm_i915_error_engine *ee = &error->engine[i];
sys/dev/drm/i915/i915_gpu_error.c
1581
found = error->engine[j].vm == ee->vm;
sys/dev/drm/i915/i915_gpu_error.c
1735
if (engine_id != -1 && error->engine[engine_id].context.pid)
sys/dev/drm/i915/i915_gpu_error.c
1739
error->engine[engine_id].context.comm,
sys/dev/drm/i915/i915_gpu_error.c
1740
error->engine[engine_id].context.pid);
sys/dev/drm/i915/i915_gpu_error.c
1789
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
sys/dev/drm/i915/i915_gpu_error.c
1790
const struct drm_i915_error_engine *ee = &error->engine[i];
sys/dev/drm/i915/i915_gpu_error.c
393
err_puts(m, err->engine != -1 ? " " : "");
sys/dev/drm/i915/i915_gpu_error.c
394
err_puts(m, engine_name(m->i915, err->engine));
sys/dev/drm/i915/i915_gpu_error.c
45
return i915->engine[id];
sys/dev/drm/i915/i915_gpu_error.c
49
__engine_name(const struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_gpu_error.c
51
return engine ? engine->name : "";
sys/dev/drm/i915/i915_gpu_error.c
562
struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_gpu_error.c
576
engine ? engine->name : "global", name,
sys/dev/drm/i915/i915_gpu_error.c
677
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
sys/dev/drm/i915/i915_gpu_error.c
678
if (error->engine[i].hangcheck_stalled &&
sys/dev/drm/i915/i915_gpu_error.c
679
error->engine[i].context.pid) {
sys/dev/drm/i915/i915_gpu_error.c
682
error->engine[i].context.comm,
sys/dev/drm/i915/i915_gpu_error.c
683
error->engine[i].context.pid,
sys/dev/drm/i915/i915_gpu_error.c
684
error->engine[i].context.ban_score,
sys/dev/drm/i915/i915_gpu_error.c
685
bannable(&error->engine[i].context));
sys/dev/drm/i915/i915_gpu_error.c
734
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
sys/dev/drm/i915/i915_gpu_error.c
735
if (error->engine[i].engine_id != -1)
sys/dev/drm/i915/i915_gpu_error.c
736
error_print_engine(m, &error->engine[i], error->epoch);
sys/dev/drm/i915/i915_gpu_error.c
747
for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
sys/dev/drm/i915/i915_gpu_error.c
748
if (error->engine[j].vm != error->active_vm[i])
sys/dev/drm/i915/i915_gpu_error.c
753
dev_priv->engine[j]->name);
sys/dev/drm/i915/i915_gpu_error.c
766
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
sys/dev/drm/i915/i915_gpu_error.c
767
const struct drm_i915_error_engine *ee = &error->engine[i];
sys/dev/drm/i915/i915_gpu_error.c
771
err_puts(m, dev_priv->engine[i]->name);
sys/dev/drm/i915/i915_gpu_error.c
783
print_error_obj(m, dev_priv->engine[i], NULL, obj);
sys/dev/drm/i915/i915_gpu_error.c
787
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
792
dev_priv->engine[i]->name,
sys/dev/drm/i915/i915_gpu_error.c
802
dev_priv->engine[i]->name);
sys/dev/drm/i915/i915_gpu_error.c
805
dev_priv->engine[i]->name,
sys/dev/drm/i915/i915_gpu_error.c
815
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
818
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
821
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
824
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
827
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
830
print_error_obj(m, dev_priv->engine[i],
sys/dev/drm/i915/i915_gpu_error.c
923
for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
sys/dev/drm/i915/i915_gpu_error.c
924
struct drm_i915_error_engine *ee = &error->engine[i];
sys/dev/drm/i915/i915_gpu_error.h
176
} engine[I915_NUM_ENGINES];
sys/dev/drm/i915/i915_gpu_error.h
190
s32 engine:4;
sys/dev/drm/i915/i915_irq.c
1155
static void notify_ring(struct intel_engine_cs *engine)
sys/dev/drm/i915/i915_irq.c
1157
const u32 seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/i915_irq.c
1162
if (unlikely(!engine->breadcrumbs.irq_armed))
sys/dev/drm/i915/i915_irq.c
1167
lockmgr(&engine->breadcrumbs.irq_lock, LK_EXCLUSIVE);
sys/dev/drm/i915/i915_irq.c
1168
wait = engine->breadcrumbs.irq_wait;
sys/dev/drm/i915/i915_irq.c
1193
if (engine->irq_seqno_barrier &&
sys/dev/drm/i915/i915_irq.c
1196
&engine->irq_posted);
sys/dev/drm/i915/i915_irq.c
1201
engine->breadcrumbs.irq_count++;
sys/dev/drm/i915/i915_irq.c
1203
if (engine->breadcrumbs.irq_armed)
sys/dev/drm/i915/i915_irq.c
1204
__intel_engine_disarm_breadcrumbs(engine);
sys/dev/drm/i915/i915_irq.c
1206
lockmgr(&engine->breadcrumbs.irq_lock, LK_RELEASE);
sys/dev/drm/i915/i915_irq.c
1222
trace_intel_engine_notify(engine, wait);
sys/dev/drm/i915/i915_irq.c
1469
notify_ring(dev_priv->engine[RCS]);
sys/dev/drm/i915/i915_irq.c
1471
notify_ring(dev_priv->engine[VCS]);
sys/dev/drm/i915/i915_irq.c
1478
notify_ring(dev_priv->engine[RCS]);
sys/dev/drm/i915/i915_irq.c
1480
notify_ring(dev_priv->engine[VCS]);
sys/dev/drm/i915/i915_irq.c
1482
notify_ring(dev_priv->engine[BCS]);
sys/dev/drm/i915/i915_irq.c
1494
gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
sys/dev/drm/i915/i915_irq.c
1502
notify_ring(engine);
sys/dev/drm/i915/i915_irq.c
1503
tasklet |= USES_GUC_SUBMISSION(engine->i915);
sys/dev/drm/i915/i915_irq.c
1507
tasklet_hi_schedule(&engine->execlists.tasklet);
sys/dev/drm/i915/i915_irq.c
1552
gen8_cs_irq_handler(i915->engine[RCS],
sys/dev/drm/i915/i915_irq.c
1554
gen8_cs_irq_handler(i915->engine[BCS],
sys/dev/drm/i915/i915_irq.c
1559
gen8_cs_irq_handler(i915->engine[VCS],
sys/dev/drm/i915/i915_irq.c
1561
gen8_cs_irq_handler(i915->engine[VCS2],
sys/dev/drm/i915/i915_irq.c
1566
gen8_cs_irq_handler(i915->engine[VECS],
sys/dev/drm/i915/i915_irq.c
1848
notify_ring(dev_priv->engine[VECS]);
sys/dev/drm/i915/i915_irq.c
3017
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_irq.c
3020
engine = i915->engine_class[class][instance];
sys/dev/drm/i915/i915_irq.c
3022
engine = NULL;
sys/dev/drm/i915/i915_irq.c
3024
if (likely(engine))
sys/dev/drm/i915/i915_irq.c
3025
return gen8_cs_irq_handler(engine, iir);
sys/dev/drm/i915/i915_irq.c
3243
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_irq.c
3246
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_irq.c
3247
I915_WRITE(RING_FAULT_REG(engine),
sys/dev/drm/i915/i915_irq.c
3248
I915_READ(RING_FAULT_REG(engine)) &
sys/dev/drm/i915/i915_irq.c
3251
POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
sys/dev/drm/i915/i915_irq.c
3273
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_irq.c
3310
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
sys/dev/drm/i915/i915_irq.c
3312
if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
sys/dev/drm/i915/i915_irq.c
3316
if (i915_reset_engine(engine, msg) == 0)
sys/dev/drm/i915/i915_irq.c
3317
engine_mask &= ~intel_engine_flag(engine);
sys/dev/drm/i915/i915_irq.c
3319
clear_bit(I915_RESET_ENGINE + engine->id,
sys/dev/drm/i915/i915_irq.c
3322
I915_RESET_ENGINE + engine->id);
sys/dev/drm/i915/i915_irq.c
3338
for_each_engine(engine, dev_priv, tmp) {
sys/dev/drm/i915/i915_irq.c
3339
while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
sys/dev/drm/i915/i915_irq.c
3342
I915_RESET_ENGINE + engine->id,
sys/dev/drm/i915/i915_irq.c
3348
for_each_engine(engine, dev_priv, tmp) {
sys/dev/drm/i915/i915_irq.c
3349
clear_bit(I915_RESET_ENGINE + engine->id,
sys/dev/drm/i915/i915_irq.c
4489
notify_ring(dev_priv->engine[RCS]);
sys/dev/drm/i915/i915_irq.c
4599
notify_ring(dev_priv->engine[RCS]);
sys/dev/drm/i915/i915_irq.c
4746
notify_ring(dev_priv->engine[RCS]);
sys/dev/drm/i915/i915_irq.c
4749
notify_ring(dev_priv->engine[VCS]);
sys/dev/drm/i915/i915_perf.c
1208
struct intel_engine_cs *engine = i915->engine[RCS];
sys/dev/drm/i915/i915_perf.c
1222
ce = intel_context_pin(ctx, engine);
sys/dev/drm/i915/i915_perf.c
1712
struct intel_engine_cs *engine = dev_priv->engine[RCS];
sys/dev/drm/i915/i915_perf.c
1741
struct intel_context *ce = to_intel_context(ctx, engine);
sys/dev/drm/i915/i915_perf.c
1764
rq = i915_request_alloc(engine, dev_priv->kernel_context);
sys/dev/drm/i915/i915_perf.c
2134
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_perf.c
2141
if (engine->id != RCS)
sys/dev/drm/i915/i915_perf.c
2144
stream = engine->i915->perf.oa.exclusive_stream;
sys/dev/drm/i915/i915_pmu.c
104
else if (intel_engine_supports_stats(i915->engine[RCS]))
sys/dev/drm/i915/i915_pmu.c
168
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
181
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/i915_pmu.c
182
u32 current_seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/i915_pmu.c
183
u32 last_seqno = intel_engine_last_submit(engine);
sys/dev/drm/i915/i915_pmu.c
189
add_sample(&engine->pmu.sample[I915_SAMPLE_BUSY],
sys/dev/drm/i915/i915_pmu.c
192
if (val && (engine->pmu.enable &
sys/dev/drm/i915/i915_pmu.c
196
val = I915_READ_FW(RING_CTL(engine->mmio_base));
sys/dev/drm/i915/i915_pmu.c
202
add_sample(&engine->pmu.sample[I915_SAMPLE_WAIT],
sys/dev/drm/i915/i915_pmu.c
206
add_sample(&engine->pmu.sample[I915_SAMPLE_SEMA],
sys/dev/drm/i915/i915_pmu.c
299
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
301
engine = intel_engine_lookup_user(i915,
sys/dev/drm/i915/i915_pmu.c
304
if (WARN_ON_ONCE(!engine))
sys/dev/drm/i915/i915_pmu.c
308
intel_engine_supports_stats(engine))
sys/dev/drm/i915/i915_pmu.c
309
intel_disable_engine_stats(engine);
sys/dev/drm/i915/i915_pmu.c
321
engine_event_status(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_pmu.c
329
if (INTEL_GEN(engine->i915) < 6)
sys/dev/drm/i915/i915_pmu.c
369
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
373
engine = intel_engine_lookup_user(i915, engine_event_class(event),
sys/dev/drm/i915/i915_pmu.c
375
if (!engine)
sys/dev/drm/i915/i915_pmu.c
379
ret = engine_event_status(engine, sample);
sys/dev/drm/i915/i915_pmu.c
383
if (sample == I915_SAMPLE_BUSY && intel_engine_supports_stats(engine))
sys/dev/drm/i915/i915_pmu.c
384
ret = intel_enable_engine_stats(engine);
sys/dev/drm/i915/i915_pmu.c
531
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
533
engine = intel_engine_lookup_user(i915,
sys/dev/drm/i915/i915_pmu.c
537
if (WARN_ON_ONCE(!engine)) {
sys/dev/drm/i915/i915_pmu.c
540
intel_engine_supports_stats(engine)) {
sys/dev/drm/i915/i915_pmu.c
541
val = ktime_to_ns(intel_engine_get_busy_time(engine));
sys/dev/drm/i915/i915_pmu.c
543
val = engine->pmu.sample[sample].cur;
sys/dev/drm/i915/i915_pmu.c
613
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
615
engine = intel_engine_lookup_user(i915,
sys/dev/drm/i915/i915_pmu.c
618
GEM_BUG_ON(!engine);
sys/dev/drm/i915/i915_pmu.c
619
engine->pmu.enable |= BIT(sample);
sys/dev/drm/i915/i915_pmu.c
622
GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
sys/dev/drm/i915/i915_pmu.c
623
engine->pmu.enable_count[sample]++;
sys/dev/drm/i915/i915_pmu.c
647
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
649
engine = intel_engine_lookup_user(i915,
sys/dev/drm/i915/i915_pmu.c
652
GEM_BUG_ON(!engine);
sys/dev/drm/i915/i915_pmu.c
654
GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
sys/dev/drm/i915/i915_pmu.c
659
if (--engine->pmu.enable_count[sample] == 0)
sys/dev/drm/i915/i915_pmu.c
660
engine->pmu.enable &= ~BIT(sample);
sys/dev/drm/i915/i915_pmu.c
847
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_pmu.c
857
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_pmu.c
859
if (!engine_event_status(engine,
sys/dev/drm/i915/i915_pmu.c
908
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_pmu.c
912
if (engine_event_status(engine,
sys/dev/drm/i915/i915_pmu.c
917
engine->name, engine_events[i].name);
sys/dev/drm/i915/i915_pmu.c
924
__I915_PMU_ENGINE(engine->uabi_class,
sys/dev/drm/i915/i915_pmu.c
925
engine->instance,
sys/dev/drm/i915/i915_pmu.c
929
engine->name, engine_events[i].name);
sys/dev/drm/i915/i915_reg.h
2373
#define RING_FAULT_REG(engine) _MMIO(0x4094 + 0x100 * (engine)->hw_id)
sys/dev/drm/i915/i915_reg.h
2595
#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
sys/dev/drm/i915/i915_reg.h
334
#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228)
sys/dev/drm/i915/i915_reg.h
335
#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518)
sys/dev/drm/i915/i915_reg.h
336
#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220)
sys/dev/drm/i915/i915_reg.h
339
#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
sys/dev/drm/i915/i915_reg.h
340
#define GEN8_RING_PDP_LDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8)
sys/dev/drm/i915/i915_request.c
1047
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/i915_request.c
1054
engine->name, request->fence.context, request->fence.seqno);
sys/dev/drm/i915/i915_request.c
1072
engine->emit_flush(request, EMIT_FLUSH);
sys/dev/drm/i915/i915_request.c
1080
cs = intel_ring_begin(request, engine->emit_breadcrumb_sz);
sys/dev/drm/i915/i915_request.c
1096
if (engine->schedule)
sys/dev/drm/i915/i915_request.c
1130
if (engine->schedule)
sys/dev/drm/i915/i915_request.c
1131
engine->schedule(request, &request->gem_context->sched);
sys/dev/drm/i915/i915_request.c
1193
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/i915_request.c
1209
if (!intel_engine_has_started(engine, seqno))
sys/dev/drm/i915/i915_request.c
1223
irq = READ_ONCE(engine->breadcrumbs.irq_count);
sys/dev/drm/i915/i915_request.c
1226
if (intel_engine_has_completed(engine, seqno))
sys/dev/drm/i915/i915_request.c
1235
if (READ_ONCE(engine->breadcrumbs.irq_count) != irq)
sys/dev/drm/i915/i915_request.c
1345
if (intel_engine_add_wait(rq->engine, &wait))
sys/dev/drm/i915/i915_request.c
1405
intel_engine_remove_wait(rq->engine, &wait);
sys/dev/drm/i915/i915_request.c
1410
intel_engine_remove_wait(rq->engine, &wait);
sys/dev/drm/i915/i915_request.c
201
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_request.c
217
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/i915_request.c
219
engine->name,
sys/dev/drm/i915/i915_request.c
220
engine->timeline.seqno,
sys/dev/drm/i915/i915_request.c
221
intel_engine_get_seqno(engine),
sys/dev/drm/i915/i915_request.c
224
if (!i915_seqno_passed(seqno, engine->timeline.seqno)) {
sys/dev/drm/i915/i915_request.c
226
intel_engine_disarm_breadcrumbs(engine);
sys/dev/drm/i915/i915_request.c
227
intel_engine_init_hangcheck(engine);
sys/dev/drm/i915/i915_request.c
228
GEM_BUG_ON(!list_empty(&engine->breadcrumbs.signals));
sys/dev/drm/i915/i915_request.c
232
GEM_BUG_ON(!intel_engine_is_idle(engine));
sys/dev/drm/i915/i915_request.c
233
GEM_BUG_ON(i915_gem_active_isset(&engine->timeline.last_request));
sys/dev/drm/i915/i915_request.c
236
intel_engine_init_global_seqno(engine, seqno);
sys/dev/drm/i915/i915_request.c
237
engine->timeline.seqno = seqno;
sys/dev/drm/i915/i915_request.c
348
static void __retire_engine_request(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_request.c
352
__func__, engine->name,
sys/dev/drm/i915/i915_request.c
355
intel_engine_get_seqno(engine));
sys/dev/drm/i915/i915_request.c
361
lockmgr(&engine->timeline.lock, LK_EXCLUSIVE);
sys/dev/drm/i915/i915_request.c
362
GEM_BUG_ON(!list_is_first(&rq->link, &engine->timeline.requests));
sys/dev/drm/i915/i915_request.c
364
lockmgr(&engine->timeline.lock, LK_RELEASE);
sys/dev/drm/i915/i915_request.c
387
if (engine->last_retired_context)
sys/dev/drm/i915/i915_request.c
388
intel_context_unpin(engine->last_retired_context);
sys/dev/drm/i915/i915_request.c
389
engine->last_retired_context = rq->hw_context;
sys/dev/drm/i915/i915_request.c
392
static void __retire_engine_upto(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_request.c
401
tmp = list_first_entry(&engine->timeline.requests,
sys/dev/drm/i915/i915_request.c
404
GEM_BUG_ON(tmp->engine != engine);
sys/dev/drm/i915/i915_request.c
405
__retire_engine_request(engine, tmp);
sys/dev/drm/i915/i915_request.c
414
request->engine->name,
sys/dev/drm/i915/i915_request.c
417
intel_engine_get_seqno(request->engine));
sys/dev/drm/i915/i915_request.c
463
__retire_engine_upto(request->engine, request);
sys/dev/drm/i915/i915_request.c
477
rq->engine->name,
sys/dev/drm/i915/i915_request.c
480
intel_engine_get_seqno(rq->engine));
sys/dev/drm/i915/i915_request.c
504
GEM_BUG_ON(request->timeline == &request->engine->timeline);
sys/dev/drm/i915/i915_request.c
505
lockdep_assert_held(&request->engine->timeline.lock);
sys/dev/drm/i915/i915_request.c
514
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/i915_request.c
518
engine->name,
sys/dev/drm/i915/i915_request.c
520
engine->timeline.seqno + 1,
sys/dev/drm/i915/i915_request.c
521
intel_engine_get_seqno(engine));
sys/dev/drm/i915/i915_request.c
524
lockdep_assert_held(&engine->timeline.lock);
sys/dev/drm/i915/i915_request.c
528
seqno = timeline_get_seqno(&engine->timeline);
sys/dev/drm/i915/i915_request.c
530
GEM_BUG_ON(intel_engine_signaled(engine, seqno));
sys/dev/drm/i915/i915_request.c
539
engine->emit_breadcrumb(request,
sys/dev/drm/i915/i915_request.c
543
move_to_timeline(request, &engine->timeline);
sys/dev/drm/i915/i915_request.c
552
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/i915_request.c
556
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_request.c
560
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_request.c
565
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/i915_request.c
568
engine->name,
sys/dev/drm/i915/i915_request.c
571
intel_engine_get_seqno(engine));
sys/dev/drm/i915/i915_request.c
574
lockdep_assert_held(&engine->timeline.lock);
sys/dev/drm/i915/i915_request.c
581
GEM_BUG_ON(request->global_seqno != engine->timeline.seqno);
sys/dev/drm/i915/i915_request.c
582
GEM_BUG_ON(intel_engine_has_completed(engine, request->global_seqno));
sys/dev/drm/i915/i915_request.c
583
engine->timeline.seqno--;
sys/dev/drm/i915/i915_request.c
606
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/i915_request.c
610
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_request.c
614
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/i915_request.c
635
request->engine->submit_request(request);
sys/dev/drm/i915/i915_request.c
657
i915_request_alloc(struct intel_engine_cs *engine, struct i915_gem_context *ctx)
sys/dev/drm/i915/i915_request.c
659
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/i915_request.c
685
ce = intel_context_pin(ctx, engine);
sys/dev/drm/i915/i915_request.c
765
rq->engine = engine;
sys/dev/drm/i915/i915_request.c
770
GEM_BUG_ON(rq->timeline == &engine->timeline);
sys/dev/drm/i915/i915_request.c
801
GEM_BUG_ON(rq->reserved_space < engine->emit_breadcrumb_sz);
sys/dev/drm/i915/i915_request.c
812
ret = engine->emit_flush(rq, EMIT_INVALIDATE);
sys/dev/drm/i915/i915_request.c
816
ret = engine->request_alloc(rq);
sys/dev/drm/i915/i915_request.c
856
if (to->engine->schedule) {
sys/dev/drm/i915/i915_request.c
864
if (to->engine == from->engine) {
sys/dev/drm/i915/i915_request.c
871
if (to->engine->semaphore.sync_to) {
sys/dev/drm/i915/i915_request.c
874
GEM_BUG_ON(!from->engine->semaphore.signal);
sys/dev/drm/i915/i915_request.c
880
if (seqno <= to->timeline->global_sync[from->engine->id])
sys/dev/drm/i915/i915_request.c
884
ret = to->engine->semaphore.sync_to(to, from);
sys/dev/drm/i915/i915_request.c
888
to->timeline->global_sync[from->engine->id] = seqno;
sys/dev/drm/i915/i915_request.h
204
i915_request_alloc(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_request.h
284
static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_request.h
286
static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
sys/dev/drm/i915/i915_request.h
314
return intel_engine_has_started(rq->engine, seqno);
sys/dev/drm/i915/i915_request.h
321
return intel_engine_has_completed(rq->engine, seqno) &&
sys/dev/drm/i915/i915_request.h
98
struct intel_engine_cs *engine;
sys/dev/drm/i915/i915_trace.h
87
#define trace_intel_engine_notify(engine, waiters)
sys/dev/drm/i915/intel_breadcrumbs.c
100
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
125
if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP) {
sys/dev/drm/i915/intel_breadcrumbs.c
126
missed_breadcrumb(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
135
struct intel_engine_cs *engine =
sys/dev/drm/i915/intel_breadcrumbs.c
136
from_timer(engine, t, breadcrumbs.fake_irq);
sys/dev/drm/i915/intel_breadcrumbs.c
137
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
149
__intel_engine_disarm_breadcrumbs(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
155
if (!test_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings)) {
sys/dev/drm/i915/intel_breadcrumbs.c
163
static void irq_enable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
171
GEM_BUG_ON(!intel_irqs_enabled(engine->i915));
sys/dev/drm/i915/intel_breadcrumbs.c
177
set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
sys/dev/drm/i915/intel_breadcrumbs.c
180
if (engine->irq_enable) {
sys/dev/drm/i915/intel_breadcrumbs.c
181
lockmgr(&engine->i915->irq_lock, LK_EXCLUSIVE);
sys/dev/drm/i915/intel_breadcrumbs.c
182
engine->irq_enable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
183
lockmgr(&engine->i915->irq_lock, LK_RELEASE);
sys/dev/drm/i915/intel_breadcrumbs.c
187
static void irq_disable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
190
if (engine->irq_disable) {
sys/dev/drm/i915/intel_breadcrumbs.c
191
lockmgr(&engine->i915->irq_lock, LK_EXCLUSIVE);
sys/dev/drm/i915/intel_breadcrumbs.c
192
engine->irq_disable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
193
lockmgr(&engine->i915->irq_lock, LK_RELEASE);
sys/dev/drm/i915/intel_breadcrumbs.c
199
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
201
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
209
irq_disable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
214
void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
216
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
220
irq_enable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
225
void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
227
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
232
irq_disable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
236
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
238
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
249
if (intel_engine_wakeup(engine) & ENGINE_WAKEUP_ASLEEP)
sys/dev/drm/i915/intel_breadcrumbs.c
250
missed_breadcrumb(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
257
__intel_engine_disarm_breadcrumbs(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
261
GEM_BUG_ON(!intel_engine_signaled(engine, wait->seqno));
sys/dev/drm/i915/intel_breadcrumbs.c
272
const struct intel_engine_cs *engine =
sys/dev/drm/i915/intel_breadcrumbs.c
275
if (!test_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings))
sys/dev/drm/i915/intel_breadcrumbs.c
299
struct intel_engine_cs *engine =
sys/dev/drm/i915/intel_breadcrumbs.c
301
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_breadcrumbs.c
336
!test_bit(engine->id, &i915->gpu_error.test_irq_rings)) {
sys/dev/drm/i915/intel_breadcrumbs.c
337
irq_enable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
372
static inline void __intel_breadcrumbs_next(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_breadcrumbs.c
375
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
391
static bool __intel_engine_add_wait(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_breadcrumbs.c
394
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
417
seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
482
__intel_breadcrumbs_next(engine, next);
sys/dev/drm/i915/intel_breadcrumbs.c
499
bool intel_engine_add_wait(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_breadcrumbs.c
502
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
506
armed = __intel_engine_add_wait(engine, wait);
sys/dev/drm/i915/intel_breadcrumbs.c
512
return intel_engine_has_started(engine, wait->seqno);
sys/dev/drm/i915/intel_breadcrumbs.c
529
static void __intel_engine_remove_wait(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_breadcrumbs.c
532
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
563
u32 seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
575
__intel_breadcrumbs_next(engine, next);
sys/dev/drm/i915/intel_breadcrumbs.c
590
void intel_engine_remove_wait(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_breadcrumbs.c
593
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
605
__intel_engine_remove_wait(engine, wait);
sys/dev/drm/i915/intel_breadcrumbs.c
618
struct intel_engine_cs *engine = arg;
sys/dev/drm/i915/intel_breadcrumbs.c
619
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
643
seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
65
unsigned int intel_engine_wakeup(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
655
__intel_engine_remove_wait(engine,
sys/dev/drm/i915/intel_breadcrumbs.c
67
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
695
engine->irq_seqno_barrier &&
sys/dev/drm/i915/intel_breadcrumbs.c
697
&engine->irq_posted)) {
sys/dev/drm/i915/intel_breadcrumbs.c
698
engine->irq_seqno_barrier(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
699
intel_engine_wakeup(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
745
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/intel_breadcrumbs.c
746
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
782
wakeup &= __intel_engine_add_wait(engine, wait);
sys/dev/drm/i915/intel_breadcrumbs.c
795
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/intel_breadcrumbs.c
796
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
805
__intel_engine_remove_wait(engine, &request->signaling.wait);
sys/dev/drm/i915/intel_breadcrumbs.c
811
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
813
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
83
static noinline void missed_breadcrumb(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
830
tsk = kthread_run(intel_breadcrumbs_signaler, engine,
sys/dev/drm/i915/intel_breadcrumbs.c
831
"i915/signal:%d", engine->id);
sys/dev/drm/i915/intel_breadcrumbs.c
840
static void cancel_fake_irq(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
842
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
846
clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
sys/dev/drm/i915/intel_breadcrumbs.c
849
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
851
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
861
clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
sys/dev/drm/i915/intel_breadcrumbs.c
864
irq_enable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
866
irq_disable(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
876
clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
sys/dev/drm/i915/intel_breadcrumbs.c
88
intel_engine_dump(engine, &p,
sys/dev/drm/i915/intel_breadcrumbs.c
881
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_breadcrumbs.c
883
struct intel_breadcrumbs *b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_breadcrumbs.c
893
cancel_fake_irq(engine);
sys/dev/drm/i915/intel_breadcrumbs.c
90
engine->name, __builtin_return_address(0));
sys/dev/drm/i915/intel_breadcrumbs.c
93
set_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
sys/dev/drm/i915/intel_breadcrumbs.c
98
struct intel_engine_cs *engine =
sys/dev/drm/i915/intel_breadcrumbs.c
99
from_timer(engine, t, breadcrumbs.hangcheck);
sys/dev/drm/i915/intel_engine_cs.c
1002
to_intel_context(engine->i915->kernel_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
1005
lockdep_assert_held(&engine->i915->drm.struct_mutex);
sys/dev/drm/i915/intel_engine_cs.c
1012
rq = __i915_gem_active_peek(&engine->timeline.last_request);
sys/dev/drm/i915/intel_engine_cs.c
1016
return engine->last_retired_context == kernel_context;
sys/dev/drm/i915/intel_engine_cs.c
1021
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
1024
for_each_engine(engine, i915, id)
sys/dev/drm/i915/intel_engine_cs.c
1025
engine->set_default_submission(engine);
sys/dev/drm/i915/intel_engine_cs.c
1039
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
1044
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/intel_engine_cs.c
1045
if (engine->reset.reset)
sys/dev/drm/i915/intel_engine_cs.c
1046
engine->reset.reset(engine, NULL);
sys/dev/drm/i915/intel_engine_cs.c
1060
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
1063
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/intel_engine_cs.c
1065
intel_engine_disarm_breadcrumbs(engine);
sys/dev/drm/i915/intel_engine_cs.c
1066
tasklet_kill(&engine->execlists.tasklet);
sys/dev/drm/i915/intel_engine_cs.c
1073
if (wait_for(intel_engine_is_idle(engine), 10)) {
sys/dev/drm/i915/intel_engine_cs.c
1078
engine->name);
sys/dev/drm/i915/intel_engine_cs.c
1080
intel_engine_dump(engine, &p, NULL);
sys/dev/drm/i915/intel_engine_cs.c
1082
intel_engine_dump(engine, &p, "\n");
sys/dev/drm/i915/intel_engine_cs.c
1087
GEM_BUG_ON(engine->execlists.queue_priority != INT_MIN);
sys/dev/drm/i915/intel_engine_cs.c
1089
if (engine->park)
sys/dev/drm/i915/intel_engine_cs.c
1090
engine->park(engine);
sys/dev/drm/i915/intel_engine_cs.c
1092
if (engine->pinned_default_state) {
sys/dev/drm/i915/intel_engine_cs.c
1093
i915_gem_object_unpin_map(engine->default_state);
sys/dev/drm/i915/intel_engine_cs.c
1094
engine->pinned_default_state = NULL;
sys/dev/drm/i915/intel_engine_cs.c
1097
i915_gem_batch_pool_fini(&engine->batch_pool);
sys/dev/drm/i915/intel_engine_cs.c
1098
engine->execlists.no_priolist = false;
sys/dev/drm/i915/intel_engine_cs.c
1110
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
1113
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/intel_engine_cs.c
1118
if (engine->default_state)
sys/dev/drm/i915/intel_engine_cs.c
1119
map = i915_gem_object_pin_map(engine->default_state,
sys/dev/drm/i915/intel_engine_cs.c
1122
engine->pinned_default_state = map;
sys/dev/drm/i915/intel_engine_cs.c
1124
if (engine->unpark)
sys/dev/drm/i915/intel_engine_cs.c
1125
engine->unpark(engine);
sys/dev/drm/i915/intel_engine_cs.c
1127
intel_engine_init_hangcheck(engine);
sys/dev/drm/i915/intel_engine_cs.c
1140
void intel_engine_lost_context(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
1144
lockdep_assert_held(&engine->i915->drm.struct_mutex);
sys/dev/drm/i915/intel_engine_cs.c
1146
ce = fetch_and_zero(&engine->last_retired_context);
sys/dev/drm/i915/intel_engine_cs.c
1151
bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
1153
switch (INTEL_GEN(engine->i915)) {
sys/dev/drm/i915/intel_engine_cs.c
1158
return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
sys/dev/drm/i915/intel_engine_cs.c
1160
return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
sys/dev/drm/i915/intel_engine_cs.c
1168
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
1173
for_each_engine(engine, i915, id)
sys/dev/drm/i915/intel_engine_cs.c
1174
if (engine->default_state)
sys/dev/drm/i915/intel_engine_cs.c
1175
which |= BIT(engine->uabi_class);
sys/dev/drm/i915/intel_engine_cs.c
1280
static void intel_engine_print_registers(const struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_engine_cs.c
1283
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
1285
&engine->execlists;
sys/dev/drm/i915/intel_engine_cs.c
1288
if (engine->id == RCS && IS_GEN(dev_priv, 4, 7))
sys/dev/drm/i915/intel_engine_cs.c
1291
I915_READ(RING_START(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1293
I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR);
sys/dev/drm/i915/intel_engine_cs.c
1295
I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR);
sys/dev/drm/i915/intel_engine_cs.c
1297
I915_READ(RING_CTL(engine->mmio_base)),
sys/dev/drm/i915/intel_engine_cs.c
1298
I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
sys/dev/drm/i915/intel_engine_cs.c
1299
if (INTEL_GEN(engine->i915) > 2) {
sys/dev/drm/i915/intel_engine_cs.c
1301
I915_READ(RING_MI_MODE(engine->mmio_base)),
sys/dev/drm/i915/intel_engine_cs.c
1302
I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : "");
sys/dev/drm/i915/intel_engine_cs.c
1306
drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine));
sys/dev/drm/i915/intel_engine_cs.c
1311
I915_READ(RING_SYNC_0(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1313
I915_READ(RING_SYNC_1(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1316
I915_READ(RING_SYNC_2(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1319
addr = intel_engine_get_active_head(engine);
sys/dev/drm/i915/intel_engine_cs.c
1322
addr = intel_engine_get_last_batch_head(engine);
sys/dev/drm/i915/intel_engine_cs.c
1326
addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base),
sys/dev/drm/i915/intel_engine_cs.c
1327
RING_DMA_FADD_UDW(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
1329
addr = I915_READ(RING_DMA_FADD(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
1336
I915_READ(RING_IPEIR(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1338
I915_READ(RING_IPEHR(engine->mmio_base)));
sys/dev/drm/i915/intel_engine_cs.c
1345
const u32 *hws = &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
sys/dev/drm/i915/intel_engine_cs.c
1350
I915_READ(RING_EXECLIST_STATUS_LO(engine)),
sys/dev/drm/i915/intel_engine_cs.c
1351
I915_READ(RING_EXECLIST_STATUS_HI(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1358
GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine))),
sys/dev/drm/i915/intel_engine_cs.c
1360
&engine->execlists.tasklet.state)),
sys/dev/drm/i915/intel_engine_cs.c
1361
enableddisabled(!atomic_read(&engine->execlists.tasklet.count)));
sys/dev/drm/i915/intel_engine_cs.c
1373
I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
sys/dev/drm/i915/intel_engine_cs.c
1375
I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
sys/dev/drm/i915/intel_engine_cs.c
1400
I915_READ(RING_PP_DIR_BASE(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1402
I915_READ(RING_PP_DIR_BASE_READ(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1404
I915_READ(RING_PP_DIR_DCLV(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1442
void intel_engine_dump(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_engine_cs.c
1447
struct intel_breadcrumbs * const b = &engine->breadcrumbs;
sys/dev/drm/i915/intel_engine_cs.c
1448
const struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_engine_cs.c
1449
struct i915_gpu_error * const error = &engine->i915->gpu_error;
sys/dev/drm/i915/intel_engine_cs.c
1463
if (i915_terminally_wedged(&engine->i915->gpu_error))
sys/dev/drm/i915/intel_engine_cs.c
1467
intel_engine_get_seqno(engine),
sys/dev/drm/i915/intel_engine_cs.c
1468
intel_engine_last_submit(engine),
sys/dev/drm/i915/intel_engine_cs.c
1469
engine->hangcheck.seqno,
sys/dev/drm/i915/intel_engine_cs.c
1470
jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
sys/dev/drm/i915/intel_engine_cs.c
1472
i915_reset_engine_count(error, engine),
sys/dev/drm/i915/intel_engine_cs.c
1479
rq = list_first_entry(&engine->timeline.requests,
sys/dev/drm/i915/intel_engine_cs.c
1481
if (&rq->link != &engine->timeline.requests)
sys/dev/drm/i915/intel_engine_cs.c
1484
rq = list_last_entry(&engine->timeline.requests,
sys/dev/drm/i915/intel_engine_cs.c
1486
if (&rq->link != &engine->timeline.requests)
sys/dev/drm/i915/intel_engine_cs.c
1489
rq = i915_gem_find_active_request(engine);
sys/dev/drm/i915/intel_engine_cs.c
1509
if (intel_runtime_pm_get_if_in_use(engine->i915)) {
sys/dev/drm/i915/intel_engine_cs.c
1510
intel_engine_print_registers(engine, m);
sys/dev/drm/i915/intel_engine_cs.c
1511
intel_runtime_pm_put(engine->i915);
sys/dev/drm/i915/intel_engine_cs.c
1517
lockmgr(&engine->timeline.lock, LK_EXCLUSIVE);
sys/dev/drm/i915/intel_engine_cs.c
1521
list_for_each_entry(rq, &engine->timeline.requests, link) {
sys/dev/drm/i915/intel_engine_cs.c
1559
lockmgr(&engine->timeline.lock, LK_RELEASE);
sys/dev/drm/i915/intel_engine_cs.c
1572
engine->irq_posted,
sys/dev/drm/i915/intel_engine_cs.c
1574
&engine->irq_posted)));
sys/dev/drm/i915/intel_engine_cs.c
1577
linux_hexdump(m, engine->status_page.page_addr, PAGE_SIZE);
sys/dev/drm/i915/intel_engine_cs.c
1579
drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
sys/dev/drm/i915/intel_engine_cs.c
1613
int intel_enable_engine_stats(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
1615
struct intel_engine_execlists *execlists = &engine->execlists;
sys/dev/drm/i915/intel_engine_cs.c
1619
if (!intel_engine_supports_stats(engine))
sys/dev/drm/i915/intel_engine_cs.c
1622
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_engine_cs.c
1623
write_seqlock(&engine->stats.lock);
sys/dev/drm/i915/intel_engine_cs.c
1625
if (unlikely(engine->stats.enabled == ~0)) {
sys/dev/drm/i915/intel_engine_cs.c
1630
if (engine->stats.enabled++ == 0) {
sys/dev/drm/i915/intel_engine_cs.c
1634
engine->stats.enabled_at = ktime_get();
sys/dev/drm/i915/intel_engine_cs.c
1638
engine->stats.active++;
sys/dev/drm/i915/intel_engine_cs.c
1642
if (engine->stats.active)
sys/dev/drm/i915/intel_engine_cs.c
1643
engine->stats.start = engine->stats.enabled_at;
sys/dev/drm/i915/intel_engine_cs.c
1647
write_sequnlock(&engine->stats.lock);
sys/dev/drm/i915/intel_engine_cs.c
1648
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_engine_cs.c
1653
static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
1655
ktime_t total = engine->stats.total;
sys/dev/drm/i915/intel_engine_cs.c
1661
if (engine->stats.active)
sys/dev/drm/i915/intel_engine_cs.c
1663
ktime_sub(ktime_get(), engine->stats.start));
sys/dev/drm/i915/intel_engine_cs.c
1674
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
1680
seq = read_seqbegin(&engine->stats.lock);
sys/dev/drm/i915/intel_engine_cs.c
1681
total = __intel_engine_get_busy_time(engine);
sys/dev/drm/i915/intel_engine_cs.c
1682
} while (read_seqretry(&engine->stats.lock, seq));
sys/dev/drm/i915/intel_engine_cs.c
1693
void intel_disable_engine_stats(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
1701
if (!intel_engine_supports_stats(engine))
sys/dev/drm/i915/intel_engine_cs.c
1704
write_seqlock_irqsave(&engine->stats.lock, flags);
sys/dev/drm/i915/intel_engine_cs.c
1705
WARN_ON_ONCE(engine->stats.enabled == 0);
sys/dev/drm/i915/intel_engine_cs.c
1706
if (--engine->stats.enabled == 0) {
sys/dev/drm/i915/intel_engine_cs.c
1707
engine->stats.total = __intel_engine_get_busy_time(engine);
sys/dev/drm/i915/intel_engine_cs.c
1708
engine->stats.active = 0;
sys/dev/drm/i915/intel_engine_cs.c
1710
write_sequnlock_irqrestore(&engine->stats.lock, flags);
sys/dev/drm/i915/intel_engine_cs.c
269
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
285
GEM_BUG_ON(dev_priv->engine[id]);
sys/dev/drm/i915/intel_engine_cs.c
286
engine = kzalloc(sizeof(*engine), GFP_KERNEL);
sys/dev/drm/i915/intel_engine_cs.c
287
if (!engine)
sys/dev/drm/i915/intel_engine_cs.c
290
engine->id = id;
sys/dev/drm/i915/intel_engine_cs.c
291
engine->i915 = dev_priv;
sys/dev/drm/i915/intel_engine_cs.c
292
__sprint_engine_name(engine->name, info);
sys/dev/drm/i915/intel_engine_cs.c
293
engine->hw_id = engine->guc_id = info->hw_id;
sys/dev/drm/i915/intel_engine_cs.c
294
engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases);
sys/dev/drm/i915/intel_engine_cs.c
295
engine->class = info->class;
sys/dev/drm/i915/intel_engine_cs.c
296
engine->instance = info->instance;
sys/dev/drm/i915/intel_engine_cs.c
298
engine->uabi_id = info->uabi_id;
sys/dev/drm/i915/intel_engine_cs.c
299
engine->uabi_class = intel_engine_classes[info->class].uabi_class;
sys/dev/drm/i915/intel_engine_cs.c
301
engine->context_size = __intel_engine_context_size(dev_priv,
sys/dev/drm/i915/intel_engine_cs.c
302
engine->class);
sys/dev/drm/i915/intel_engine_cs.c
303
if (WARN_ON(engine->context_size > BIT(20)))
sys/dev/drm/i915/intel_engine_cs.c
304
engine->context_size = 0;
sys/dev/drm/i915/intel_engine_cs.c
305
if (engine->context_size)
sys/dev/drm/i915/intel_engine_cs.c
309
engine->schedule = NULL;
sys/dev/drm/i915/intel_engine_cs.c
311
seqlock_init(&engine->stats.lock);
sys/dev/drm/i915/intel_engine_cs.c
313
ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
sys/dev/drm/i915/intel_engine_cs.c
315
dev_priv->engine_class[info->class][info->instance] = engine;
sys/dev/drm/i915/intel_engine_cs.c
316
dev_priv->engine[id] = engine;
sys/dev/drm/i915/intel_engine_cs.c
330
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
372
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_engine_cs.c
373
kfree(engine);
sys/dev/drm/i915/intel_engine_cs.c
385
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
389
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_engine_cs.c
391
&intel_engine_classes[engine->class];
sys/dev/drm/i915/intel_engine_cs.c
392
int (*init)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_engine_cs.c
405
err = init(engine);
sys/dev/drm/i915/intel_engine_cs.c
409
GEM_BUG_ON(!engine->submit_request);
sys/dev/drm/i915/intel_engine_cs.c
415
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_engine_cs.c
417
kfree(engine);
sys/dev/drm/i915/intel_engine_cs.c
418
dev_priv->engine[id] = NULL;
sys/dev/drm/i915/intel_engine_cs.c
420
dev_priv->gt.cleanup_engine(engine);
sys/dev/drm/i915/intel_engine_cs.c
426
void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
sys/dev/drm/i915/intel_engine_cs.c
428
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
439
I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
sys/dev/drm/i915/intel_engine_cs.c
440
I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
sys/dev/drm/i915/intel_engine_cs.c
442
I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
sys/dev/drm/i915/intel_engine_cs.c
445
intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
sys/dev/drm/i915/intel_engine_cs.c
446
clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
sys/dev/drm/i915/intel_engine_cs.c
451
intel_engine_wakeup(engine);
sys/dev/drm/i915/intel_engine_cs.c
453
GEM_BUG_ON(intel_engine_get_seqno(engine) != seqno);
sys/dev/drm/i915/intel_engine_cs.c
456
static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
458
i915_gem_batch_pool_init(&engine->batch_pool, engine);
sys/dev/drm/i915/intel_engine_cs.c
461
static void intel_engine_init_execlist(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
463
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_engine_cs.c
482
void intel_engine_setup_common(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
484
i915_timeline_init(engine->i915, &engine->timeline, engine->name);
sys/dev/drm/i915/intel_engine_cs.c
485
lockdep_set_subclass(&engine->timeline.lock, TIMELINE_ENGINE);
sys/dev/drm/i915/intel_engine_cs.c
487
intel_engine_init_execlist(engine);
sys/dev/drm/i915/intel_engine_cs.c
488
intel_engine_init_hangcheck(engine);
sys/dev/drm/i915/intel_engine_cs.c
489
intel_engine_init_batch_pool(engine);
sys/dev/drm/i915/intel_engine_cs.c
490
intel_engine_init_cmd_parser(engine);
sys/dev/drm/i915/intel_engine_cs.c
493
static void cleanup_status_page(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
495
if (HWS_NEEDS_PHYSICAL(engine->i915)) {
sys/dev/drm/i915/intel_engine_cs.c
496
void *addr = fetch_and_zero(&engine->status_page.page_addr);
sys/dev/drm/i915/intel_engine_cs.c
50
int (*init_legacy)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_engine_cs.c
501
i915_vma_unpin_and_release(&engine->status_page.vma,
sys/dev/drm/i915/intel_engine_cs.c
505
static int init_status_page(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
51
int (*init_execlists)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_engine_cs.c
513
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
sys/dev/drm/i915/intel_engine_cs.c
523
vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
sys/dev/drm/i915/intel_engine_cs.c
530
if (!HAS_LLC(engine->i915))
sys/dev/drm/i915/intel_engine_cs.c
554
engine->status_page.vma = vma;
sys/dev/drm/i915/intel_engine_cs.c
555
engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
sys/dev/drm/i915/intel_engine_cs.c
556
engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
sys/dev/drm/i915/intel_engine_cs.c
566
static int init_phys_status_page(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
579
engine->status_page.page_addr = page_address(page);
sys/dev/drm/i915/intel_engine_cs.c
585
struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
587
intel_context_unpin(to_intel_context(ctx, engine));
sys/dev/drm/i915/intel_engine_cs.c
601
int intel_engine_init_common(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
603
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
607
engine->set_default_submission(engine);
sys/dev/drm/i915/intel_engine_cs.c
616
ce = intel_context_pin(i915->kernel_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
625
ce = intel_context_pin(i915->preempt_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
632
ret = intel_engine_init_breadcrumbs(engine);
sys/dev/drm/i915/intel_engine_cs.c
637
ret = init_phys_status_page(engine);
sys/dev/drm/i915/intel_engine_cs.c
639
ret = init_status_page(engine);
sys/dev/drm/i915/intel_engine_cs.c
646
intel_engine_fini_breadcrumbs(engine);
sys/dev/drm/i915/intel_engine_cs.c
649
__intel_context_unpin(i915->preempt_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
652
__intel_context_unpin(i915->kernel_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
663
void intel_engine_cleanup_common(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
665
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
667
cleanup_status_page(engine);
sys/dev/drm/i915/intel_engine_cs.c
669
intel_engine_fini_breadcrumbs(engine);
sys/dev/drm/i915/intel_engine_cs.c
670
intel_engine_cleanup_cmd_parser(engine);
sys/dev/drm/i915/intel_engine_cs.c
671
i915_gem_batch_pool_fini(&engine->batch_pool);
sys/dev/drm/i915/intel_engine_cs.c
673
if (engine->default_state)
sys/dev/drm/i915/intel_engine_cs.c
674
i915_gem_object_put(engine->default_state);
sys/dev/drm/i915/intel_engine_cs.c
677
__intel_context_unpin(i915->preempt_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
678
__intel_context_unpin(i915->kernel_context, engine);
sys/dev/drm/i915/intel_engine_cs.c
680
i915_timeline_fini(&engine->timeline);
sys/dev/drm/i915/intel_engine_cs.c
682
intel_wa_list_free(&engine->wa_list);
sys/dev/drm/i915/intel_engine_cs.c
685
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
687
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
691
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
sys/dev/drm/i915/intel_engine_cs.c
692
RING_ACTHD_UDW(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
694
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
701
u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
703
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
707
bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base),
sys/dev/drm/i915/intel_engine_cs.c
708
RING_BBADDR_UDW(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
710
bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
sys/dev/drm/i915/intel_engine_cs.c
715
int intel_engine_stop_cs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
717
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
718
const u32 base = engine->mmio_base;
sys/dev/drm/i915/intel_engine_cs.c
725
GEM_TRACE("%s\n", engine->name);
sys/dev/drm/i915/intel_engine_cs.c
734
GEM_TRACE("%s: timed out on STOP_RING -> IDLE\n", engine->name);
sys/dev/drm/i915/intel_engine_cs.c
744
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
746
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
748
GEM_TRACE("%s\n", engine->name);
sys/dev/drm/i915/intel_engine_cs.c
750
I915_WRITE_FW(RING_MI_MODE(engine->mmio_base),
sys/dev/drm/i915/intel_engine_cs.c
841
void intel_engine_get_instdone(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_engine_cs.c
844
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
845
u32 mmio_base = engine->mmio_base;
sys/dev/drm/i915/intel_engine_cs.c
855
if (engine->id != RCS)
sys/dev/drm/i915/intel_engine_cs.c
871
if (engine->id != RCS)
sys/dev/drm/i915/intel_engine_cs.c
884
if (engine->id == RCS)
sys/dev/drm/i915/intel_engine_cs.c
895
static bool ring_is_idle(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
897
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
905
if ((I915_READ_HEAD(engine) & HEAD_ADDR) !=
sys/dev/drm/i915/intel_engine_cs.c
906
(I915_READ_TAIL(engine) & TAIL_ADDR))
sys/dev/drm/i915/intel_engine_cs.c
910
if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE))
sys/dev/drm/i915/intel_engine_cs.c
925
bool intel_engine_is_idle(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_engine_cs.c
927
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_engine_cs.c
934
if (!intel_engine_signaled(engine, intel_engine_last_submit(engine)))
sys/dev/drm/i915/intel_engine_cs.c
937
if (I915_SELFTEST_ONLY(engine->breadcrumbs.mock))
sys/dev/drm/i915/intel_engine_cs.c
941
if (READ_ONCE(engine->execlists.active)) {
sys/dev/drm/i915/intel_engine_cs.c
942
struct tasklet_struct *t = &engine->execlists.tasklet;
sys/dev/drm/i915/intel_engine_cs.c
956
if (READ_ONCE(engine->execlists.active))
sys/dev/drm/i915/intel_engine_cs.c
961
if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
sys/dev/drm/i915/intel_engine_cs.c
965
if (!ring_is_idle(engine))
sys/dev/drm/i915/intel_engine_cs.c
973
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_engine_cs.c
983
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_engine_cs.c
984
if (!intel_engine_is_idle(engine))
sys/dev/drm/i915/intel_engine_cs.c
999
bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_gpu_commands.h
106
#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
sys/dev/drm/i915/intel_guc.c
559
struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc.c
566
data[1] = engine->guc_id;
sys/dev/drm/i915/intel_guc.h
39
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_ads.c
108
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_guc_ads.c
109
blob->reg_state.white_list[engine->guc_id].mmio_start =
sys/dev/drm/i915/intel_guc_ads.c
110
engine->mmio_base + GUC_MMIO_WHITE_LIST_START;
sys/dev/drm/i915/intel_guc_ads.c
113
blob->reg_state.white_list[engine->guc_id].count = 0;
sys/dev/drm/i915/intel_guc_ads.c
125
dev_priv->engine[RCS])->state;
sys/dev/drm/i915/intel_guc_ads.c
135
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_guc_ads.c
136
blob->ads.eng_state_size[engine->guc_id] =
sys/dev/drm/i915/intel_guc_ads.c
137
engine->context_size - skipped_size;
sys/dev/drm/i915/intel_guc_ads.c
87
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
1122
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
1143
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_guc_submission.c
1144
guc->preempt_work[id].engine = engine;
sys/dev/drm/i915/intel_guc_submission.c
1158
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
1161
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_guc_submission.c
1174
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
1182
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_guc_submission.c
1183
I915_WRITE(RING_MODE_GEN7(engine), irqs);
sys/dev/drm/i915/intel_guc_submission.c
1219
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
1229
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_guc_submission.c
1230
I915_WRITE(RING_MODE_GEN7(engine), irqs);
sys/dev/drm/i915/intel_guc_submission.c
1241
static void guc_submission_park(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
1243
intel_engine_unpin_breadcrumbs_irq(engine);
sys/dev/drm/i915/intel_guc_submission.c
1246
static void guc_submission_unpark(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
1248
intel_engine_pin_breadcrumbs_irq(engine);
sys/dev/drm/i915/intel_guc_submission.c
1251
static void guc_set_default_submission(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
1264
intel_execlists_set_default_submission(engine);
sys/dev/drm/i915/intel_guc_submission.c
1266
engine->execlists.tasklet.func = guc_submission_tasklet;
sys/dev/drm/i915/intel_guc_submission.c
1268
engine->park = guc_submission_park;
sys/dev/drm/i915/intel_guc_submission.c
1269
engine->unpark = guc_submission_unpark;
sys/dev/drm/i915/intel_guc_submission.c
1271
engine->reset.prepare = guc_reset_prepare;
sys/dev/drm/i915/intel_guc_submission.c
1273
engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
sys/dev/drm/i915/intel_guc_submission.c
1279
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
1292
BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.port) *
sys/dev/drm/i915/intel_guc_submission.c
1313
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_guc_submission.c
1314
engine->set_default_submission = guc_set_default_submission;
sys/dev/drm/i915/intel_guc_submission.c
1315
engine->set_default_submission(engine);
sys/dev/drm/i915/intel_guc_submission.c
348
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_guc_submission.c
365
for_each_engine_masked(engine, dev_priv, client->engines, tmp) {
sys/dev/drm/i915/intel_guc_submission.c
366
struct intel_context *ce = to_intel_context(ctx, engine);
sys/dev/drm/i915/intel_guc_submission.c
367
u32 guc_engine_id = engine->guc_id;
sys/dev/drm/i915/intel_guc_submission.c
521
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/intel_guc_submission.c
527
guc_wq_item_append(client, engine->guc_id, ctx_desc,
sys/dev/drm/i915/intel_guc_submission.c
531
client->submissions[engine->id] += 1;
sys/dev/drm/i915/intel_guc_submission.c
555
struct intel_engine_cs *engine = preempt_work->engine;
sys/dev/drm/i915/intel_guc_submission.c
557
preempt_work[engine->id]);
sys/dev/drm/i915/intel_guc_submission.c
560
struct intel_context *ce = to_intel_context(client->owner, engine);
sys/dev/drm/i915/intel_guc_submission.c
564
u32 addr = intel_hws_preempt_done_address(engine);
sys/dev/drm/i915/intel_guc_submission.c
568
if (engine->id == RCS) {
sys/dev/drm/i915/intel_guc_submission.c
589
guc_wq_item_append(client, engine->guc_id, lower_32_bits(ce->lrc_desc),
sys/dev/drm/i915/intel_guc_submission.c
611
data[3] = engine->guc_id;
sys/dev/drm/i915/intel_guc_submission.c
617
execlists_clear_active(&engine->execlists,
sys/dev/drm/i915/intel_guc_submission.c
619
tasklet_schedule(&engine->execlists.tasklet);
sys/dev/drm/i915/intel_guc_submission.c
632
static void wait_for_guc_preempt_report(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
634
struct intel_guc *guc = &engine->i915->guc;
sys/dev/drm/i915/intel_guc_submission.c
637
&data->preempt_ctx_report[engine->guc_id];
sys/dev/drm/i915/intel_guc_submission.c
651
static void complete_preempt_context(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
653
struct intel_engine_execlists *execlists = &engine->execlists;
sys/dev/drm/i915/intel_guc_submission.c
663
wait_for_guc_preempt_report(engine);
sys/dev/drm/i915/intel_guc_submission.c
664
intel_write_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX, 0);
sys/dev/drm/i915/intel_guc_submission.c
674
static void guc_submit(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
676
struct intel_guc *guc = &engine->i915->guc;
sys/dev/drm/i915/intel_guc_submission.c
677
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_guc_submission.c
713
static bool __guc_dequeue(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
715
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_guc_submission.c
723
lockdep_assert_held(&engine->timeline.lock);
sys/dev/drm/i915/intel_guc_submission.c
726
if (intel_engine_has_preemption(engine)) {
sys/dev/drm/i915/intel_guc_submission.c
728
&engine->i915->guc.preempt_work[engine->id];
sys/dev/drm/i915/intel_guc_submission.c
734
queue_work(engine->i915->guc.preempt_wq,
sys/dev/drm/i915/intel_guc_submission.c
774
kmem_cache_free(engine->i915->priorities, p);
sys/dev/drm/i915/intel_guc_submission.c
792
static void guc_dequeue(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
799
lockmgr(&engine->timeline.lock, LK_EXCLUSIVE);
sys/dev/drm/i915/intel_guc_submission.c
800
submit = __guc_dequeue(engine);
sys/dev/drm/i915/intel_guc_submission.c
801
lockmgr(&engine->timeline.lock, LK_RELEASE);
sys/dev/drm/i915/intel_guc_submission.c
804
guc_submit(engine);
sys/dev/drm/i915/intel_guc_submission.c
811
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
sys/dev/drm/i915/intel_guc_submission.c
812
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_guc_submission.c
832
intel_read_status_page(engine, I915_GEM_HWS_PREEMPT_INDEX) ==
sys/dev/drm/i915/intel_guc_submission.c
834
complete_preempt_context(engine);
sys/dev/drm/i915/intel_guc_submission.c
837
guc_dequeue(engine);
sys/dev/drm/i915/intel_guc_submission.c
841
guc_reset_prepare(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_guc_submission.c
843
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_guc_submission.c
845
GEM_TRACE("%s\n", engine->name);
sys/dev/drm/i915/intel_guc_submission.c
865
if (engine->i915->guc.preempt_wq)
sys/dev/drm/i915/intel_guc_submission.c
866
flush_workqueue(engine->i915->guc.preempt_wq);
sys/dev/drm/i915/intel_guc_submission.c
868
return i915_gem_find_active_request(engine);
sys/dev/drm/i915/intel_hangcheck.c
101
vaddr = (void __iomem *)engine->buffer->vaddr;
sys/dev/drm/i915/intel_hangcheck.c
109
head &= engine->buffer->size - 1;
sys/dev/drm/i915/intel_hangcheck.c
123
return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
sys/dev/drm/i915/intel_hangcheck.c
126
static int semaphore_passed(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_hangcheck.c
128
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_hangcheck.c
132
engine->hangcheck.deadlock++;
sys/dev/drm/i915/intel_hangcheck.c
134
signaller = semaphore_waits_for(engine, &seqno);
sys/dev/drm/i915/intel_hangcheck.c
158
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_hangcheck.c
161
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_hangcheck.c
162
engine->hangcheck.deadlock = 0;
sys/dev/drm/i915/intel_hangcheck.c
176
static bool subunits_stuck(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_hangcheck.c
178
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_hangcheck.c
180
struct intel_instdone *accu_instdone = &engine->hangcheck.instdone;
sys/dev/drm/i915/intel_hangcheck.c
185
if (engine->id != RCS)
sys/dev/drm/i915/intel_hangcheck.c
188
intel_engine_get_instdone(engine, &instdone);
sys/dev/drm/i915/intel_hangcheck.c
211
head_stuck(struct intel_engine_cs *engine, u64 acthd)
sys/dev/drm/i915/intel_hangcheck.c
213
if (acthd != engine->hangcheck.acthd) {
sys/dev/drm/i915/intel_hangcheck.c
216
memset(&engine->hangcheck.instdone, 0,
sys/dev/drm/i915/intel_hangcheck.c
217
sizeof(engine->hangcheck.instdone));
sys/dev/drm/i915/intel_hangcheck.c
222
if (!subunits_stuck(engine))
sys/dev/drm/i915/intel_hangcheck.c
229
engine_stuck(struct intel_engine_cs *engine, u64 acthd)
sys/dev/drm/i915/intel_hangcheck.c
231
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_hangcheck.c
235
ha = head_stuck(engine, acthd);
sys/dev/drm/i915/intel_hangcheck.c
247
tmp = I915_READ_CTL(engine);
sys/dev/drm/i915/intel_hangcheck.c
249
i915_handle_error(dev_priv, BIT(engine->id), 0,
sys/dev/drm/i915/intel_hangcheck.c
250
"stuck wait on %s", engine->name);
sys/dev/drm/i915/intel_hangcheck.c
251
I915_WRITE_CTL(engine, tmp);
sys/dev/drm/i915/intel_hangcheck.c
256
switch (semaphore_passed(engine)) {
sys/dev/drm/i915/intel_hangcheck.c
262
engine->name);
sys/dev/drm/i915/intel_hangcheck.c
263
I915_WRITE_CTL(engine, tmp);
sys/dev/drm/i915/intel_hangcheck.c
273
static void hangcheck_load_sample(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_hangcheck.c
28
ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
sys/dev/drm/i915/intel_hangcheck.c
283
if (engine->irq_seqno_barrier)
sys/dev/drm/i915/intel_hangcheck.c
284
engine->irq_seqno_barrier(engine);
sys/dev/drm/i915/intel_hangcheck.c
286
hc->acthd = intel_engine_get_active_head(engine);
sys/dev/drm/i915/intel_hangcheck.c
287
hc->seqno = intel_engine_get_seqno(engine);
sys/dev/drm/i915/intel_hangcheck.c
290
static void hangcheck_store_sample(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_hangcheck.c
293
engine->hangcheck.acthd = hc->acthd;
sys/dev/drm/i915/intel_hangcheck.c
294
engine->hangcheck.seqno = hc->seqno;
sys/dev/drm/i915/intel_hangcheck.c
295
engine->hangcheck.action = hc->action;
sys/dev/drm/i915/intel_hangcheck.c
296
engine->hangcheck.stalled = hc->stalled;
sys/dev/drm/i915/intel_hangcheck.c
297
engine->hangcheck.wedged = hc->wedged;
sys/dev/drm/i915/intel_hangcheck.c
301
hangcheck_get_action(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_hangcheck.c
304
if (engine->hangcheck.seqno != hc->seqno)
sys/dev/drm/i915/intel_hangcheck.c
307
if (intel_engine_is_idle(engine))
sys/dev/drm/i915/intel_hangcheck.c
310
return engine_stuck(engine, hc->acthd);
sys/dev/drm/i915/intel_hangcheck.c
313
static void hangcheck_accumulate_sample(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_hangcheck.c
318
hc->action = hangcheck_get_action(engine, hc);
sys/dev/drm/i915/intel_hangcheck.c
341
memset(&engine->hangcheck.instdone, 0,
sys/dev/drm/i915/intel_hangcheck.c
342
sizeof(engine->hangcheck.instdone));
sys/dev/drm/i915/intel_hangcheck.c
347
engine->hangcheck.action_timestamp = jiffies;
sys/dev/drm/i915/intel_hangcheck.c
36
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
sys/dev/drm/i915/intel_hangcheck.c
362
intel_engine_dump(engine, &p, "%s\n", engine->name);
sys/dev/drm/i915/intel_hangcheck.c
371
engine->hangcheck.action_timestamp + timeout);
sys/dev/drm/i915/intel_hangcheck.c
373
engine->hangcheck.action_timestamp +
sys/dev/drm/i915/intel_hangcheck.c
381
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_hangcheck.c
39
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_hangcheck.c
393
for_each_engine_masked(engine, i915, hung, tmp)
sys/dev/drm/i915/intel_hangcheck.c
395
"%s, ", engine->name);
sys/dev/drm/i915/intel_hangcheck.c
414
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_hangcheck.c
433
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_hangcheck.c
438
hangcheck_load_sample(engine, &hc);
sys/dev/drm/i915/intel_hangcheck.c
439
hangcheck_accumulate_sample(engine, &hc);
sys/dev/drm/i915/intel_hangcheck.c
440
hangcheck_store_sample(engine, &hc);
sys/dev/drm/i915/intel_hangcheck.c
442
if (engine->hangcheck.stalled) {
sys/dev/drm/i915/intel_hangcheck.c
443
hung |= intel_engine_flag(engine);
sys/dev/drm/i915/intel_hangcheck.c
445
stuck |= intel_engine_flag(engine);
sys/dev/drm/i915/intel_hangcheck.c
448
if (engine->hangcheck.wedged)
sys/dev/drm/i915/intel_hangcheck.c
449
wedged |= intel_engine_flag(engine);
sys/dev/drm/i915/intel_hangcheck.c
45
if (engine == signaller)
sys/dev/drm/i915/intel_hangcheck.c
467
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_hangcheck.c
469
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
sys/dev/drm/i915/intel_hangcheck.c
470
engine->hangcheck.action_timestamp = jiffies;
sys/dev/drm/i915/intel_hangcheck.c
48
if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id])
sys/dev/drm/i915/intel_hangcheck.c
53
engine->name, ipehr);
sys/dev/drm/i915/intel_hangcheck.c
59
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
sys/dev/drm/i915/intel_hangcheck.c
61
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_hangcheck.c
84
if (engine->buffer == NULL)
sys/dev/drm/i915/intel_hangcheck.c
87
ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
sys/dev/drm/i915/intel_hangcheck.c
88
if (!ipehr_is_semaphore_wait(engine, ipehr))
sys/dev/drm/i915/intel_hangcheck.c
99
head = I915_READ_HEAD(engine) & HEAD_ADDR;
sys/dev/drm/i915/intel_lrc.c
1016
engine->name,
sys/dev/drm/i915/intel_lrc.c
1021
intel_engine_get_seqno(engine),
sys/dev/drm/i915/intel_lrc.c
1056
engine->name, port->context_id);
sys/dev/drm/i915/intel_lrc.c
1071
static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
sys/dev/drm/i915/intel_lrc.c
1073
lockdep_assert_held(&engine->timeline.lock);
sys/dev/drm/i915/intel_lrc.c
1075
process_csb(engine);
sys/dev/drm/i915/intel_lrc.c
1076
if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
sys/dev/drm/i915/intel_lrc.c
1077
execlists_dequeue(engine);
sys/dev/drm/i915/intel_lrc.c
1086
struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
sys/dev/drm/i915/intel_lrc.c
1090
engine->name,
sys/dev/drm/i915/intel_lrc.c
1091
engine->i915->gt.awake,
sys/dev/drm/i915/intel_lrc.c
1092
engine->execlists.active);
sys/dev/drm/i915/intel_lrc.c
1094
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1095
__execlists_submission_tasklet(engine);
sys/dev/drm/i915/intel_lrc.c
1096
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1099
static void queue_request(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1104
&lookup_priolist(engine, prio)->requests);
sys/dev/drm/i915/intel_lrc.c
1107
static void __update_queue(struct intel_engine_cs *engine, int prio)
sys/dev/drm/i915/intel_lrc.c
1109
engine->execlists.queue_priority = prio;
sys/dev/drm/i915/intel_lrc.c
1112
static void __submit_queue_imm(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1114
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
1120
__execlists_submission_tasklet(engine);
sys/dev/drm/i915/intel_lrc.c
1125
static void submit_queue(struct intel_engine_cs *engine, int prio)
sys/dev/drm/i915/intel_lrc.c
1127
if (prio > engine->execlists.queue_priority) {
sys/dev/drm/i915/intel_lrc.c
1128
__update_queue(engine, prio);
sys/dev/drm/i915/intel_lrc.c
1129
__submit_queue_imm(engine);
sys/dev/drm/i915/intel_lrc.c
1135
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/intel_lrc.c
1139
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1141
queue_request(engine, &request->sched, rq_prio(request));
sys/dev/drm/i915/intel_lrc.c
1143
GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
sys/dev/drm/i915/intel_lrc.c
1146
submit_queue(engine, rq_prio(request));
sys/dev/drm/i915/intel_lrc.c
1148
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1159
struct intel_engine_cs *engine = sched_to_request(node)->engine;
sys/dev/drm/i915/intel_lrc.c
1163
if (engine != locked) {
sys/dev/drm/i915/intel_lrc.c
1165
lockmgr(&engine->timeline.lock, LK_EXCLUSIVE);
sys/dev/drm/i915/intel_lrc.c
1168
return engine;
sys/dev/drm/i915/intel_lrc.c
1179
struct intel_engine_cs *engine, *last;
sys/dev/drm/i915/intel_lrc.c
1253
engine = request->engine;
sys/dev/drm/i915/intel_lrc.c
1254
spin_lock_irq(&engine->timeline.lock);
sys/dev/drm/i915/intel_lrc.c
1262
engine = sched_lock_engine(node, engine);
sys/dev/drm/i915/intel_lrc.c
1269
if (last != engine) {
sys/dev/drm/i915/intel_lrc.c
1270
pl = lookup_priolist(engine, prio);
sys/dev/drm/i915/intel_lrc.c
1271
last = engine;
sys/dev/drm/i915/intel_lrc.c
1277
if (prio > engine->execlists.queue_priority &&
sys/dev/drm/i915/intel_lrc.c
1280
__update_queue(engine, prio);
sys/dev/drm/i915/intel_lrc.c
1281
tasklet_hi_schedule(&engine->execlists.tasklet);
sys/dev/drm/i915/intel_lrc.c
1285
spin_unlock_irq(&engine->timeline.lock);
sys/dev/drm/i915/intel_lrc.c
1337
__execlists_context_pin(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1344
ret = execlists_context_deferred_alloc(ctx, engine, ce);
sys/dev/drm/i915/intel_lrc.c
1369
intel_lr_context_descriptor_update(ctx, engine, ce);
sys/dev/drm/i915/intel_lrc.c
1400
execlists_context_pin(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1403
struct intel_context *ce = to_intel_context(ctx, engine);
sys/dev/drm/i915/intel_lrc.c
1413
return __execlists_context_pin(engine, ctx, ce);
sys/dev/drm/i915/intel_lrc.c
1460
gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
sys/dev/drm/i915/intel_lrc.c
1465
*batch++ = i915_scratch_offset(engine->i915) + 256;
sys/dev/drm/i915/intel_lrc.c
1479
*batch++ = i915_scratch_offset(engine->i915) + 256;
sys/dev/drm/i915/intel_lrc.c
1500
static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
sys/dev/drm/i915/intel_lrc.c
1506
if (IS_BROADWELL(engine->i915))
sys/dev/drm/i915/intel_lrc.c
1507
batch = gen8_emit_flush_coherentl3_wa(engine, batch);
sys/dev/drm/i915/intel_lrc.c
1516
i915_scratch_offset(engine->i915) +
sys/dev/drm/i915/intel_lrc.c
1553
static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
sys/dev/drm/i915/intel_lrc.c
1581
batch = gen8_emit_flush_coherentl3_wa(engine, batch);
sys/dev/drm/i915/intel_lrc.c
1587
if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
sys/dev/drm/i915/intel_lrc.c
1593
i915_scratch_offset(engine->i915)
sys/dev/drm/i915/intel_lrc.c
1598
if (HAS_POOLED_EU(engine->i915)) {
sys/dev/drm/i915/intel_lrc.c
1630
gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
sys/dev/drm/i915/intel_lrc.c
1665
static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1671
obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
sys/dev/drm/i915/intel_lrc.c
1675
vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
sys/dev/drm/i915/intel_lrc.c
168
struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1685
engine->wa_ctx.vma = vma;
sys/dev/drm/i915/intel_lrc.c
1693
static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1695
i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
sys/dev/drm/i915/intel_lrc.c
1698
typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
sys/dev/drm/i915/intel_lrc.c
1700
static int intel_init_workaround_bb(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1702
struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
sys/dev/drm/i915/intel_lrc.c
1711
if (GEM_WARN_ON(engine->id != RCS))
sys/dev/drm/i915/intel_lrc.c
1714
switch (INTEL_GEN(engine->i915)) {
sys/dev/drm/i915/intel_lrc.c
172
struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1730
MISSING_CASE(INTEL_GEN(engine->i915));
sys/dev/drm/i915/intel_lrc.c
1734
ret = lrc_setup_wa_ctx(engine);
sys/dev/drm/i915/intel_lrc.c
1756
batch_ptr = wa_bb_fn[i](engine, batch_ptr);
sys/dev/drm/i915/intel_lrc.c
1764
lrc_destroy_wa_ctx(engine);
sys/dev/drm/i915/intel_lrc.c
1769
static void enable_execlists(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1771
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
1773
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
sys/dev/drm/i915/intel_lrc.c
1784
I915_WRITE(RING_MODE_GEN7(engine),
sys/dev/drm/i915/intel_lrc.c
1787
I915_WRITE(RING_MODE_GEN7(engine),
sys/dev/drm/i915/intel_lrc.c
1790
I915_WRITE(RING_MI_MODE(engine->mmio_base),
sys/dev/drm/i915/intel_lrc.c
1793
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
sys/dev/drm/i915/intel_lrc.c
1794
engine->status_page.ggtt_offset);
sys/dev/drm/i915/intel_lrc.c
1795
POSTING_READ(RING_HWS_PGA(engine->mmio_base));
sys/dev/drm/i915/intel_lrc.c
1798
static bool unexpected_starting_state(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1800
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
1803
if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
sys/dev/drm/i915/intel_lrc.c
1811
static int gen8_init_common_ring(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1813
intel_engine_apply_workarounds(engine);
sys/dev/drm/i915/intel_lrc.c
1815
intel_mocs_init_engine(engine);
sys/dev/drm/i915/intel_lrc.c
1817
intel_engine_reset_breadcrumbs(engine);
sys/dev/drm/i915/intel_lrc.c
1819
if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
sys/dev/drm/i915/intel_lrc.c
1822
intel_engine_dump(engine, &p, NULL);
sys/dev/drm/i915/intel_lrc.c
1825
enable_execlists(engine);
sys/dev/drm/i915/intel_lrc.c
1830
static int gen8_init_render_ring(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1832
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
1835
ret = gen8_init_common_ring(engine);
sys/dev/drm/i915/intel_lrc.c
1839
intel_whitelist_workarounds_apply(engine);
sys/dev/drm/i915/intel_lrc.c
185
static inline bool need_preempt(const struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1854
static int gen9_init_render_ring(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1858
ret = gen8_init_common_ring(engine);
sys/dev/drm/i915/intel_lrc.c
1862
intel_whitelist_workarounds_apply(engine);
sys/dev/drm/i915/intel_lrc.c
1868
execlists_reset_prepare(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
1870
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
1874
GEM_TRACE("%s: depth<-%d\n", engine->name,
sys/dev/drm/i915/intel_lrc.c
1888
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
189
return (intel_engine_has_preemption(engine) &&
sys/dev/drm/i915/intel_lrc.c
1897
process_csb(engine);
sys/dev/drm/i915/intel_lrc.c
1911
intel_engine_stop_cs(engine);
sys/dev/drm/i915/intel_lrc.c
1914
&engine->timeline.requests,
sys/dev/drm/i915/intel_lrc.c
1924
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1929
static void execlists_reset(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
1932
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
1937
engine->name, request ? request->global_seqno : 0,
sys/dev/drm/i915/intel_lrc.c
1938
intel_engine_get_seqno(engine));
sys/dev/drm/i915/intel_lrc.c
1940
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1954
__unwind_incomplete_requests(engine);
sys/dev/drm/i915/intel_lrc.c
1957
reset_csb_pointers(&engine->execlists);
sys/dev/drm/i915/intel_lrc.c
1959
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
1984
if (engine->pinned_default_state) {
sys/dev/drm/i915/intel_lrc.c
1986
engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
sys/dev/drm/i915/intel_lrc.c
1987
engine->context_size - PAGE_SIZE);
sys/dev/drm/i915/intel_lrc.c
1990
request->gem_context, engine, request->ring);
sys/dev/drm/i915/intel_lrc.c
2004
static void execlists_reset_finish(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2006
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
2018
GEM_TRACE("%s: depth->%d\n", engine->name,
sys/dev/drm/i915/intel_lrc.c
2025
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/intel_lrc.c
2038
*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
sys/dev/drm/i915/intel_lrc.c
2040
*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
sys/dev/drm/i915/intel_lrc.c
2064
(intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
sys/dev/drm/i915/intel_lrc.c
2071
rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
sys/dev/drm/i915/intel_lrc.c
2110
static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2112
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
2113
I915_WRITE_IMR(engine,
sys/dev/drm/i915/intel_lrc.c
2114
~(engine->irq_enable_mask | engine->irq_keep_mask));
sys/dev/drm/i915/intel_lrc.c
2115
POSTING_READ_FW(RING_IMR(engine->mmio_base));
sys/dev/drm/i915/intel_lrc.c
2116
DRM_DEBUG("%s\n", engine->name);
sys/dev/drm/i915/intel_lrc.c
2119
static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2121
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
2122
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
sys/dev/drm/i915/intel_lrc.c
2123
DRM_DEBUG("%s\n", engine->name);
sys/dev/drm/i915/intel_lrc.c
2145
if (request->engine->id == VCS)
sys/dev/drm/i915/intel_lrc.c
2161
struct intel_engine_cs *engine = request->engine;
sys/dev/drm/i915/intel_lrc.c
2163
i915_scratch_offset(engine->i915) + 2 * CACHELINE_BYTES;
sys/dev/drm/i915/intel_lrc.c
222
struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
2247
intel_hws_seqno_address(request->engine));
sys/dev/drm/i915/intel_lrc.c
2263
intel_hws_seqno_address(request->engine));
sys/dev/drm/i915/intel_lrc.c
2296
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2305
&engine->execlists.tasklet.state)))
sys/dev/drm/i915/intel_lrc.c
2306
tasklet_kill(&engine->execlists.tasklet);
sys/dev/drm/i915/intel_lrc.c
2308
dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
2310
if (engine->buffer) {
sys/dev/drm/i915/intel_lrc.c
2311
WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
sys/dev/drm/i915/intel_lrc.c
2314
if (engine->cleanup)
sys/dev/drm/i915/intel_lrc.c
2315
engine->cleanup(engine);
sys/dev/drm/i915/intel_lrc.c
2317
intel_engine_cleanup_common(engine);
sys/dev/drm/i915/intel_lrc.c
2319
lrc_destroy_wa_ctx(engine);
sys/dev/drm/i915/intel_lrc.c
2321
engine->i915 = NULL;
sys/dev/drm/i915/intel_lrc.c
2322
dev_priv->engine[engine->id] = NULL;
sys/dev/drm/i915/intel_lrc.c
2323
kfree(engine);
sys/dev/drm/i915/intel_lrc.c
2326
void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2328
engine->submit_request = execlists_submit_request;
sys/dev/drm/i915/intel_lrc.c
2329
engine->cancel_requests = execlists_cancel_requests;
sys/dev/drm/i915/intel_lrc.c
2330
engine->schedule = execlists_schedule;
sys/dev/drm/i915/intel_lrc.c
2331
engine->execlists.tasklet.func = execlists_submission_tasklet;
sys/dev/drm/i915/intel_lrc.c
2333
engine->reset.prepare = execlists_reset_prepare;
sys/dev/drm/i915/intel_lrc.c
2335
engine->park = NULL;
sys/dev/drm/i915/intel_lrc.c
2336
engine->unpark = NULL;
sys/dev/drm/i915/intel_lrc.c
2338
engine->flags |= I915_ENGINE_SUPPORTS_STATS;
sys/dev/drm/i915/intel_lrc.c
2339
if (engine->i915->preempt_context)
sys/dev/drm/i915/intel_lrc.c
2340
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
sys/dev/drm/i915/intel_lrc.c
2342
engine->i915->caps.scheduler =
sys/dev/drm/i915/intel_lrc.c
2345
if (intel_engine_has_preemption(engine))
sys/dev/drm/i915/intel_lrc.c
2346
engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
sys/dev/drm/i915/intel_lrc.c
2350
logical_ring_default_vfuncs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2353
engine->init_hw = gen8_init_common_ring;
sys/dev/drm/i915/intel_lrc.c
2355
engine->reset.prepare = execlists_reset_prepare;
sys/dev/drm/i915/intel_lrc.c
2356
engine->reset.reset = execlists_reset;
sys/dev/drm/i915/intel_lrc.c
2357
engine->reset.finish = execlists_reset_finish;
sys/dev/drm/i915/intel_lrc.c
2359
engine->context_pin = execlists_context_pin;
sys/dev/drm/i915/intel_lrc.c
2360
engine->request_alloc = execlists_request_alloc;
sys/dev/drm/i915/intel_lrc.c
2362
engine->emit_flush = gen8_emit_flush;
sys/dev/drm/i915/intel_lrc.c
2363
engine->emit_breadcrumb = gen8_emit_breadcrumb;
sys/dev/drm/i915/intel_lrc.c
2364
engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
sys/dev/drm/i915/intel_lrc.c
2366
engine->set_default_submission = intel_execlists_set_default_submission;
sys/dev/drm/i915/intel_lrc.c
2368
if (INTEL_GEN(engine->i915) < 11) {
sys/dev/drm/i915/intel_lrc.c
2369
engine->irq_enable = gen8_logical_ring_enable_irq;
sys/dev/drm/i915/intel_lrc.c
2370
engine->irq_disable = gen8_logical_ring_disable_irq;
sys/dev/drm/i915/intel_lrc.c
2379
engine->emit_bb_start = gen8_emit_bb_start;
sys/dev/drm/i915/intel_lrc.c
2383
logical_ring_default_irqs(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2387
if (INTEL_GEN(engine->i915) < 11) {
sys/dev/drm/i915/intel_lrc.c
2396
shift = irq_shifts[engine->id];
sys/dev/drm/i915/intel_lrc.c
2399
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
sys/dev/drm/i915/intel_lrc.c
2400
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
sys/dev/drm/i915/intel_lrc.c
2404
logical_ring_setup(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2406
intel_engine_setup_common(engine);
sys/dev/drm/i915/intel_lrc.c
2409
engine->buffer = NULL;
sys/dev/drm/i915/intel_lrc.c
2411
tasklet_init(&engine->execlists.tasklet,
sys/dev/drm/i915/intel_lrc.c
2412
execlists_submission_tasklet, (unsigned long)engine);
sys/dev/drm/i915/intel_lrc.c
2414
logical_ring_default_vfuncs(engine);
sys/dev/drm/i915/intel_lrc.c
2415
logical_ring_default_irqs(engine);
sys/dev/drm/i915/intel_lrc.c
2424
static int logical_ring_init(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2426
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_lrc.c
2427
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
2430
ret = intel_engine_init_common(engine);
sys/dev/drm/i915/intel_lrc.c
2436
i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
sys/dev/drm/i915/intel_lrc.c
2438
i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
sys/dev/drm/i915/intel_lrc.c
2441
i915_mmio_reg_offset(RING_ELSP(engine));
sys/dev/drm/i915/intel_lrc.c
2447
to_intel_context(i915->preempt_context, engine);
sys/dev/drm/i915/intel_lrc.c
2454
i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
sys/dev/drm/i915/intel_lrc.c
2457
(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
sys/dev/drm/i915/intel_lrc.c
2465
&engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
sys/dev/drm/i915/intel_lrc.c
2468
&engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
sys/dev/drm/i915/intel_lrc.c
247
desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
sys/dev/drm/i915/intel_lrc.c
2476
int logical_render_ring_init(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2478
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
2481
logical_ring_setup(engine);
sys/dev/drm/i915/intel_lrc.c
2484
engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
sys/dev/drm/i915/intel_lrc.c
2488
engine->init_hw = gen9_init_render_ring;
sys/dev/drm/i915/intel_lrc.c
2490
engine->init_hw = gen8_init_render_ring;
sys/dev/drm/i915/intel_lrc.c
2491
engine->init_context = gen8_init_rcs_context;
sys/dev/drm/i915/intel_lrc.c
2492
engine->emit_flush = gen8_emit_flush_render;
sys/dev/drm/i915/intel_lrc.c
2493
engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
sys/dev/drm/i915/intel_lrc.c
2494
engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
sys/dev/drm/i915/intel_lrc.c
2496
ret = logical_ring_init(engine);
sys/dev/drm/i915/intel_lrc.c
2500
ret = intel_init_workaround_bb(engine);
sys/dev/drm/i915/intel_lrc.c
2511
intel_engine_init_workarounds(engine);
sys/dev/drm/i915/intel_lrc.c
2516
int logical_xcs_ring_init(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
2518
logical_ring_setup(engine);
sys/dev/drm/i915/intel_lrc.c
252
desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
sys/dev/drm/i915/intel_lrc.c
2520
return logical_ring_init(engine);
sys/dev/drm/i915/intel_lrc.c
2627
static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
263
lookup_priolist(struct intel_engine_cs *engine, int prio)
sys/dev/drm/i915/intel_lrc.c
2631
switch (INTEL_GEN(engine->i915)) {
sys/dev/drm/i915/intel_lrc.c
2633
MISSING_CASE(INTEL_GEN(engine->i915));
sys/dev/drm/i915/intel_lrc.c
265
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
2658
struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
2661
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_lrc.c
2663
u32 base = engine->mmio_base;
sys/dev/drm/i915/intel_lrc.c
2664
bool rcs = engine->class == RENDER_CLASS;
sys/dev/drm/i915/intel_lrc.c
2676
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
sys/dev/drm/i915/intel_lrc.c
2696
struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
sys/dev/drm/i915/intel_lrc.c
2709
intel_lr_indirect_ctx_offset(engine) << 6;
sys/dev/drm/i915/intel_lrc.c
2725
CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
sys/dev/drm/i915/intel_lrc.c
2726
CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
sys/dev/drm/i915/intel_lrc.c
2727
CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
sys/dev/drm/i915/intel_lrc.c
2728
CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
sys/dev/drm/i915/intel_lrc.c
2729
CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
sys/dev/drm/i915/intel_lrc.c
2730
CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
sys/dev/drm/i915/intel_lrc.c
2731
CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
sys/dev/drm/i915/intel_lrc.c
2732
CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
sys/dev/drm/i915/intel_lrc.c
2747
i915_oa_init_reg_state(engine, ctx, regs);
sys/dev/drm/i915/intel_lrc.c
2758
struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
2779
if (engine->default_state) {
sys/dev/drm/i915/intel_lrc.c
2788
defaults = i915_gem_object_pin_map(engine->default_state,
sys/dev/drm/i915/intel_lrc.c
2795
memcpy(vaddr + start, defaults + start, engine->context_size);
sys/dev/drm/i915/intel_lrc.c
2796
i915_gem_object_unpin_map(engine->default_state);
sys/dev/drm/i915/intel_lrc.c
2802
execlists_init_reg_state(regs, ctx, engine, ring);
sys/dev/drm/i915/intel_lrc.c
2803
if (!engine->default_state)
sys/dev/drm/i915/intel_lrc.c
2806
if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
sys/dev/drm/i915/intel_lrc.c
2817
struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_lrc.c
2830
context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
sys/dev/drm/i915/intel_lrc.c
2854
ring = intel_engine_create_ring(engine, timeline, ctx->ring_size);
sys/dev/drm/i915/intel_lrc.c
2861
ret = populate_lr_context(ctx, ctx_obj, engine, ring);
sys/dev/drm/i915/intel_lrc.c
2881
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_lrc.c
2897
for_each_engine(engine, i915, id) {
sys/dev/drm/i915/intel_lrc.c
2899
to_intel_context(ctx, engine);
sys/dev/drm/i915/intel_lrc.c
293
p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
sys/dev/drm/i915/intel_lrc.c
325
static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
335
lockdep_assert_held(&engine->timeline.lock);
sys/dev/drm/i915/intel_lrc.c
338
&engine->timeline.requests,
sys/dev/drm/i915/intel_lrc.c
349
p = lookup_priolist(engine, last_prio);
sys/dev/drm/i915/intel_lrc.c
360
struct intel_engine_cs *engine =
sys/dev/drm/i915/intel_lrc.c
361
container_of(execlists, typeof(*engine), execlists);
sys/dev/drm/i915/intel_lrc.c
364
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
366
__unwind_incomplete_requests(engine);
sys/dev/drm/i915/intel_lrc.c
368
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
381
atomic_notifier_call_chain(&rq->engine->context_status_notifier,
sys/dev/drm/i915/intel_lrc.c
402
intel_engine_context_in(rq->engine);
sys/dev/drm/i915/intel_lrc.c
408
intel_engine_context_out(rq->engine);
sys/dev/drm/i915/intel_lrc.c
470
static void execlists_submit_ports(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
472
struct intel_engine_execlists *execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
484
GEM_BUG_ON(!engine->i915->gt.awake);
sys/dev/drm/i915/intel_lrc.c
507
engine->name, n,
sys/dev/drm/i915/intel_lrc.c
511
intel_engine_get_seqno(engine),
sys/dev/drm/i915/intel_lrc.c
556
static void inject_preempt_context(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
558
struct intel_engine_execlists *execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
560
to_intel_context(engine->i915->preempt_context, engine);
sys/dev/drm/i915/intel_lrc.c
570
GEM_TRACE("%s\n", engine->name);
sys/dev/drm/i915/intel_lrc.c
597
static void execlists_dequeue(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
599
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
650
if (need_preempt(engine, last, execlists->queue_priority)) {
sys/dev/drm/i915/intel_lrc.c
651
inject_preempt_context(engine);
sys/dev/drm/i915/intel_lrc.c
752
kmem_cache_free(engine->i915->priorities, p);
sys/dev/drm/i915/intel_lrc.c
777
execlists_submit_ports(engine);
sys/dev/drm/i915/intel_lrc.c
789
GEM_BUG_ON(execlists_is_active(&engine->execlists,
sys/dev/drm/i915/intel_lrc.c
791
!port_isset(engine->execlists.port));
sys/dev/drm/i915/intel_lrc.c
804
rq->engine->name,
sys/dev/drm/i915/intel_lrc.c
808
intel_engine_get_seqno(rq->engine));
sys/dev/drm/i915/intel_lrc.c
845
static void execlists_cancel_requests(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
847
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
853
engine->name, intel_engine_get_seqno(engine));
sys/dev/drm/i915/intel_lrc.c
869
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
876
list_for_each_entry(rq, &engine->timeline.requests, link) {
sys/dev/drm/i915/intel_lrc.c
896
kmem_cache_free(engine->i915->priorities, p);
sys/dev/drm/i915/intel_lrc.c
908
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_lrc.c
917
static void process_csb(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_lrc.c
919
struct intel_engine_execlists * const execlists = &engine->execlists;
sys/dev/drm/i915/intel_lrc.c
936
GEM_TRACE("%s cs-irq head=%d, tail=%d, csb_write=%p\n", engine->name, head, tail, execlists->csb_write);
sys/dev/drm/i915/intel_lrc.c
977
engine->name, head,
sys/dev/drm/i915/intel_lrc.c
999
GEM_TRACE("%s preempt-idle\n", engine->name);
sys/dev/drm/i915/intel_lrc.h
105
void intel_execlists_set_default_submission(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_lrc.h
31
#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
sys/dev/drm/i915/intel_lrc.h
32
#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
sys/dev/drm/i915/intel_lrc.h
33
#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
sys/dev/drm/i915/intel_lrc.h
34
#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
sys/dev/drm/i915/intel_lrc.h
39
#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
sys/dev/drm/i915/intel_lrc.h
40
#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
sys/dev/drm/i915/intel_lrc.h
41
#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
sys/dev/drm/i915/intel_lrc.h
42
#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
sys/dev/drm/i915/intel_lrc.h
43
#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
sys/dev/drm/i915/intel_lrc.h
44
#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)
sys/dev/drm/i915/intel_lrc.h
70
void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_lrc.h
71
int logical_render_ring_init(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_lrc.h
72
int logical_xcs_ring_init(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_mocs.c
236
void intel_mocs_init_engine(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_mocs.c
238
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_mocs.c
248
I915_WRITE(mocs_register(engine->id, index),
sys/dev/drm/i915/intel_mocs.c
260
I915_WRITE(mocs_register(engine->id, index),
sys/dev/drm/i915/intel_mocs.c
277
enum intel_engine_id engine = rq->engine->id;
sys/dev/drm/i915/intel_mocs.c
291
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
sys/dev/drm/i915/intel_mocs.c
304
*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
sys/dev/drm/i915/intel_mocs.h
57
void intel_mocs_init_engine(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_overlay.c
240
struct intel_engine_cs *engine = dev_priv->engine[RCS];
sys/dev/drm/i915/intel_overlay.c
242
return i915_request_alloc(engine, dev_priv->kernel_context);
sys/dev/drm/i915/intel_pm.c
6920
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_pm.c
6950
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_pm.c
6951
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
sys/dev/drm/i915/intel_pm.c
7011
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_pm.c
7028
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_pm.c
7029
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
sys/dev/drm/i915/intel_pm.c
7085
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_pm.c
7111
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_pm.c
7112
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
sys/dev/drm/i915/intel_pm.c
7580
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_pm.c
7606
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_pm.c
7607
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
sys/dev/drm/i915/intel_pm.c
7675
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_pm.c
7697
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_pm.c
7698
I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
sys/dev/drm/i915/intel_ringbuffer.c
1173
intel_engine_create_ring(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.c
1182
GEM_BUG_ON(timeline == &engine->timeline);
sys/dev/drm/i915/intel_ringbuffer.c
1183
lockdep_assert_held(&engine->i915->drm.struct_mutex);
sys/dev/drm/i915/intel_ringbuffer.c
1198
if (IS_I830(engine->i915) || IS_I845G(engine->i915))
sys/dev/drm/i915/intel_ringbuffer.c
1203
vma = intel_ring_create_vma(engine->i915, size);
sys/dev/drm/i915/intel_ringbuffer.c
1311
alloc_context_vma(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
1313
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
1318
obj = i915_gem_object_create(i915, engine->context_size);
sys/dev/drm/i915/intel_ringbuffer.c
1322
if (engine->default_state) {
sys/dev/drm/i915/intel_ringbuffer.c
1331
defaults = i915_gem_object_pin_map(engine->default_state,
sys/dev/drm/i915/intel_ringbuffer.c
1338
memcpy(vaddr, defaults, engine->context_size);
sys/dev/drm/i915/intel_ringbuffer.c
1340
i915_gem_object_unpin_map(engine->default_state);
sys/dev/drm/i915/intel_ringbuffer.c
1380
__ring_context_pin(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.c
1386
if (!ce->state && engine->context_size) {
sys/dev/drm/i915/intel_ringbuffer.c
1389
vma = alloc_context_vma(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1409
GEM_BUG_ON(!engine->buffer);
sys/dev/drm/i915/intel_ringbuffer.c
1410
ce->ring = engine->buffer;
sys/dev/drm/i915/intel_ringbuffer.c
1427
intel_ring_context_pin(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.c
1430
struct intel_context *ce = to_intel_context(ctx, engine);
sys/dev/drm/i915/intel_ringbuffer.c
1440
return __ring_context_pin(engine, ctx, ce);
sys/dev/drm/i915/intel_ringbuffer.c
1443
static int intel_init_ring_buffer(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
1449
intel_engine_setup_common(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1451
timeline = i915_timeline_create(engine->i915, engine->name);
sys/dev/drm/i915/intel_ringbuffer.c
1457
ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
sys/dev/drm/i915/intel_ringbuffer.c
1468
GEM_BUG_ON(engine->buffer);
sys/dev/drm/i915/intel_ringbuffer.c
1469
engine->buffer = ring;
sys/dev/drm/i915/intel_ringbuffer.c
1471
err = intel_engine_init_common(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1482
intel_engine_cleanup_common(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1486
void intel_engine_cleanup(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
1488
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
1491
(I915_READ_MODE(engine) & MODE_IDLE) == 0);
sys/dev/drm/i915/intel_ringbuffer.c
1493
intel_ring_unpin(engine->buffer);
sys/dev/drm/i915/intel_ringbuffer.c
1494
intel_ring_free(engine->buffer);
sys/dev/drm/i915/intel_ringbuffer.c
1496
if (engine->cleanup)
sys/dev/drm/i915/intel_ringbuffer.c
1497
engine->cleanup(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1499
intel_engine_cleanup_common(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1501
dev_priv->engine[engine->id] = NULL;
sys/dev/drm/i915/intel_ringbuffer.c
1502
kfree(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1507
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_ringbuffer.c
1511
for_each_engine(engine, dev_priv, id)
sys/dev/drm/i915/intel_ringbuffer.c
1512
intel_ring_reset(engine->buffer, 0);
sys/dev/drm/i915/intel_ringbuffer.c
1518
const struct intel_engine_cs * const engine = rq->engine;
sys/dev/drm/i915/intel_ringbuffer.c
1526
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
sys/dev/drm/i915/intel_ringbuffer.c
1530
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
sys/dev/drm/i915/intel_ringbuffer.c
1540
const struct intel_engine_cs * const engine = rq->engine;
sys/dev/drm/i915/intel_ringbuffer.c
1549
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
sys/dev/drm/i915/intel_ringbuffer.c
1560
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/intel_ringbuffer.c
1600
if (signaller == engine)
sys/dev/drm/i915/intel_ringbuffer.c
1626
engine)->state) |
sys/dev/drm/i915/intel_ringbuffer.c
1647
if (signaller == engine)
sys/dev/drm/i915/intel_ringbuffer.c
1700
struct intel_engine_cs *engine = rq->engine;
sys/dev/drm/i915/intel_ringbuffer.c
1723
if (engine->id == BCS && IS_VALLEYVIEW(engine->i915))
sys/dev/drm/i915/intel_ringbuffer.c
1732
if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
sys/dev/drm/i915/intel_ringbuffer.c
1733
unwind_mm = intel_engine_flag(engine);
sys/dev/drm/i915/intel_ringbuffer.c
1740
GEM_BUG_ON(engine->id != RCS);
sys/dev/drm/i915/intel_ringbuffer.c
1758
ret = engine->emit_flush(rq, EMIT_INVALIDATE);
sys/dev/drm/i915/intel_ringbuffer.c
1774
ret = engine->emit_flush(rq, EMIT_INVALIDATE);
sys/dev/drm/i915/intel_ringbuffer.c
1778
ret = engine->emit_flush(rq, EMIT_FLUSH);
sys/dev/drm/i915/intel_ringbuffer.c
2112
struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2120
engine->semaphore.sync_to = gen6_ring_sync_to;
sys/dev/drm/i915/intel_ringbuffer.c
2121
engine->semaphore.signal = gen6_signal;
sys/dev/drm/i915/intel_ringbuffer.c
2158
if (i == engine->hw_id) {
sys/dev/drm/i915/intel_ringbuffer.c
2162
wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
sys/dev/drm/i915/intel_ringbuffer.c
2163
mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
sys/dev/drm/i915/intel_ringbuffer.c
2166
engine->semaphore.mbox.wait[i] = wait_mbox;
sys/dev/drm/i915/intel_ringbuffer.c
2167
engine->semaphore.mbox.signal[i] = mbox_reg;
sys/dev/drm/i915/intel_ringbuffer.c
2172
struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2175
engine->irq_enable = gen6_irq_enable;
sys/dev/drm/i915/intel_ringbuffer.c
2176
engine->irq_disable = gen6_irq_disable;
sys/dev/drm/i915/intel_ringbuffer.c
2177
engine->irq_seqno_barrier = gen6_seqno_barrier;
sys/dev/drm/i915/intel_ringbuffer.c
2179
engine->irq_enable = gen5_irq_enable;
sys/dev/drm/i915/intel_ringbuffer.c
2180
engine->irq_disable = gen5_irq_disable;
sys/dev/drm/i915/intel_ringbuffer.c
2181
engine->irq_seqno_barrier = gen5_seqno_barrier;
sys/dev/drm/i915/intel_ringbuffer.c
2183
engine->irq_enable = i9xx_irq_enable;
sys/dev/drm/i915/intel_ringbuffer.c
2184
engine->irq_disable = i9xx_irq_disable;
sys/dev/drm/i915/intel_ringbuffer.c
2186
engine->irq_enable = i8xx_irq_enable;
sys/dev/drm/i915/intel_ringbuffer.c
2187
engine->irq_disable = i8xx_irq_disable;
sys/dev/drm/i915/intel_ringbuffer.c
2191
static void i9xx_set_default_submission(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2193
engine->submit_request = i9xx_submit_request;
sys/dev/drm/i915/intel_ringbuffer.c
2194
engine->cancel_requests = cancel_requests;
sys/dev/drm/i915/intel_ringbuffer.c
2196
engine->park = NULL;
sys/dev/drm/i915/intel_ringbuffer.c
2197
engine->unpark = NULL;
sys/dev/drm/i915/intel_ringbuffer.c
2200
static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2202
i9xx_set_default_submission(engine);
sys/dev/drm/i915/intel_ringbuffer.c
2203
engine->submit_request = gen6_bsd_submit_request;
sys/dev/drm/i915/intel_ringbuffer.c
2207
struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2212
intel_ring_init_irq(dev_priv, engine);
sys/dev/drm/i915/intel_ringbuffer.c
2213
intel_ring_init_semaphores(dev_priv, engine);
sys/dev/drm/i915/intel_ringbuffer.c
2215
engine->init_hw = init_ring_common;
sys/dev/drm/i915/intel_ringbuffer.c
2216
engine->reset.prepare = reset_prepare;
sys/dev/drm/i915/intel_ringbuffer.c
2217
engine->reset.reset = reset_ring;
sys/dev/drm/i915/intel_ringbuffer.c
2218
engine->reset.finish = reset_finish;
sys/dev/drm/i915/intel_ringbuffer.c
2220
engine->context_pin = intel_ring_context_pin;
sys/dev/drm/i915/intel_ringbuffer.c
2221
engine->request_alloc = ring_request_alloc;
sys/dev/drm/i915/intel_ringbuffer.c
2223
engine->emit_breadcrumb = i9xx_emit_breadcrumb;
sys/dev/drm/i915/intel_ringbuffer.c
2224
engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
sys/dev/drm/i915/intel_ringbuffer.c
2228
engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
sys/dev/drm/i915/intel_ringbuffer.c
2231
engine->emit_breadcrumb_sz += num_rings * 3;
sys/dev/drm/i915/intel_ringbuffer.c
2233
engine->emit_breadcrumb_sz++;
sys/dev/drm/i915/intel_ringbuffer.c
2236
engine->set_default_submission = i9xx_set_default_submission;
sys/dev/drm/i915/intel_ringbuffer.c
2239
engine->emit_bb_start = gen6_emit_bb_start;
sys/dev/drm/i915/intel_ringbuffer.c
2241
engine->emit_bb_start = i965_emit_bb_start;
sys/dev/drm/i915/intel_ringbuffer.c
2243
engine->emit_bb_start = i830_emit_bb_start;
sys/dev/drm/i915/intel_ringbuffer.c
2245
engine->emit_bb_start = i915_emit_bb_start;
sys/dev/drm/i915/intel_ringbuffer.c
2248
int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2250
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
2253
intel_ring_default_vfuncs(dev_priv, engine);
sys/dev/drm/i915/intel_ringbuffer.c
2256
engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2258
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2261
engine->init_context = intel_rcs_ctx_init;
sys/dev/drm/i915/intel_ringbuffer.c
2262
engine->emit_flush = gen7_render_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2264
engine->emit_flush = gen6_render_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2266
engine->emit_flush = gen4_render_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2269
engine->emit_flush = gen2_render_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2271
engine->emit_flush = gen4_render_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2272
engine->irq_enable_mask = I915_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2276
engine->emit_bb_start = hsw_emit_bb_start;
sys/dev/drm/i915/intel_ringbuffer.c
2278
engine->init_hw = init_render_ring;
sys/dev/drm/i915/intel_ringbuffer.c
2280
ret = intel_init_ring_buffer(engine);
sys/dev/drm/i915/intel_ringbuffer.c
2287
int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2289
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
2291
intel_ring_default_vfuncs(dev_priv, engine);
sys/dev/drm/i915/intel_ringbuffer.c
2296
engine->set_default_submission = gen6_bsd_set_default_submission;
sys/dev/drm/i915/intel_ringbuffer.c
2297
engine->emit_flush = gen6_bsd_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2298
engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2300
engine->emit_flush = bsd_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2302
engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2304
engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2307
return intel_init_ring_buffer(engine);
sys/dev/drm/i915/intel_ringbuffer.c
2310
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2312
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
2314
intel_ring_default_vfuncs(dev_priv, engine);
sys/dev/drm/i915/intel_ringbuffer.c
2316
engine->emit_flush = gen6_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2317
engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2319
return intel_init_ring_buffer(engine);
sys/dev/drm/i915/intel_ringbuffer.c
2322
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
2324
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
2326
intel_ring_default_vfuncs(dev_priv, engine);
sys/dev/drm/i915/intel_ringbuffer.c
2328
engine->emit_flush = gen6_ring_flush;
sys/dev/drm/i915/intel_ringbuffer.c
2329
engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
sys/dev/drm/i915/intel_ringbuffer.c
2330
engine->irq_enable = hsw_vebox_irq_enable;
sys/dev/drm/i915/intel_ringbuffer.c
2331
engine->irq_disable = hsw_vebox_irq_disable;
sys/dev/drm/i915/intel_ringbuffer.c
2333
return intel_init_ring_buffer(engine);
sys/dev/drm/i915/intel_ringbuffer.c
382
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
384
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
385
struct page *page = virt_to_page(engine->status_page.page_addr);
sys/dev/drm/i915/intel_ringbuffer.c
396
static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
398
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
405
switch (engine->id) {
sys/dev/drm/i915/intel_ringbuffer.c
411
GEM_BUG_ON(engine->id);
sys/dev/drm/i915/intel_ringbuffer.c
426
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
sys/dev/drm/i915/intel_ringbuffer.c
428
mmio = RING_HWS_PGA(engine->mmio_base);
sys/dev/drm/i915/intel_ringbuffer.c
438
if (engine->id == RCS)
sys/dev/drm/i915/intel_ringbuffer.c
441
I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
sys/dev/drm/i915/intel_ringbuffer.c
444
I915_WRITE(mmio, engine->status_page.ggtt_offset);
sys/dev/drm/i915/intel_ringbuffer.c
449
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
sys/dev/drm/i915/intel_ringbuffer.c
452
WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
sys/dev/drm/i915/intel_ringbuffer.c
461
engine->name);
sys/dev/drm/i915/intel_ringbuffer.c
465
static bool stop_ring(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
467
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
470
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
sys/dev/drm/i915/intel_ringbuffer.c
472
RING_MI_MODE(engine->mmio_base),
sys/dev/drm/i915/intel_ringbuffer.c
477
engine->name);
sys/dev/drm/i915/intel_ringbuffer.c
482
if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
sys/dev/drm/i915/intel_ringbuffer.c
487
I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
sys/dev/drm/i915/intel_ringbuffer.c
489
I915_WRITE_HEAD(engine, 0);
sys/dev/drm/i915/intel_ringbuffer.c
490
I915_WRITE_TAIL(engine, 0);
sys/dev/drm/i915/intel_ringbuffer.c
493
I915_WRITE_CTL(engine, 0);
sys/dev/drm/i915/intel_ringbuffer.c
495
return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
sys/dev/drm/i915/intel_ringbuffer.c
498
static int init_ring_common(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
500
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
501
struct intel_ring *ring = engine->buffer;
sys/dev/drm/i915/intel_ringbuffer.c
506
if (!stop_ring(engine)) {
sys/dev/drm/i915/intel_ringbuffer.c
510
engine->name,
sys/dev/drm/i915/intel_ringbuffer.c
511
I915_READ_CTL(engine),
sys/dev/drm/i915/intel_ringbuffer.c
512
I915_READ_HEAD(engine),
sys/dev/drm/i915/intel_ringbuffer.c
513
I915_READ_TAIL(engine),
sys/dev/drm/i915/intel_ringbuffer.c
514
I915_READ_START(engine));
sys/dev/drm/i915/intel_ringbuffer.c
516
if (!stop_ring(engine)) {
sys/dev/drm/i915/intel_ringbuffer.c
519
engine->name,
sys/dev/drm/i915/intel_ringbuffer.c
520
I915_READ_CTL(engine),
sys/dev/drm/i915/intel_ringbuffer.c
521
I915_READ_HEAD(engine),
sys/dev/drm/i915/intel_ringbuffer.c
522
I915_READ_TAIL(engine),
sys/dev/drm/i915/intel_ringbuffer.c
523
I915_READ_START(engine));
sys/dev/drm/i915/intel_ringbuffer.c
530
ring_setup_phys_status_page(engine);
sys/dev/drm/i915/intel_ringbuffer.c
532
intel_ring_setup_status_page(engine);
sys/dev/drm/i915/intel_ringbuffer.c
534
intel_engine_reset_breadcrumbs(engine);
sys/dev/drm/i915/intel_ringbuffer.c
537
I915_READ_HEAD(engine);
sys/dev/drm/i915/intel_ringbuffer.c
543
I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
sys/dev/drm/i915/intel_ringbuffer.c
546
if (I915_READ_HEAD(engine))
sys/dev/drm/i915/intel_ringbuffer.c
548
engine->name, I915_READ_HEAD(engine));
sys/dev/drm/i915/intel_ringbuffer.c
555
I915_WRITE_HEAD(engine, ring->head);
sys/dev/drm/i915/intel_ringbuffer.c
556
I915_WRITE_TAIL(engine, ring->tail);
sys/dev/drm/i915/intel_ringbuffer.c
557
(void)I915_READ_TAIL(engine);
sys/dev/drm/i915/intel_ringbuffer.c
559
I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
sys/dev/drm/i915/intel_ringbuffer.c
562
if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
sys/dev/drm/i915/intel_ringbuffer.c
567
engine->name,
sys/dev/drm/i915/intel_ringbuffer.c
568
I915_READ_CTL(engine),
sys/dev/drm/i915/intel_ringbuffer.c
569
I915_READ_CTL(engine) & RING_VALID,
sys/dev/drm/i915/intel_ringbuffer.c
570
I915_READ_HEAD(engine), ring->head,
sys/dev/drm/i915/intel_ringbuffer.c
571
I915_READ_TAIL(engine), ring->tail,
sys/dev/drm/i915/intel_ringbuffer.c
572
I915_READ_START(engine),
sys/dev/drm/i915/intel_ringbuffer.c
579
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
sys/dev/drm/i915/intel_ringbuffer.c
582
intel_engine_wakeup(engine);
sys/dev/drm/i915/intel_ringbuffer.c
589
static struct i915_request *reset_prepare(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
591
intel_engine_stop_cs(engine);
sys/dev/drm/i915/intel_ringbuffer.c
593
if (engine->irq_seqno_barrier)
sys/dev/drm/i915/intel_ringbuffer.c
594
engine->irq_seqno_barrier(engine);
sys/dev/drm/i915/intel_ringbuffer.c
596
return i915_gem_find_active_request(engine);
sys/dev/drm/i915/intel_ringbuffer.c
613
static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq)
sys/dev/drm/i915/intel_ringbuffer.c
615
GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0);
sys/dev/drm/i915/intel_ringbuffer.c
639
static void reset_finish(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
658
static int init_render_ring(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
660
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
661
int ret = init_ring_common(engine);
sys/dev/drm/i915/intel_ringbuffer.c
665
intel_whitelist_workarounds_apply(engine);
sys/dev/drm/i915/intel_ringbuffer.c
706
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
sys/dev/drm/i915/intel_ringbuffer.c
714
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_ringbuffer.c
718
for_each_engine(engine, dev_priv, id) {
sys/dev/drm/i915/intel_ringbuffer.c
721
if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
sys/dev/drm/i915/intel_ringbuffer.c
724
mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
sys/dev/drm/i915/intel_ringbuffer.c
738
static void cancel_requests(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
743
spin_lock_irqsave(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_ringbuffer.c
746
list_for_each_entry(request, &engine->timeline.requests, link) {
sys/dev/drm/i915/intel_ringbuffer.c
753
spin_unlock_irqrestore(&engine->timeline.lock, flags);
sys/dev/drm/i915/intel_ringbuffer.c
763
I915_WRITE_TAIL(request->engine,
sys/dev/drm/i915/intel_ringbuffer.c
782
return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
sys/dev/drm/i915/intel_ringbuffer.c
791
u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
sys/dev/drm/i915/intel_ringbuffer.c
814
gen5_seqno_barrier(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
832
gen6_seqno_barrier(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
834
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
852
POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
sys/dev/drm/i915/intel_ringbuffer.c
857
gen5_irq_enable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
859
gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.c
863
gen5_irq_disable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
865
gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.c
869
i9xx_irq_enable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
871
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
873
dev_priv->irq_mask &= ~engine->irq_enable_mask;
sys/dev/drm/i915/intel_ringbuffer.c
875
POSTING_READ_FW(RING_IMR(engine->mmio_base));
sys/dev/drm/i915/intel_ringbuffer.c
879
i9xx_irq_disable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
881
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
883
dev_priv->irq_mask |= engine->irq_enable_mask;
sys/dev/drm/i915/intel_ringbuffer.c
888
i8xx_irq_enable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
890
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
892
dev_priv->irq_mask &= ~engine->irq_enable_mask;
sys/dev/drm/i915/intel_ringbuffer.c
894
POSTING_READ16(RING_IMR(engine->mmio_base));
sys/dev/drm/i915/intel_ringbuffer.c
898
i8xx_irq_disable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
900
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
902
dev_priv->irq_mask |= engine->irq_enable_mask;
sys/dev/drm/i915/intel_ringbuffer.c
922
gen6_irq_enable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
924
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
926
I915_WRITE_IMR(engine,
sys/dev/drm/i915/intel_ringbuffer.c
927
~(engine->irq_enable_mask |
sys/dev/drm/i915/intel_ringbuffer.c
928
engine->irq_keep_mask));
sys/dev/drm/i915/intel_ringbuffer.c
929
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.c
933
gen6_irq_disable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
935
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
937
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
sys/dev/drm/i915/intel_ringbuffer.c
938
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.c
942
hsw_vebox_irq_enable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
944
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
946
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.c
947
gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.c
951
hsw_vebox_irq_disable(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.c
953
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_ringbuffer.c
955
I915_WRITE_IMR(engine, ~0);
sys/dev/drm/i915/intel_ringbuffer.c
956
gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
sys/dev/drm/i915/intel_ringbuffer.h
1024
bool intel_engine_add_wait(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
1026
void intel_engine_remove_wait(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
1031
static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
1033
return READ_ONCE(engine->breadcrumbs.irq_wait);
sys/dev/drm/i915/intel_ringbuffer.h
1036
unsigned int intel_engine_wakeup(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1040
void intel_engine_pin_breadcrumbs_irq(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1041
void intel_engine_unpin_breadcrumbs_irq(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1043
void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1044
void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1046
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1047
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1100
bool intel_engine_is_idle(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1103
bool intel_engine_has_kernel_context(const struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1104
void intel_engine_lost_context(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1112
bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1115
void intel_engine_dump(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
1122
static inline void intel_engine_context_in(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
1126
if (READ_ONCE(engine->stats.enabled) == 0)
sys/dev/drm/i915/intel_ringbuffer.h
1129
write_seqlock_irqsave(&engine->stats.lock, flags);
sys/dev/drm/i915/intel_ringbuffer.h
1131
if (engine->stats.enabled > 0) {
sys/dev/drm/i915/intel_ringbuffer.h
1132
if (engine->stats.active++ == 0)
sys/dev/drm/i915/intel_ringbuffer.h
1133
engine->stats.start = ktime_get();
sys/dev/drm/i915/intel_ringbuffer.h
1134
GEM_BUG_ON(engine->stats.active == 0);
sys/dev/drm/i915/intel_ringbuffer.h
1137
write_sequnlock_irqrestore(&engine->stats.lock, flags);
sys/dev/drm/i915/intel_ringbuffer.h
1140
static inline void intel_engine_context_out(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
1144
if (READ_ONCE(engine->stats.enabled) == 0)
sys/dev/drm/i915/intel_ringbuffer.h
1147
write_seqlock_irqsave(&engine->stats.lock, flags);
sys/dev/drm/i915/intel_ringbuffer.h
1149
if (engine->stats.enabled > 0) {
sys/dev/drm/i915/intel_ringbuffer.h
1152
if (engine->stats.active && --engine->stats.active == 0) {
sys/dev/drm/i915/intel_ringbuffer.h
1157
last = ktime_sub(ktime_get(), engine->stats.start);
sys/dev/drm/i915/intel_ringbuffer.h
1159
engine->stats.total = ktime_add(engine->stats.total,
sys/dev/drm/i915/intel_ringbuffer.h
1161
} else if (engine->stats.active == 0) {
sys/dev/drm/i915/intel_ringbuffer.h
1167
last = ktime_sub(ktime_get(), engine->stats.enabled_at);
sys/dev/drm/i915/intel_ringbuffer.h
1169
engine->stats.total = ktime_add(engine->stats.total,
sys/dev/drm/i915/intel_ringbuffer.h
1174
write_sequnlock_irqrestore(&engine->stats.lock, flags);
sys/dev/drm/i915/intel_ringbuffer.h
1177
int intel_enable_engine_stats(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1178
void intel_disable_engine_stats(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
1180
ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
38
#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
39
#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val)
sys/dev/drm/i915/intel_ringbuffer.h
41
#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
42
#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val)
sys/dev/drm/i915/intel_ringbuffer.h
44
#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
447
void (*irq_enable)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
448
void (*irq_disable)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
45
#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val)
sys/dev/drm/i915/intel_ringbuffer.h
450
int (*init_hw)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
453
struct i915_request *(*prepare)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
454
void (*reset)(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
456
void (*finish)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
459
void (*park)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
460
void (*unpark)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
462
void (*set_default_submission)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
464
struct intel_context *(*context_pin)(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
47
#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
48
#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val)
sys/dev/drm/i915/intel_ringbuffer.h
50
#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
505
void (*cancel_requests)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
51
#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val)
sys/dev/drm/i915/intel_ringbuffer.h
513
void (*irq_seqno_barrier)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
514
void (*cleanup)(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
53
#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base))
sys/dev/drm/i915/intel_ringbuffer.h
54
#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val)
sys/dev/drm/i915/intel_ringbuffer.h
651
intel_engine_needs_cmd_parser(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
653
return engine->flags & I915_ENGINE_NEEDS_CMD_PARSER;
sys/dev/drm/i915/intel_ringbuffer.h
657
intel_engine_supports_stats(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
659
return engine->flags & I915_ENGINE_SUPPORTS_STATS;
sys/dev/drm/i915/intel_ringbuffer.h
663
intel_engine_has_preemption(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
665
return engine->flags & I915_ENGINE_HAS_PREEMPTION;
sys/dev/drm/i915/intel_ringbuffer.h
739
intel_engine_flag(const struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
741
return BIT(engine->id);
sys/dev/drm/i915/intel_ringbuffer.h
745
intel_read_status_page(const struct intel_engine_cs *engine, int reg)
sys/dev/drm/i915/intel_ringbuffer.h
748
return READ_ONCE(engine->status_page.page_addr[reg]);
sys/dev/drm/i915/intel_ringbuffer.h
752
intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
sys/dev/drm/i915/intel_ringbuffer.h
761
linux_clflush(&engine->status_page.page_addr[reg]);
sys/dev/drm/i915/intel_ringbuffer.h
762
engine->status_page.page_addr[reg] = value;
sys/dev/drm/i915/intel_ringbuffer.h
763
linux_clflush(&engine->status_page.page_addr[reg]);
sys/dev/drm/i915/intel_ringbuffer.h
766
WRITE_ONCE(engine->status_page.page_addr[reg], value);
sys/dev/drm/i915/intel_ringbuffer.h
798
intel_engine_create_ring(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
807
void intel_engine_stop(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
808
void intel_engine_cleanup(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
895
void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
sys/dev/drm/i915/intel_ringbuffer.h
897
void intel_engine_setup_common(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
898
int intel_engine_init_common(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
899
void intel_engine_cleanup_common(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
901
int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
902
int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
903
int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
904
int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
906
int intel_engine_stop_cs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
907
void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
909
u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
910
u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_ringbuffer.h
912
static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
922
return READ_ONCE(engine->timeline.seqno);
sys/dev/drm/i915/intel_ringbuffer.h
925
static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
927
return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
sys/dev/drm/i915/intel_ringbuffer.h
930
static inline bool intel_engine_signaled(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
933
return i915_seqno_passed(intel_engine_get_seqno(engine), seqno);
sys/dev/drm/i915/intel_ringbuffer.h
936
static inline bool intel_engine_has_completed(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
940
return intel_engine_signaled(engine, seqno);
sys/dev/drm/i915/intel_ringbuffer.h
943
static inline bool intel_engine_has_started(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
947
return intel_engine_signaled(engine, seqno - 1);
sys/dev/drm/i915/intel_ringbuffer.h
950
void intel_engine_get_instdone(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_ringbuffer.h
962
static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
964
return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR;
sys/dev/drm/i915/intel_ringbuffer.h
967
static inline u32 intel_hws_preempt_done_address(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_ringbuffer.h
969
return engine->status_page.ggtt_offset + I915_GEM_HWS_PREEMPT_ADDR;
sys/dev/drm/i915/intel_ringbuffer.h
973
int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_uncore.c
1717
static void gen3_stop_engine(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_uncore.c
1719
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_uncore.c
1720
const u32 base = engine->mmio_base;
sys/dev/drm/i915/intel_uncore.c
1722
if (intel_engine_stop_cs(engine))
sys/dev/drm/i915/intel_uncore.c
1723
DRM_DEBUG_DRIVER("%s: timed out on STOP_RING\n", engine->name);
sys/dev/drm/i915/intel_uncore.c
1738
engine->name);
sys/dev/drm/i915/intel_uncore.c
1744
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_uncore.c
1750
for_each_engine_masked(engine, dev_priv, engine_mask, id)
sys/dev/drm/i915/intel_uncore.c
1751
gen3_stop_engine(engine);
sys/dev/drm/i915/intel_uncore.c
1911
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_uncore.c
1927
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
sys/dev/drm/i915/intel_uncore.c
1928
hw_mask |= hw_engine_mask[engine->id];
sys/dev/drm/i915/intel_uncore.c
1950
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_uncore.c
1971
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
sys/dev/drm/i915/intel_uncore.c
1972
hw_mask |= hw_engine_mask[engine->id];
sys/dev/drm/i915/intel_uncore.c
2088
static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_uncore.c
2090
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_uncore.c
2093
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
sys/dev/drm/i915/intel_uncore.c
2097
RING_RESET_CTL(engine->mmio_base),
sys/dev/drm/i915/intel_uncore.c
2103
DRM_ERROR("%s: reset request timeout\n", engine->name);
sys/dev/drm/i915/intel_uncore.c
2108
static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_uncore.c
2110
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_uncore.c
2112
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
sys/dev/drm/i915/intel_uncore.c
2130
struct intel_engine_cs *engine;
sys/dev/drm/i915/intel_uncore.c
2135
for_each_engine_masked(engine, dev_priv, engine_mask, tmp) {
sys/dev/drm/i915/intel_uncore.c
2136
ret = gen8_engine_reset_prepare(engine);
sys/dev/drm/i915/intel_uncore.c
2158
for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
sys/dev/drm/i915/intel_uncore.c
2159
gen8_engine_reset_cancel(engine);
sys/dev/drm/i915/intel_workarounds.c
1063
static struct whitelist *whitelist_build(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_workarounds.c
1066
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_workarounds.c
1068
GEM_BUG_ON(engine->id != RCS);
sys/dev/drm/i915/intel_workarounds.c
1071
w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base));
sys/dev/drm/i915/intel_workarounds.c
1099
static void whitelist_apply(struct intel_engine_cs *engine,
sys/dev/drm/i915/intel_workarounds.c
1102
struct drm_i915_private *dev_priv = engine->i915;
sys/dev/drm/i915/intel_workarounds.c
1103
const u32 base = engine->mmio_base;
sys/dev/drm/i915/intel_workarounds.c
1109
intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL);
sys/dev/drm/i915/intel_workarounds.c
1119
intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
sys/dev/drm/i915/intel_workarounds.c
1122
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_workarounds.c
1126
whitelist_apply(engine, whitelist_build(engine, &w));
sys/dev/drm/i915/intel_workarounds.c
1129
static void rcs_engine_wa_init(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_workarounds.c
1131
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_workarounds.c
1132
struct i915_wa_list *wal = &engine->wa_list;
sys/dev/drm/i915/intel_workarounds.c
1234
static void xcs_engine_wa_init(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_workarounds.c
1236
struct drm_i915_private *i915 = engine->i915;
sys/dev/drm/i915/intel_workarounds.c
1237
struct i915_wa_list *wal = &engine->wa_list;
sys/dev/drm/i915/intel_workarounds.c
1242
RING_SEMA_WAIT_POLL(engine->mmio_base),
sys/dev/drm/i915/intel_workarounds.c
1247
void intel_engine_init_workarounds(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_workarounds.c
1249
struct i915_wa_list *wal = &engine->wa_list;
sys/dev/drm/i915/intel_workarounds.c
1251
if (GEM_WARN_ON(INTEL_GEN(engine->i915) < 8))
sys/dev/drm/i915/intel_workarounds.c
1254
wa_init_start(wal, engine->name);
sys/dev/drm/i915/intel_workarounds.c
1256
if (engine->id == RCS)
sys/dev/drm/i915/intel_workarounds.c
1257
rcs_engine_wa_init(engine);
sys/dev/drm/i915/intel_workarounds.c
1259
xcs_engine_wa_init(engine);
sys/dev/drm/i915/intel_workarounds.c
1264
void intel_engine_apply_workarounds(struct intel_engine_cs *engine)
sys/dev/drm/i915/intel_workarounds.c
1266
wa_list_apply(engine->i915, &engine->wa_list);
sys/dev/drm/i915/intel_workarounds.c
573
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
sys/dev/drm/i915/intel_workarounds.c
590
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
sys/dev/drm/i915/intel_workarounds.h
36
void intel_whitelist_workarounds_apply(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_workarounds.h
38
void intel_engine_init_workarounds(struct intel_engine_cs *engine);
sys/dev/drm/i915/intel_workarounds.h
39
void intel_engine_apply_workarounds(struct intel_engine_cs *engine);
