drm_dp_dpcd_write
drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
wret = drm_dp_dpcd_write(
return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,
res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);
EXPORT_SYMBOL(drm_dp_dpcd_write);
err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
ret = drm_dp_dpcd_write(
ret = drm_dp_dpcd_write(mgr->aux, regbase + offset,
ret = drm_dp_dpcd_write(mgr->aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3);
wret = drm_dp_dpcd_write(&intel_dp->aux,
dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
return drm_dp_dpcd_write(aux, offset, &value, 1);
drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,