bin/ls/ls.c

474

display(NULL, chp);

bin/ls/ls.c

516

display(p, chp);

bin/ls/ls.c

84

static void display(const FTSENT *, FTSENT *);

bin/mined/mined.h

300

void display(int x_coord, int y_coord, LINE *line, int count);

bin/mined/mined1.c

1404

display (0, 0, header->next, last_y);

bin/mined/mined1.c

1549

display(0, 0, top_line, last_y);

bin/mined/mined2.c

564

display(0, y, cur_line, last_y - y);

bin/mined/mined2.c

772

display(0, y, start_line, shift - y);

bin/mined/mined2.c

866

display(0, y, cur_line, screenmax - y);

crypto/openssh/channels.c

5127

is_path_to_xsocket(const char *display, char *path, size_t pathlen)

crypto/openssh/channels.c

5131

if (strlcpy(path, display, pathlen) >= pathlen) {

crypto/openssh/channels.c

5135

if (display[0] != '/')

crypto/openssh/channels.c

5156

const char *display;

crypto/openssh/channels.c

5163

display = getenv("DISPLAY");

crypto/openssh/channels.c

5164

if (!display) {

crypto/openssh/channels.c

5178

if (is_path_to_xsocket(display, path, sizeof(path))) {

crypto/openssh/channels.c

5195

if (strncmp(display, "unix:", 5) == 0 ||

crypto/openssh/channels.c

5196

display[0] == ':') {

crypto/openssh/channels.c

5198

if (sscanf(strrchr(display, ':') + 1, "%u",

crypto/openssh/channels.c

5201

"%.100s", display);

crypto/openssh/channels.c

5216

strlcpy(buf, display, sizeof(buf));

crypto/openssh/channels.c

5219

error("Could not find ':' in DISPLAY: %.100s", display);

crypto/openssh/channels.c

5229

display);

crypto/openssh/clientloop.c

268

client_x11_display_valid(const char *display)

crypto/openssh/clientloop.c

272

if (display == NULL)

crypto/openssh/clientloop.c

275

dlen = strlen(display);

crypto/openssh/clientloop.c

277

if (!isalnum((u_char)display[i]) &&

crypto/openssh/clientloop.c

278

strchr(SSH_X11_VALID_DISPLAY_CHARS, display[i]) == NULL) {

crypto/openssh/clientloop.c

279

debug("Invalid character '%c' in DISPLAY", display[i]);

crypto/openssh/clientloop.c

289

client_x11_get_proto(struct ssh *ssh, const char *display,

crypto/openssh/clientloop.c

305

if (!client_x11_display_valid(display)) {

crypto/openssh/clientloop.c

306

if (display != NULL)

crypto/openssh/clientloop.c

308

display);

crypto/openssh/clientloop.c

324

if (strncmp(display, "localhost:", 10) == 0) {

crypto/openssh/clientloop.c

326

display + 10)) < 0 ||

crypto/openssh/clientloop.c

331

display = xdisplay;

crypto/openssh/clientloop.c

359

xauth_path, xauthfile, display,

crypto/openssh/clientloop.c

372

xauth_path, xauthfile, display,

crypto/openssh/clientloop.c

403

display);

crypto/openssh/mux.c

1359

const char *display;

crypto/openssh/mux.c

1381

display = getenv("DISPLAY");

crypto/openssh/mux.c

1382

if (cctx->want_x_fwd && options.forward_x11 && display != NULL) {

crypto/openssh/mux.c

1386

if (client_x11_get_proto(ssh, display, options.xauth_location,

crypto/openssh/mux.c

1393

display, proto, data, 1);

crypto/openssh/session.c

1055

if (s->display)

crypto/openssh/session.c

1056

child_set_env(&env, &envsize, "DISPLAY", s->display);

crypto/openssh/session.c

1198

s->display != NULL && s->auth_proto != NULL && s->auth_data != NULL;

crypto/openssh/session.c

2354

free(s->display);

crypto/openssh/session.c

2355

s->display = NULL;

crypto/openssh/session.c

2437

free(s->display);

crypto/openssh/session.c

2567

char display[512], auth_display[512];

crypto/openssh/session.c

2584

if (s->display != NULL) {

crypto/openssh/session.c

2608

snprintf(display, sizeof display, "localhost:%u.%u",

crypto/openssh/session.c

2612

s->display = xstrdup(display);

crypto/openssh/session.c

2626

snprintf(display, sizeof display, "%.50s:%u.%u", inet_ntoa(my_addr),

crypto/openssh/session.c

2629

snprintf(display, sizeof display, "%.400s:%u.%u", hostname,

crypto/openssh/session.c

2632

s->display = xstrdup(display);

crypto/openssh/session.c

2633

s->auth_display = xstrdup(display);

crypto/openssh/session.c

528

ssh_packet_set_interactive(ssh, s->display != NULL,

crypto/openssh/session.h

48

char *display;

crypto/openssh/ssh.c

2119

const char *display, *term;

crypto/openssh/ssh.c

2126

display = getenv("DISPLAY");

crypto/openssh/ssh.c

2127

if (display == NULL && options.forward_x11)

crypto/openssh/ssh.c

2129

if (options.forward_x11 && client_x11_get_proto(ssh, display,

crypto/openssh/ssh.c

2135

x11_request_forwarding_with_spoofing(ssh, id, display, proto,

games/fortune/fortune/fortune.c

124

static void display(FILEDESC *);

games/fortune/fortune/fortune.c

180

display(Fortfile);

games/worm/worm.c

143

display(head, HEAD);

games/worm/worm.c

150

display(np, BODY);

games/worm/worm.c

234

display(tail, ' ');

games/worm/worm.c

241

display(head, BODY);

games/worm/worm.c

260

display(nh, HEAD);

games/worm/worm.c

70

static void display(struct body *, char);

libexec/rpc.rusersd/rusers_proc.c

107

getidle(const char *tty, const char *display __unused)

libexec/rpc.rusersd/rusers_proc.c

119

if (display && *display && (idle = XqueryIdle(display)) >= 0)

libexec/rpc.rusersd/rusers_proc.c

72

XqueryIdle(char *display)

libexec/rpc.rusersd/rusers_proc.c

80

if (!(dpy= XOpenDisplay(display))) {

libexec/rpc.rusersd/rusers_proc.c

81

syslog(LOG_ERR, "Cannot open display %s", display);

libexec/rpc.rusersd/rusers_proc.c

86

syslog(LOG_ERR, "%s: unable to get idle time", display);

libexec/rpc.rusersd/rusers_proc.c

90

syslog(LOG_ERR, "%s: Xidle extension not loaded", display);

libexec/rpc.rusersd/rusers_proc.c

95

syslog(LOG_ERR, "%s: server grabbed for over 10 seconds", display);

sbin/disklabel32/disklabel.c

269

display(stdout, lp);

sbin/disklabel32/disklabel.c

375

display(stdout, lp);

sbin/disklabel32/disklabel.c

710

display(fp, lp);

sbin/disklabel32/disklabel.c

95

void display(FILE *, const struct disklabel32 *);

sbin/disklabel64/disklabel64.c

105

static void display(FILE *, const struct disklabel64 *);

sbin/disklabel64/disklabel64.c

273

display(stdout, lp);

sbin/disklabel64/disklabel64.c

391

display(stdout, lp);

sbin/disklabel64/disklabel64.c

760

display(fp, lp);

sys/dev/drm/amd/display/dc/dm_services.h

329

(struct dc_context *ctx, enum dm_acpi_display_type display,

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

709

ps->display.disableFrameModulation = false;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

719

ps->display.refreshrateSource = PP_RefreshrateSource_Explicit;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

720

ps->display.explicitRefreshrate = look_up[rrr_index];

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

721

ps->display.limitRefreshrate = true;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

723

if (ps->display.explicitRefreshrate == 0)

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

724

ps->display.limitRefreshrate = false;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

726

ps->display.limitRefreshrate = false;

sys/dev/drm/amd/powerplay/hwmgr/processpptables.c

731

ps->display.enableVariBright = (0 != tmp);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.h

109

uint32_t display : 1;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3152

power_state->display.disableFrameModulation = false;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3153

power_state->display.limitRefreshrate = false;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3154

power_state->display.enableVariBright =

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.h

132

uint32_t display : 1;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3013

power_state->display.disableFrameModulation = false;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3014

power_state->display.limitRefreshrate = false;

sys/dev/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

3015

power_state->display.enableVariBright =

sys/dev/drm/amd/powerplay/inc/power_state.h

151

struct PP_StateDisplayBlock display;

sys/dev/drm/drm_edid.c

4328

struct drm_display_info *display = &connector->display_info;

sys/dev/drm/drm_edid.c

4329

struct drm_hdmi_info *hdmi = &display->hdmi;

sys/dev/drm/drm_edid.c

4331

display->has_hdmi_infoframe = true;

sys/dev/drm/drm_edid.c

4354

display->max_tmds_clock = max_tmds_clock;

sys/dev/drm/drm_edid.c

4356

display->max_tmds_clock);

sys/dev/drm/drm_modes.c

1765

bool drm_mode_is_420_only(const struct drm_display_info *display,

sys/dev/drm/drm_modes.c

1770

return test_bit(vic, display->hdmi.y420_vdb_modes);

sys/dev/drm/drm_modes.c

1785

bool drm_mode_is_420_also(const struct drm_display_info *display,

sys/dev/drm/drm_modes.c

1790

return test_bit(vic, display->hdmi.y420_cmdb_modes);

sys/dev/drm/drm_modes.c

1804

bool drm_mode_is_420(const struct drm_display_info *display,

sys/dev/drm/drm_modes.c

1807

return drm_mode_is_420_only(display, mode) ||

sys/dev/drm/drm_modes.c

1808

drm_mode_is_420_also(display, mode);

sys/dev/drm/i915/gvt/gvt.h

163

struct intel_vgpu_display display;

sys/dev/drm/i915/i915_drv.c

2148

if (dev_priv->display.hpd_irq_setup)

sys/dev/drm/i915/i915_drv.c

2149

dev_priv->display.hpd_irq_setup(dev_priv);

sys/dev/drm/i915/i915_drv.h

1763

struct drm_i915_display_funcs display;

sys/dev/drm/i915/i915_gpu_error.c

1820

error->display = intel_display_capture_error_state(error->i915);

sys/dev/drm/i915/i915_gpu_error.c

837

if (error->display)

sys/dev/drm/i915/i915_gpu_error.c

838

intel_display_print_error_state(m, error->display);

sys/dev/drm/i915/i915_gpu_error.c

947

kfree(error->display);

sys/dev/drm/i915/i915_gpu_error.h

78

struct intel_display_error_state *display;

sys/dev/drm/i915/i915_irq.c

4853

dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4861

dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4869

dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4878

dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4881

dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4883

dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4891

dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;

sys/dev/drm/i915/i915_irq.c

4916

dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;

sys/dev/drm/i915/intel_audio.c

657

if (dev_priv->display.audio_codec_enable)

sys/dev/drm/i915/intel_audio.c

658

dev_priv->display.audio_codec_enable(encoder,

sys/dev/drm/i915/intel_audio.c

702

if (dev_priv->display.audio_codec_disable)

sys/dev/drm/i915/intel_audio.c

703

dev_priv->display.audio_codec_disable(encoder,

sys/dev/drm/i915/intel_audio.c

731

dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;

sys/dev/drm/i915/intel_audio.c

732

dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;

sys/dev/drm/i915/intel_audio.c

734

dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;

sys/dev/drm/i915/intel_audio.c

735

dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;

sys/dev/drm/i915/intel_audio.c

737

dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;

sys/dev/drm/i915/intel_audio.c

738

dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;

sys/dev/drm/i915/intel_audio.c

740

dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;

sys/dev/drm/i915/intel_audio.c

741

dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;

sys/dev/drm/i915/intel_cdclk.c

2124

if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))

sys/dev/drm/i915/intel_cdclk.c

2129

dev_priv->display.set_cdclk(dev_priv, cdclk_state);

sys/dev/drm/i915/intel_cdclk.c

2635

dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);

sys/dev/drm/i915/intel_cdclk.c

2767

dev_priv->display.set_cdclk = chv_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2768

dev_priv->display.modeset_calc_cdclk =

sys/dev/drm/i915/intel_cdclk.c

2771

dev_priv->display.set_cdclk = vlv_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2772

dev_priv->display.modeset_calc_cdclk =

sys/dev/drm/i915/intel_cdclk.c

2775

dev_priv->display.set_cdclk = bdw_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2776

dev_priv->display.modeset_calc_cdclk =

sys/dev/drm/i915/intel_cdclk.c

2779

dev_priv->display.set_cdclk = bxt_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2780

dev_priv->display.modeset_calc_cdclk =

sys/dev/drm/i915/intel_cdclk.c

2783

dev_priv->display.set_cdclk = skl_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2784

dev_priv->display.modeset_calc_cdclk =

sys/dev/drm/i915/intel_cdclk.c

2787

dev_priv->display.set_cdclk = cnl_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2788

dev_priv->display.modeset_calc_cdclk =

sys/dev/drm/i915/intel_cdclk.c

2791

dev_priv->display.set_cdclk = icl_set_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2792

dev_priv->display.modeset_calc_cdclk = icl_modeset_calc_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2796

dev_priv->display.get_cdclk = icl_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2798

dev_priv->display.get_cdclk = cnl_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2800

dev_priv->display.get_cdclk = skl_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2802

dev_priv->display.get_cdclk = bxt_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2804

dev_priv->display.get_cdclk = bdw_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2806

dev_priv->display.get_cdclk = hsw_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2808

dev_priv->display.get_cdclk = vlv_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2810

dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2812

dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2814

dev_priv->display.get_cdclk = gm45_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2816

dev_priv->display.get_cdclk = g33_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2818

dev_priv->display.get_cdclk = i965gm_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2820

dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2822

dev_priv->display.get_cdclk = pnv_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2824

dev_priv->display.get_cdclk = g33_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2826

dev_priv->display.get_cdclk = i945gm_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2828

dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2830

dev_priv->display.get_cdclk = i915gm_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2832

dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2834

dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2836

dev_priv->display.get_cdclk = i85x_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2838

dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;

sys/dev/drm/i915/intel_cdclk.c

2842

dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;

sys/dev/drm/i915/intel_color.c

308

if (dev_priv->display.load_csc_matrix)

sys/dev/drm/i915/intel_color.c

309

dev_priv->display.load_csc_matrix(crtc_state);

sys/dev/drm/i915/intel_color.c

613

dev_priv->display.load_luts(crtc_state);

sys/dev/drm/i915/intel_color.c

652

dev_priv->display.load_csc_matrix = cherryview_load_csc_matrix;

sys/dev/drm/i915/intel_color.c

653

dev_priv->display.load_luts = cherryview_load_luts;

sys/dev/drm/i915/intel_color.c

655

dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;

sys/dev/drm/i915/intel_color.c

656

dev_priv->display.load_luts = haswell_load_luts;

sys/dev/drm/i915/intel_color.c

659

dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;

sys/dev/drm/i915/intel_color.c

660

dev_priv->display.load_luts = broadwell_load_luts;

sys/dev/drm/i915/intel_color.c

662

dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;

sys/dev/drm/i915/intel_color.c

663

dev_priv->display.load_luts = glk_load_luts;

sys/dev/drm/i915/intel_color.c

665

dev_priv->display.load_luts = i9xx_load_luts;

sys/dev/drm/i915/intel_crt.c

272

dev_priv->display.fdi_link_train(crtc, crtc_state);

sys/dev/drm/i915/intel_display.c

10652

if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) {

sys/dev/drm/i915/intel_display.c

10870

dev_priv->display.crtc_compute_clock &&

sys/dev/drm/i915/intel_display.c

10872

ret = dev_priv->display.crtc_compute_clock(intel_crtc,

sys/dev/drm/i915/intel_display.c

10891

if (dev_priv->display.compute_pipe_wm) {

sys/dev/drm/i915/intel_display.c

10892

ret = dev_priv->display.compute_pipe_wm(pipe_config);

sys/dev/drm/i915/intel_display.c

10899

if (dev_priv->display.compute_intermediate_wm &&

sys/dev/drm/i915/intel_display.c

10901

if (WARN_ON(!dev_priv->display.compute_pipe_wm))

sys/dev/drm/i915/intel_display.c

10909

ret = dev_priv->display.compute_intermediate_wm(dev,

sys/dev/drm/i915/intel_display.c

10916

} else if (dev_priv->display.compute_intermediate_wm) {

sys/dev/drm/i915/intel_display.c

12049

active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);

sys/dev/drm/i915/intel_display.c

12280

if (!dev_priv->display.crtc_compute_clock)

sys/dev/drm/i915/intel_display.c

12449

if (dev_priv->display.modeset_calc_cdclk) {

sys/dev/drm/i915/intel_display.c

12450

ret = dev_priv->display.modeset_calc_cdclk(state);

sys/dev/drm/i915/intel_display.c

12503

if (dev_priv->display.compute_global_watermarks)

sys/dev/drm/i915/intel_display.c

12504

return dev_priv->display.compute_global_watermarks(state);

sys/dev/drm/i915/intel_display.c

12620

dev_priv->display.crtc_enable(pipe_config, state);

sys/dev/drm/i915/intel_display.c

12831

dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);

sys/dev/drm/i915/intel_display.c

12846

dev_priv->display.initial_watermarks)

sys/dev/drm/i915/intel_display.c

12847

dev_priv->display.initial_watermarks(intel_state,

sys/dev/drm/i915/intel_display.c

12886

dev_priv->display.update_crtcs(state);

sys/dev/drm/i915/intel_display.c

12909

if (dev_priv->display.optimize_watermarks)

sys/dev/drm/i915/intel_display.c

12910

dev_priv->display.optimize_watermarks(intel_state,

sys/dev/drm/i915/intel_display.c

13434

if (dev_priv->display.atomic_update_watermarks)

sys/dev/drm/i915/intel_display.c

13435

dev_priv->display.atomic_update_watermarks(old_intel_state,

sys/dev/drm/i915/intel_display.c

14893

dev_priv->display.get_pipe_config = haswell_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14894

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14896

dev_priv->display.crtc_compute_clock =

sys/dev/drm/i915/intel_display.c

14898

dev_priv->display.crtc_enable = haswell_crtc_enable;

sys/dev/drm/i915/intel_display.c

14899

dev_priv->display.crtc_disable = haswell_crtc_disable;

sys/dev/drm/i915/intel_display.c

14901

dev_priv->display.get_pipe_config = haswell_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14902

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14904

dev_priv->display.crtc_compute_clock =

sys/dev/drm/i915/intel_display.c

14906

dev_priv->display.crtc_enable = haswell_crtc_enable;

sys/dev/drm/i915/intel_display.c

14907

dev_priv->display.crtc_disable = haswell_crtc_disable;

sys/dev/drm/i915/intel_display.c

14909

dev_priv->display.get_pipe_config = ironlake_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14910

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14912

dev_priv->display.crtc_compute_clock =

sys/dev/drm/i915/intel_display.c

14914

dev_priv->display.crtc_enable = ironlake_crtc_enable;

sys/dev/drm/i915/intel_display.c

14915

dev_priv->display.crtc_disable = ironlake_crtc_disable;

sys/dev/drm/i915/intel_display.c

14917

dev_priv->display.get_pipe_config = i9xx_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14918

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14920

dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;

sys/dev/drm/i915/intel_display.c

14921

dev_priv->display.crtc_enable = valleyview_crtc_enable;

sys/dev/drm/i915/intel_display.c

14922

dev_priv->display.crtc_disable = i9xx_crtc_disable;

sys/dev/drm/i915/intel_display.c

14924

dev_priv->display.get_pipe_config = i9xx_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14925

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14927

dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;

sys/dev/drm/i915/intel_display.c

14928

dev_priv->display.crtc_enable = valleyview_crtc_enable;

sys/dev/drm/i915/intel_display.c

14929

dev_priv->display.crtc_disable = i9xx_crtc_disable;

sys/dev/drm/i915/intel_display.c

14931

dev_priv->display.get_pipe_config = i9xx_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14932

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14934

dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;

sys/dev/drm/i915/intel_display.c

14935

dev_priv->display.crtc_enable = i9xx_crtc_enable;

sys/dev/drm/i915/intel_display.c

14936

dev_priv->display.crtc_disable = i9xx_crtc_disable;

sys/dev/drm/i915/intel_display.c

14938

dev_priv->display.get_pipe_config = i9xx_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14939

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14941

dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;

sys/dev/drm/i915/intel_display.c

14942

dev_priv->display.crtc_enable = i9xx_crtc_enable;

sys/dev/drm/i915/intel_display.c

14943

dev_priv->display.crtc_disable = i9xx_crtc_disable;

sys/dev/drm/i915/intel_display.c

14945

dev_priv->display.get_pipe_config = i9xx_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14946

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14948

dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;

sys/dev/drm/i915/intel_display.c

14949

dev_priv->display.crtc_enable = i9xx_crtc_enable;

sys/dev/drm/i915/intel_display.c

14950

dev_priv->display.crtc_disable = i9xx_crtc_disable;

sys/dev/drm/i915/intel_display.c

14952

dev_priv->display.get_pipe_config = i9xx_get_pipe_config;

sys/dev/drm/i915/intel_display.c

14953

dev_priv->display.get_initial_plane_config =

sys/dev/drm/i915/intel_display.c

14955

dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;

sys/dev/drm/i915/intel_display.c

14956

dev_priv->display.crtc_enable = i9xx_crtc_enable;

sys/dev/drm/i915/intel_display.c

14957

dev_priv->display.crtc_disable = i9xx_crtc_disable;

sys/dev/drm/i915/intel_display.c

14961

dev_priv->display.fdi_link_train = ironlake_fdi_link_train;

sys/dev/drm/i915/intel_display.c

14963

dev_priv->display.fdi_link_train = gen6_fdi_link_train;

sys/dev/drm/i915/intel_display.c

14966

dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;

sys/dev/drm/i915/intel_display.c

14968

dev_priv->display.fdi_link_train = hsw_fdi_link_train;

sys/dev/drm/i915/intel_display.c

14972

dev_priv->display.update_crtcs = skl_update_crtcs;

sys/dev/drm/i915/intel_display.c

14974

dev_priv->display.update_crtcs = intel_update_crtcs;

sys/dev/drm/i915/intel_display.c

15195

if (!dev_priv->display.optimize_watermarks)

sys/dev/drm/i915/intel_display.c

15248

dev_priv->display.optimize_watermarks(intel_state, cs);

sys/dev/drm/i915/intel_display.c

15447

dev_priv->display.get_initial_plane_config(crtc,

sys/dev/drm/i915/intel_display.c

15850

dev_priv->display.get_pipe_config(crtc, crtc_state);

sys/dev/drm/i915/intel_display.c

15963

if (dev_priv->display.modeset_calc_cdclk) {

sys/dev/drm/i915/intel_display.c

3892

if (dev_priv->display.hpd_irq_setup)

sys/dev/drm/i915/intel_display.c

3893

dev_priv->display.hpd_irq_setup(dev_priv);

sys/dev/drm/i915/intel_display.c

4743

dev_priv->display.fdi_link_train(crtc, crtc_state);

sys/dev/drm/i915/intel_display.c

5476

if (dev_priv->display.initial_watermarks != NULL)

sys/dev/drm/i915/intel_display.c

5477

dev_priv->display.initial_watermarks(old_intel_state,

sys/dev/drm/i915/intel_display.c

5688

if (dev_priv->display.initial_watermarks != NULL)

sys/dev/drm/i915/intel_display.c

5689

dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);

sys/dev/drm/i915/intel_display.c

5837

if (dev_priv->display.initial_watermarks != NULL)

sys/dev/drm/i915/intel_display.c

5838

dev_priv->display.initial_watermarks(old_intel_state, pipe_config);

sys/dev/drm/i915/intel_display.c

6168

dev_priv->display.initial_watermarks(old_intel_state,

sys/dev/drm/i915/intel_display.c

6224

if (dev_priv->display.initial_watermarks != NULL)

sys/dev/drm/i915/intel_display.c

6225

dev_priv->display.initial_watermarks(old_intel_state,

sys/dev/drm/i915/intel_display.c

6293

if (!dev_priv->display.initial_watermarks)

sys/dev/drm/i915/intel_display.c

6340

dev_priv->display.crtc_disable(crtc_state, state);

sys/dev/drm/i915/intel_hotplug.c

244

if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup)

sys/dev/drm/i915/intel_hotplug.c

245

dev_priv->display.hpd_irq_setup(dev_priv);

sys/dev/drm/i915/intel_hotplug.c

487

dev_priv->display.hpd_irq_setup(dev_priv);

sys/dev/drm/i915/intel_hotplug.c

532

if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) {

sys/dev/drm/i915/intel_hotplug.c

535

dev_priv->display.hpd_irq_setup(dev_priv);

sys/dev/drm/i915/intel_pm.c

2279

fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);

sys/dev/drm/i915/intel_pm.c

2306

fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);

sys/dev/drm/i915/intel_pm.c

2419

dev_priv->display.get_fifo_size(dev_priv, PLANE_A),

sys/dev/drm/i915/intel_pm.c

6148

if (dev_priv->display.update_wm)

sys/dev/drm/i915/intel_pm.c

6149

dev_priv->display.update_wm(crtc);

sys/dev/drm/i915/intel_pm.c

9290

dev_priv->display.init_clock_gating(dev_priv);

sys/dev/drm/i915/intel_pm.c

9316

dev_priv->display.init_clock_gating = icl_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9318

dev_priv->display.init_clock_gating = cnl_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9320

dev_priv->display.init_clock_gating = cfl_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9322

dev_priv->display.init_clock_gating = skl_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9324

dev_priv->display.init_clock_gating = kbl_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9326

dev_priv->display.init_clock_gating = bxt_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9328

dev_priv->display.init_clock_gating = glk_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9330

dev_priv->display.init_clock_gating = bdw_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9332

dev_priv->display.init_clock_gating = chv_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9334

dev_priv->display.init_clock_gating = hsw_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9336

dev_priv->display.init_clock_gating = ivb_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9338

dev_priv->display.init_clock_gating = vlv_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9340

dev_priv->display.init_clock_gating = gen6_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9342

dev_priv->display.init_clock_gating = ilk_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9344

dev_priv->display.init_clock_gating = g4x_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9346

dev_priv->display.init_clock_gating = i965gm_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9348

dev_priv->display.init_clock_gating = i965g_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9350

dev_priv->display.init_clock_gating = gen3_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9352

dev_priv->display.init_clock_gating = i85x_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9354

dev_priv->display.init_clock_gating = i830_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9357

dev_priv->display.init_clock_gating = nop_init_clock_gating;

sys/dev/drm/i915/intel_pm.c

9375

dev_priv->display.initial_watermarks = skl_initial_wm;

sys/dev/drm/i915/intel_pm.c

9376

dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;

sys/dev/drm/i915/intel_pm.c

9377

dev_priv->display.compute_global_watermarks = skl_compute_wm;

sys/dev/drm/i915/intel_pm.c

9385

dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;

sys/dev/drm/i915/intel_pm.c

9386

dev_priv->display.compute_intermediate_wm =

sys/dev/drm/i915/intel_pm.c

9388

dev_priv->display.initial_watermarks =

sys/dev/drm/i915/intel_pm.c

9390

dev_priv->display.optimize_watermarks =

sys/dev/drm/i915/intel_pm.c

9398

dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm;

sys/dev/drm/i915/intel_pm.c

9399

dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm;

sys/dev/drm/i915/intel_pm.c

9400

dev_priv->display.initial_watermarks = vlv_initial_watermarks;

sys/dev/drm/i915/intel_pm.c

9401

dev_priv->display.optimize_watermarks = vlv_optimize_watermarks;

sys/dev/drm/i915/intel_pm.c

9402

dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo;

sys/dev/drm/i915/intel_pm.c

9405

dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm;

sys/dev/drm/i915/intel_pm.c

9406

dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm;

sys/dev/drm/i915/intel_pm.c

9407

dev_priv->display.initial_watermarks = g4x_initial_watermarks;

sys/dev/drm/i915/intel_pm.c

9408

dev_priv->display.optimize_watermarks = g4x_optimize_watermarks;

sys/dev/drm/i915/intel_pm.c

9421

dev_priv->display.update_wm = NULL;

sys/dev/drm/i915/intel_pm.c

9423

dev_priv->display.update_wm = pineview_update_wm;

sys/dev/drm/i915/intel_pm.c

9425

dev_priv->display.update_wm = i965_update_wm;

sys/dev/drm/i915/intel_pm.c

9427

dev_priv->display.update_wm = i9xx_update_wm;

sys/dev/drm/i915/intel_pm.c

9428

dev_priv->display.get_fifo_size = i9xx_get_fifo_size;

sys/dev/drm/i915/intel_pm.c

9431

dev_priv->display.update_wm = i845_update_wm;

sys/dev/drm/i915/intel_pm.c

9432

dev_priv->display.get_fifo_size = i845_get_fifo_size;

sys/dev/drm/i915/intel_pm.c

9434

dev_priv->display.update_wm = i9xx_update_wm;

sys/dev/drm/i915/intel_pm.c

9435

dev_priv->display.get_fifo_size = i830_get_fifo_size;

sys/dev/drm/i915/intel_runtime_pm.c

803

dev_priv->display.get_cdclk(dev_priv, &cdclk_state);

sys/dev/drm/include/drm/drm_modes.h

471

bool drm_mode_is_420_only(const struct drm_display_info *display,

sys/dev/drm/include/drm/drm_modes.h

473

bool drm_mode_is_420_also(const struct drm_display_info *display,

sys/dev/drm/include/drm/drm_modes.h

475

bool drm_mode_is_420(const struct drm_display_info *display,

sys/dev/drm/radeon/atombios_encoders.c

2657

if (rdev->asic->display.hdmi_enable)

sys/dev/drm/radeon/radeon.h

1919

} display;

sys/dev/drm/radeon/radeon.h

2750

#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))

sys/dev/drm/radeon/radeon.h

2751

#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))

sys/dev/drm/radeon/radeon.h

2752

#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))

sys/dev/drm/radeon/radeon.h

2753

#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))

sys/dev/drm/radeon/radeon.h

2754

#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))

sys/dev/drm/radeon/radeon.h

2775

#define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev))

sys/dev/drm/radeon/radeon.h

2788

#define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc))

sys/dev/drm/radeon/radeon_asic.c

1044

.display = {

sys/dev/drm/radeon/radeon_asic.c

1137

.display = {

sys/dev/drm/radeon/radeon_asic.c

1243

.display = {

sys/dev/drm/radeon/radeon_asic.c

1363

.display = {

sys/dev/drm/radeon/radeon_asic.c

1457

.display = {

sys/dev/drm/radeon/radeon_asic.c

1550

.display = {

sys/dev/drm/radeon/radeon_asic.c

1698

.display = {

sys/dev/drm/radeon/radeon_asic.c

1818

.display = {

sys/dev/drm/radeon/radeon_asic.c

1956

.display = {

sys/dev/drm/radeon/radeon_asic.c

2126

.display = {

sys/dev/drm/radeon/radeon_asic.c

221

.display = {

sys/dev/drm/radeon/radeon_asic.c

2239

.display = {

sys/dev/drm/radeon/radeon_asic.c

2364

rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;

sys/dev/drm/radeon/radeon_asic.c

289

.display = {

sys/dev/drm/radeon/radeon_asic.c

385

.display = {

sys/dev/drm/radeon/radeon_asic.c

453

.display = {

sys/dev/drm/radeon/radeon_asic.c

521

.display = {

sys/dev/drm/radeon/radeon_asic.c

589

.display = {

sys/dev/drm/radeon/radeon_asic.c

657

.display = {

sys/dev/drm/radeon/radeon_asic.c

725

.display = {

sys/dev/drm/radeon/radeon_asic.c

793

.display = {

sys/dev/drm/radeon/radeon_asic.c

861

.display = {

sys/dev/drm/radeon/radeon_asic.c

958

.display = {

sys/dev/netif/ix/if_ix.c

3280

goto display;

sys/dev/netif/ix/if_ix.c

3308

goto display;

sys/dev/netif/ix/if_ix.c

3314

display:

usr.bin/chpass/edit.c

59

static int display(const char *tfn, struct passwd *pw);

usr.bin/chpass/edit.c

69

if (display(tfn, pw) == -1)

usr.bin/hexdump/hexdump.c

71

display();

usr.bin/hexdump/hexdump.h

89

void display(void);

usr.bin/ipcs/ipcs.c

130

int display = SHMINFO | MSGINFO | SEMINFO;

usr.bin/ipcs/ipcs.c

144

display = SHMTOTAL;

usr.bin/ipcs/ipcs.c

147

display = SHMINFO;

usr.bin/ipcs/ipcs.c

150

display = MSGTOTAL;

usr.bin/ipcs/ipcs.c

153

display = MSGINFO;

usr.bin/ipcs/ipcs.c

156

display = SEMTOTAL;

usr.bin/ipcs/ipcs.c

159

display = SEMINFO;

usr.bin/ipcs/ipcs.c

162

display = SHMTOTAL | MSGTOTAL | SEMTOTAL;

usr.bin/ipcs/ipcs.c

228

if ((display & (MSGINFO | MSGTOTAL)) &&

usr.bin/ipcs/ipcs.c

231

if (display & MSGTOTAL) {

usr.bin/ipcs/ipcs.c

246

if (display & MSGINFO) {

usr.bin/ipcs/ipcs.c

319

if (display & (MSGINFO | MSGTOTAL)) {

usr.bin/ipcs/ipcs.c

323

if ((display & (SHMINFO | SHMTOTAL)) &&

usr.bin/ipcs/ipcs.c

325

if (display & SHMTOTAL) {

usr.bin/ipcs/ipcs.c

338

if (display & SHMINFO) {

usr.bin/ipcs/ipcs.c

412

if (display & (SHMINFO | SHMTOTAL)) {

usr.bin/ipcs/ipcs.c

416

if ((display & (SEMINFO | SEMTOTAL)) &&

usr.bin/ipcs/ipcs.c

420

if (display & SEMTOTAL) {

usr.bin/ipcs/ipcs.c

443

if (display & SEMINFO) {

usr.bin/ipcs/ipcs.c

499

if (display & (SEMINFO | SEMTOTAL)) {

usr.bin/sockstat/sockstat.c

603

display();

usr.bin/systat/altqs.c

100

u_int display;

usr.bin/systat/altqs.c

151

p->display = 1;

usr.bin/systat/altqs.c

224

if (p->display == 0)

usr.bin/systat/altqs.c

271

ifp->display = 1;

usr.bin/systat/altqs.c

358

if (ifp->display)

usr.bin/systat/cmds.c

130

display(0);

usr.bin/systat/cmds.c

98

display(0);

usr.bin/systat/extern.h

93

void display(int);

usr.bin/systat/ifstat.c

174

p->display = 1;

usr.bin/systat/ifstat.c

219

if (ifp->display == 0)

usr.bin/systat/ifstat.c

264

ifp->display = 1;

usr.bin/systat/ifstat.c

349

if (ifp->display) {

usr.bin/systat/ifstat.c

81

u_int display;

usr.bin/systat/main.c

174

signal(SIGALRM, display);

usr.bin/systat/main.c

175

display(0);

usr.bin/talk/io.c

113

display(&his_win, buf, nb);

usr.bin/talk/io.c

123

display(&my_win, buf, nb);

usr.bin/talk/talk.h

68

extern void display(xwin_t *, char *, int);

usr.bin/telnet/commands.c

2460

{ "display", displayhelp, display, 0 },

usr.sbin/mfiutil/mfi_foreign.c

261

MFI_COMMAND(foreign, display, foreign_display);

usr.sbin/pppctl/pppctl.c

106

if (display & (REC_SHOW|REC_VERBOSE)) {

usr.sbin/pppctl/pppctl.c

107

if (display & REC_VERBOSE)

usr.sbin/pppctl/pppctl.c

121

if (display & REC_PASSWD) {

usr.sbin/pppctl/pppctl.c

127

if (display & REC_VERBOSE)

usr.sbin/pppctl/pppctl.c

131

return Receive(fd, display & ~REC_PASSWD);

usr.sbin/pppctl/pppctl.c

88

Receive(int fd, int display)