Symbol: dce_environment
sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c
424
init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
sys/dev/drm/amd/display/dc/core/dc.c
624
dc_ctx->dce_environment = init_params->dce_environment;
sys/dev/drm/amd/display/dc/core/dc.c
663
dc_ctx->dce_environment,
sys/dev/drm/amd/display/dc/core/dc_link.c
2576
if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
sys/dev/drm/amd/display/dc/dc.h
349
enum dce_environment dce_environment;
sys/dev/drm/amd/display/dc/dc_helper.c
280
!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
sys/dev/drm/amd/display/dc/dc_helper.c
292
if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
sys/dev/drm/amd/display/dc/dc_types.h
58
#define IS_FPGA_MAXIMUS_DC(dce_environment) \
sys/dev/drm/amd/display/dc/dc_types.h
59
(dce_environment == DCE_ENV_FPGA_MAXIMUS)
sys/dev/drm/amd/display/dc/dc_types.h
61
#define IS_DIAG_DC(dce_environment) \
sys/dev/drm/amd/display/dc/dc_types.h
62
(IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
sys/dev/drm/amd/display/dc/dc_types.h
82
enum dce_environment dce_environment;
sys/dev/drm/amd/display/dc/dce/dce_clock_source.c
904
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
sys/dev/drm/amd/display/dc/dce/dce_clocks.c
336
if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
199
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
123
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
164
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
1101
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
2423
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
746
if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
985
if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.c
607
if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
1228
if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c
1464
(!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
sys/dev/drm/amd/display/dc/gpio/hw_factory.c
59
enum dce_environment dce_environment)
sys/dev/drm/amd/display/dc/gpio/hw_factory.c
61
if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
sys/dev/drm/amd/display/dc/gpio/hw_factory.h
72
enum dce_environment dce_environment);
sys/dev/drm/amd/display/dc/gpio/hw_translate.c
59
enum dce_environment dce_environment)
sys/dev/drm/amd/display/dc/gpio/hw_translate.c
61
if (IS_FPGA_MAXIMUS_DC(dce_environment)) {
sys/dev/drm/amd/display/dc/gpio/hw_translate.h
48
enum dce_environment dce_environment);
sys/dev/drm/amd/display/dc/i2caux/i2caux.c
76
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {