sys/dev/drm/amd/display/dc/core/dc_resource.c

2076

dst_ctx->dis_clk = dc->res_pool->dccg;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

175

static int dce_get_dp_ref_freq_khz(struct dccg *clk)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

201

static int dce12_get_dp_ref_freq_khz(struct dccg *clk)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

209

struct dccg *clk,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

241

struct dccg *clk,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

278

struct dccg *clk,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

294

struct dccg *clk,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

465

static void dce12_update_clocks(struct dccg *dccg,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

474

if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

477

new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

478

dccg->clks.dispclk_khz = new_clocks->dispclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

480

dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

483

if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

486

dccg->clks.phyclk_khz = new_clocks->phyclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

488

dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

493

static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

496

bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

498

bool cur_dpp_div = dccg->clks.dispclk_khz > dccg->clks.dppclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

528

if (dccg->clks.dispclk_khz <= disp_clk_threshold)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

539

static void dcn1_ramp_up_dispclk_with_dpp(struct dccg *dccg, struct dc_clocks *new_clocks)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

541

struct dc *dc = dccg->ctx->dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

542

int dispclk_to_dpp_threshold = dcn1_determine_dppclk_threshold(dccg, new_clocks);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

547

dccg->funcs->set_dispclk(dccg, dispclk_to_dpp_threshold);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

564

dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

566

dccg->clks.dispclk_khz = new_clocks->dispclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

567

dccg->clks.dppclk_khz = new_clocks->dppclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

568

dccg->clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

571

static void dcn1_update_clocks(struct dccg *dccg,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

575

struct dc *dc = dccg->ctx->dc;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

589

if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

590

|| new_clocks->phyclk_khz > dccg->clks.phyclk_khz

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

591

|| new_clocks->fclk_khz > dccg->clks.fclk_khz

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

592

|| new_clocks->dcfclk_khz > dccg->clks.dcfclk_khz)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

595

if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

596

dccg->clks.phyclk_khz = new_clocks->phyclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

601

if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, dccg->clks.fclk_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

602

dccg->clks.fclk_khz = new_clocks->fclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

607

dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

611

if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, dccg->clks.dcfclk_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

612

dccg->clks.dcfclk_khz = new_clocks->dcfclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

619

new_clocks->dcfclk_deep_sleep_khz, dccg->clks.dcfclk_deep_sleep_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

620

dccg->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

633

dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

640

if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

641

|| new_clocks->dispclk_khz == dccg->clks.dispclk_khz) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

642

dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

643

dccg->clks.dispclk_khz = new_clocks->dispclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

652

dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

662

static void dce_update_clocks(struct dccg *dccg,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

667

struct dce_dccg *clk_dce = TO_DCE_CLOCKS(dccg);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

673

level_change_req.power_level = dce_get_required_clocks_state(dccg, new_clocks);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

675

if ((level_change_req.power_level < dccg->cur_min_clks_state && safe_to_lower)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

676

|| level_change_req.power_level > dccg->cur_min_clks_state) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

677

if (dm_pp_apply_power_level_change_request(dccg->ctx, &level_change_req))

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

678

dccg->cur_min_clks_state = level_change_req.power_level;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

681

if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) {

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

682

new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

683

dccg->clks.dispclk_khz = new_clocks->dispclk_khz;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

688

struct dccg *dccg,

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

693

struct dce_dccg *clk_dce = TO_DCE_CLOCKS(dccg);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

734

dccg->clks.dispclk_khz =

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

735

dccg->funcs->set_dispclk(dccg, dccg->clks.dispclk_khz);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

782

struct dccg *base = &clk_dce->base;

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

804

struct dccg *dce_dccg_create(

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

827

struct dccg *dce110_dccg_create(

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

852

struct dccg *dce112_dccg_create(

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

877

struct dccg *dce120_dccg_create(struct dc_context *ctx)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

900

struct dccg *dcn1_dccg_create(struct dc_context *ctx)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

941

void dce_dccg_destroy(struct dccg **dccg)

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

943

struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg);

sys/dev/drm/amd/display/dc/dce/dce_clocks.c

946

*dccg = NULL;

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

103

struct dccg *dce110_dccg_create(

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

109

struct dccg *dce112_dccg_create(

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

115

struct dccg *dce120_dccg_create(struct dc_context *ctx);

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

118

struct dccg *dcn1_dccg_create(struct dc_context *ctx);

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

121

void dce_dccg_destroy(struct dccg **dccg);

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

70

struct dccg base;

sys/dev/drm/amd/display/dc/dce/dce_clocks.h

97

struct dccg *dce_dccg_create(

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

167

dc->res_pool->dccg->funcs->update_clocks(

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

168

dc->res_pool->dccg,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

734

if (pool->base.dccg != NULL)

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

735

dce_dccg_destroy(&pool->base.dccg);

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

922

pool->base.dccg = dce_dccg_create(ctx,

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

926

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce100/dce100_resource.c

956

pool->base.dccg->max_clks_state =

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2546

pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2574

struct dccg *dccg = dc->res_pool->dccg;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2584

if (dccg->funcs->update_dfs_bypass)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2585

dccg->funcs->update_dfs_bypass(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2586

dccg,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2591

dccg->funcs->update_clocks(

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

2592

dccg,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1267

pool->base.dccg = dce110_dccg_create(ctx,

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1271

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

1301

pool->base.dccg->max_clks_state =

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

767

if (pool->base.dccg != NULL)

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

768

dce_dccg_destroy(&pool->base.dccg);

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1213

pool->base.dccg = dce112_dccg_create(ctx,

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1217

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

1247

pool->base.dccg->max_clks_state =

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

761

if (pool->base.dccg != NULL)

sys/dev/drm/amd/display/dc/dce112/dce112_resource.c

762

dce_dccg_destroy(&pool->base.dccg);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

582

if (pool->base.dccg != NULL)

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

583

dce_dccg_destroy(&pool->base.dccg);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

982

pool->base.dccg = dce120_dccg_create(ctx);

sys/dev/drm/amd/display/dc/dce120/dce120_resource.c

983

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1141

pool->base.dccg = dce_dccg_create(ctx,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1145

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1172

pool->base.dccg->max_clks_state =

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1347

pool->base.dccg = dce_dccg_create(ctx,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1351

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

1378

pool->base.dccg->max_clks_state =

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

790

if (pool->base.dccg != NULL)

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

791

dce_dccg_destroy(&pool->base.dccg);

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

931

pool->base.dccg = dce_dccg_create(ctx,

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

935

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dce80/dce80_resource.c

962

pool->base.dccg->max_clks_state =

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

1132

memset(&dc->res_pool->dccg->clks, 0, sizeof(dc->res_pool->dccg->clks));

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2060

dc->res_pool->dccg->clks.dispclk_khz / 2;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2067

dc->res_pool->dccg->clks.dppclk_khz = should_divided_by_2 ?

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2068

dc->res_pool->dccg->clks.dispclk_khz / 2 :

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2069

dc->res_pool->dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2280

pp_display_cfg->min_engine_clock_khz = dc->res_pool->dccg->clks.dcfclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2281

pp_display_cfg->min_memory_clock_khz = dc->res_pool->dccg->clks.fclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2282

pp_display_cfg->min_engine_clock_deep_sleep_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2283

pp_display_cfg->min_dcfc_deep_sleep_clock_khz = dc->res_pool->dccg->clks.dcfclk_deep_sleep_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2284

pp_display_cfg->min_dcfclock_khz = dc->res_pool->dccg->clks.dcfclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2285

pp_display_cfg->disp_clk_khz = dc->res_pool->dccg->clks.dispclk_khz;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2427

dc->res_pool->dccg->funcs->update_clocks(

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2428

dc->res_pool->dccg,

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1285

pool->base.dccg = dcn1_dccg_create(ctx);

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

1286

if (pool->base.dccg == NULL) {

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

957

if (pool->base.dccg != NULL)

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

958

dce_dccg_destroy(&pool->base.dccg);

sys/dev/drm/amd/display/dc/inc/core_types.h

172

struct dccg *dccg;

sys/dev/drm/amd/display/dc/inc/core_types.h

290

struct dccg *dis_clk;

sys/dev/drm/amd/display/dc/inc/hw/display_clock.h

49

void (*update_clocks)(struct dccg *dccg,

sys/dev/drm/amd/display/dc/inc/hw/display_clock.h

52

int (*set_dispclk)(struct dccg *dccg,

sys/dev/drm/amd/display/dc/inc/hw/display_clock.h

55

int (*get_dp_ref_clk_frequency)(struct dccg *dccg);

sys/dev/drm/amd/display/dc/inc/hw/display_clock.h

57

bool (*update_dfs_bypass)(struct dccg *dccg,