sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

101

adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1;

sys/dev/drm/amd/display/dc/bios/bios_parser.c

827

enum controller_id id,

sys/dev/drm/amd/display/dc/bios/bios_parser.c

852

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/bios_parser.c

860

return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,

sys/dev/drm/amd/display/dc/bios/bios_parser2.c

1060

enum controller_id id,

sys/dev/drm/amd/display/dc/bios/bios_parser2.c

1085

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/bios_parser2.c

1093

return bp->cmd_tbl.enable_disp_power_gating(bp, controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

1019

uint8_t controller_id;

sys/dev/drm/amd/display/dc/bios/command_table.c

1026

bp_params->controller_id, &controller_id)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1027

clk.sPCLKInput.ucCRTC = controller_id;

sys/dev/drm/amd/display/dc/bios/command_table.c

1076

uint8_t controller_id;

sys/dev/drm/amd/display/dc/bios/command_table.c

1083

bp_params->controller_id, &controller_id)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1103

clk.sPCLKInput.ulCrtcPclkFreq.ucCRTC = controller_id;

sys/dev/drm/amd/display/dc/bios/command_table.c

1154

uint8_t controller_id;

sys/dev/drm/amd/display/dc/bios/command_table.c

1160

&& bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

1180

clk.ucCRTC = controller_id;

sys/dev/drm/amd/display/dc/bios/command_table.c

1752

bp_params->controller_id, &atom_controller_id))

sys/dev/drm/amd/display/dc/bios/command_table.c

1825

bp_params->controller_id, &atom_controller_id))

sys/dev/drm/amd/display/dc/bios/command_table.c

1945

bp_params->controller_id, &atom_controller_id))

sys/dev/drm/amd/display/dc/bios/command_table.c

1984

if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

2023

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

2042

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

2049

if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))

sys/dev/drm/amd/display/dc/bios/command_table.c

2075

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

2092

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

2099

if (bp->cmd_helper->controller_id_to_atom(controller_id, &id)) {

sys/dev/drm/amd/display/dc/bios/command_table.c

2355

enum controller_id crtc_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

2376

enum controller_id crtc_id,

sys/dev/drm/amd/display/dc/bios/command_table.c

986

if (CONTROLLER_ID_D1 != bp_params->controller_id)

sys/dev/drm/amd/display/dc/bios/command_table.h

79

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.h

83

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table.h

93

enum controller_id crtc_id,

sys/dev/drm/amd/display/dc/bios/command_table2.c

266

uint8_t controller_id;

sys/dev/drm/amd/display/dc/bios/command_table2.c

273

controller_id, &controller_id)) {

sys/dev/drm/amd/display/dc/bios/command_table2.c

293

clk.crtc_id = controller_id;

sys/dev/drm/amd/display/dc/bios/command_table2.c

378

bp_params->controller_id, &atom_controller_id))

sys/dev/drm/amd/display/dc/bios/command_table2.c

503

if (bp->cmd_helper->controller_id_to_atom(bp_params->controller_id,

sys/dev/drm/amd/display/dc/bios/command_table2.c

542

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table2.c

561

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table2.c

568

if (bp->cmd_helper->controller_id_to_atom(controller_id, &id))

sys/dev/drm/amd/display/dc/bios/command_table2.c

638

enum controller_id crtc_id,

sys/dev/drm/amd/display/dc/bios/command_table2.c

659

enum controller_id crtc_id,

sys/dev/drm/amd/display/dc/bios/command_table2.h

79

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table2.h

83

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/bios/command_table2.h

93

enum controller_id crtc_id,

sys/dev/drm/amd/display/dc/bios/command_table_helper.c

68

enum controller_id id,

sys/dev/drm/amd/display/dc/bios/command_table_helper.h

38

enum controller_id id,

sys/dev/drm/amd/display/dc/bios/command_table_helper2.c

83

enum controller_id id,

sys/dev/drm/amd/display/dc/bios/command_table_helper2.h

38

enum controller_id id,

sys/dev/drm/amd/display/dc/bios/command_table_helper_struct.h

35

bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);

sys/dev/drm/amd/display/dc/core/dc_link.c

2185

unsigned int controller_id = 0;

sys/dev/drm/amd/display/dc/core/dc_link.c

2215

controller_id =

sys/dev/drm/amd/display/dc/core/dc_link.c

2225

controller_id,

sys/dev/drm/amd/display/dc/core/dc_surface.c

65

uint32_t controller_id)

sys/dev/drm/amd/display/dc/core/dc_surface.c

67

plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1;

sys/dev/drm/amd/display/dc/dc_bios_types.h

106

enum controller_id id,

sys/dev/drm/amd/display/dc/dc_bios_types.h

133

enum controller_id controller_id,

sys/dev/drm/amd/display/dc/dc_types.h

596

enum controller_id controllerId;

sys/dev/drm/amd/display/dc/dce/dce_abm.c

199

uint32_t controller_id)

sys/dev/drm/amd/display/dc/dce/dce_abm.c

213

MASTER_COMM_CMD_REG_BYTE1, controller_id);

sys/dev/drm/amd/display/dc/dce/dce_abm.c

226

if (controller_id == 0)

sys/dev/drm/amd/display/dc/dce/dce_abm.c

407

unsigned int controller_id,

sys/dev/drm/amd/display/dc/dce/dce_abm.c

420

controller_id);

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

854

bp_pc_params.controller_id = pix_clk_params->controller_id;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

905

unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

928

bp_pc_params.controller_id = pix_clk_params->controller_id;

sys/dev/drm/amd/display/dc/dce/dce_clock_source.c

968

bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

74

uint8_t controller_id,

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

89

if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

92

dcb, controller_id + 1, cntl);

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.c

98

HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),

sys/dev/drm/amd/display/dc/dce100/dce100_hw_sequencer.h

41

bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

491

unsigned int controller_id_to_index(enum controller_id controller_id)

sys/dev/drm/amd/display/dc/dce110/dce110_compressor.c

495

switch (controller_id) {

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

1120

static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

190

uint8_t controller_id,

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

209

if (controller_id == underlay_idx)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

210

controller_id = CONTROLLER_ID_UNDERLAY0 - 1;

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

212

if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

215

dcb, controller_id + 1, cntl);

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

224

if (controller_id < CONTROLLER_ID_MAX - 1)

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

226

HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),

sys/dev/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

631

crtc_source_select.controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dce110/dce110_resource.c

789

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

146

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

1805

switch (tg110->controller_id) {

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

2245

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

238

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false);

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.c

308

bp_params.controller_id = tg110->controller_id;

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator.h

101

enum controller_id controller_id;

sys/dev/drm/amd/display/dc/dce110/dce110_timing_generator_v.c

688

tg110->controller_id = CONTROLLER_ID_UNDERLAY0;

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

115

uint8_t controller_id,

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

133

if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

136

dcb, controller_id + 1, cntl);

sys/dev/drm/amd/display/dc/dce112/dce112_hw_sequencer.c

142

HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

154

uint8_t controller_id,

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

174

if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

177

dcb, controller_id + 1, cntl);

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

183

HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

188

dce120_init_pte(ctx, controller_id);

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

79

#define CNTL_ID(controller_id)\

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

80

controller_id

sys/dev/drm/amd/display/dc/dce120/dce120_hw_sequencer.c

85

static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

1184

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

155

result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true);

sys/dev/drm/amd/display/dc/dce120/dce120_timing_generator.c

408

switch (tg110->controller_id) {

sys/dev/drm/amd/display/dc/dce80/dce80_timing_generator.c

225

tg110->controller_id = CONTROLLER_ID_D0 + instance;

sys/dev/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

2603

uint8_t controller_id,

sys/dev/drm/amd/display/dc/dcn10/dcn10_optc.h

430

enum controller_id controller_id;

sys/dev/drm/amd/display/dc/dcn10/dcn10_resource.c

986

pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;

sys/dev/drm/amd/display/dc/dm_services.h

332

bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int controller_id);

sys/dev/drm/amd/display/dc/inc/clock_source.h

92

enum controller_id controller_id;

sys/dev/drm/amd/display/dc/inc/core_types.h

43

uint32_t controller_id);

sys/dev/drm/amd/display/dc/inc/hw/abm.h

53

unsigned int controller_id,

sys/dev/drm/amd/display/dc/inc/hw_sequencer.h

149

uint8_t controller_id,

sys/dev/drm/amd/display/include/bios_parser_types.h

129

enum controller_id controller_id;

sys/dev/drm/amd/display/include/bios_parser_types.h

160

enum controller_id controller_id;

sys/dev/drm/amd/display/include/bios_parser_types.h

208

enum controller_id controller_id; /* (Which CRTC uses this PLL) */

sys/dev/drm/amd/display/include/grph_object_id.h

248

static inline enum controller_id dal_graphics_object_id_get_controller_id(

sys/dev/drm/amd/display/include/grph_object_id.h

252

return (enum controller_id) id.id;

sys/dev/drm/amd/include/dm_pp_interface.h

51

uint32_t controller_id;

sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c

295

if (display_config->displays[index].controller_id != 0)