include/time.h

122

clock_t clock(void);

lib/libc/resolv/res_debug.c

1137

time_t clock = secs;

lib/libc/resolv/res_debug.c

1142

time = gmtime_r(&clock, &res);

lib/libc/resolv/res_debug.c

1144

time = gmtime(&clock);

libexec/rpc.sprayd/sprayd.c

151

scum.clock.sec = get.tv_sec;

libexec/rpc.sprayd/sprayd.c

152

scum.clock.usec = get.tv_usec;

sys/bus/mmc/bridge.h

124

uint32_t clock; /* Speed of the clock in Hz to move data */

sys/bus/mmc/mmc.c

721

uint32_t clock;

sys/bus/mmc/mmc.c

730

clock = mmcbr_get_clock(dev);

sys/bus/mmc/mmc.c

733

if (clock <= MMC_TYPE_HS_26_MAX) {

sys/bus/mmc/mmc.c

735

} else if (clock <= MMC_TYPE_HS_52_MAX) {

sys/bus/mmc/mmc.c

741

} else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) {

sys/bus/mmc/mmc.c

754

if (clock <= MMC_TYPE_HS_26_MAX) {

sys/bus/mmc/mmc.c

756

} else if (clock <= MMC_TYPE_HS_52_MAX) {

sys/bus/mmc/mmc.c

762

} else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) {

sys/bus/mmc/mmcbrvar.h

90

MMCBR_ACCESSOR(clock, CLOCK, int)

sys/dev/disk/sdhci/sdhci.c

1044

sdhci_set_clock(slot, slot->host.ios.clock);

sys/dev/disk/sdhci/sdhci.c

1127

slot->clock == 0) {

sys/dev/disk/sdhci/sdhci.c

176

uint32_t clock;

sys/dev/disk/sdhci/sdhci.c

1845

*(int *)result = slot->host.ios.clock;

sys/dev/disk/sdhci/sdhci.c

187

clock = slot->clock;

sys/dev/disk/sdhci/sdhci.c

188

slot->clock = 0;

sys/dev/disk/sdhci/sdhci.c

189

sdhci_set_clock(slot, clock);

sys/dev/disk/sdhci/sdhci.c

1894

uint32_t clock, max_clock;

sys/dev/disk/sdhci/sdhci.c

1912

clock = max_clock;

sys/dev/disk/sdhci/sdhci.c

1917

if (clock <= value)

sys/dev/disk/sdhci/sdhci.c

1919

clock >>= 1;

sys/dev/disk/sdhci/sdhci.c

1924

if (clock <= value)

sys/dev/disk/sdhci/sdhci.c

1926

clock = max_clock / (i + 2);

sys/dev/disk/sdhci/sdhci.c

193

slot->clock = 0;

sys/dev/disk/sdhci/sdhci.c

1930

slot->host.ios.clock = clock;

sys/dev/disk/sdhci/sdhci.c

1932

slot->host.ios.clock = 0;

sys/dev/disk/sdhci/sdhci.c

252

sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock)

sys/dev/disk/sdhci/sdhci.c

261

if (clock == slot->clock)

sys/dev/disk/sdhci/sdhci.c

263

slot->clock = clock;

sys/dev/disk/sdhci/sdhci.c

269

if (clock == 0)

sys/dev/disk/sdhci/sdhci.c

278

if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) {

sys/dev/disk/sdhci/sdhci.c

290

slot->timeout_clk = slot->clock / 1000;

sys/dev/disk/sdhci/sdhci.c

296

if (res <= clock)

sys/dev/disk/sdhci/sdhci.c

304

if (clock >= clk_base)

sys/dev/disk/sdhci/sdhci.c

308

if ((clk_base / div) <= clock)

sys/dev/disk/sdhci/sdhci.c

317

div, clock, clk_base);

sys/dev/disk/sdhci/sdhci.c

81

static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);

sys/dev/disk/sdhci/sdhci.c

936

else if (ios->clock > SD_SDR50_MAX)

sys/dev/disk/sdhci/sdhci.c

938

else if (ios->clock > SD_SDR25_MAX)

sys/dev/disk/sdhci/sdhci.c

940

else if (ios->clock > SD_SDR12_MAX) {

sys/dev/disk/sdhci/sdhci.c

946

} else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY)

sys/dev/disk/sdhci/sdhci.c

949

sdhci_set_clock(slot, ios->clock);

sys/dev/disk/sdhci/sdhci.c

965

sdhci_set_clock(slot, ios->clock);

sys/dev/disk/sdhci/sdhci.c

979

if (ios->clock > SD_SDR12_MAX &&

sys/dev/disk/sdhci/sdhci.h

386

uint32_t clock; /* Current clock freq. */

sys/dev/drm/amd/amdgpu/amdgpu.h

1258

u32 clock;

sys/dev/drm/amd/amdgpu/amdgpu.h

1271

struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);

sys/dev/drm/amd/amdgpu/amdgpu.h

918

struct amdgpu_clock clock;

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

100

amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

101

amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

102

amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

51

static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq)

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

58

cts = clock * 1000;

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

88

struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock)

sys/dev/drm/amd/amdgpu/amdgpu_afmt.c

95

if (amdgpu_afmt_predefined_acr[i].clock == clock)

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

381

mem_info->mem_clk_max = adev->clock.default_mclk / 100;

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd.c

404

return adev->clock.default_sclk / 100;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1014

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1035

args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1053

args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1073

args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1084

args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1103

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1122

args.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

585

struct amdgpu_pll *ppll = &adev->clock.ppll[0];

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

586

struct amdgpu_pll *spll = &adev->clock.spll;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

587

struct amdgpu_pll *mpll = &adev->clock.mpll;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

629

adev->clock.ppll[i] = *ppll;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

677

adev->clock.default_sclk =

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

679

adev->clock.default_mclk =

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

691

adev->clock.default_dispclk =

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

694

if (adev->clock.default_dispclk < 53900) {

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

696

adev->clock.default_dispclk / 100);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

697

adev->clock.default_dispclk = 60000;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

698

} else if (adev->clock.default_dispclk <= 60000) {

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

700

adev->clock.default_dispclk / 100);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

701

adev->clock.default_dispclk = 62500;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

703

adev->clock.dp_extclk =

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

705

adev->clock.current_dispclk = adev->clock.default_dispclk;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

707

adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

708

if (adev->clock.max_pixel_clock == 0)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

709

adev->clock.max_pixel_clock = 40000;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

718

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

719

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

898

int id, u32 clock)

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

932

(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

950

(clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

972

(clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

155

int id, u32 clock);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

159

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atombios.h

164

u32 clock,

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

252

struct amdgpu_pll *spll = &adev->clock.spll;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

253

struct amdgpu_pll *mpll = &adev->clock.mpll;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

266

adev->clock.default_sclk =

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

268

adev->clock.default_mclk =

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

271

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/amdgpu_atomfirmware.c

272

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

1168

if (amdgpu_connector->use_digital && (mode->clock > 165000)) {

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

1175

if (mode->clock > 340000)

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

1185

if ((mode->clock / 10) > adev->clock.max_pixel_clock)

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

1319

if ((adev->clock.default_dispclk >= 53900) &&

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

1461

if (mode->clock > 340000)

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

1464

if (mode->clock > 165000)

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

376

amdgpu_encoder->native_mode.clock = 0;

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

390

native_mode->clock != 0) {

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

598

(amdgpu_encoder->native_mode.clock == 0))

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

627

if (!native_mode->clock) {

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

639

if (!native_mode->clock) {

sys/dev/drm/amd/amdgpu/amdgpu_connectors.c

846

if ((mode->clock / 10) > adev->clock.max_pixel_clock)

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

151

if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

158

vblank_time_us = vblank_in_pixels * 1000 / amdgpu_crtc->hw_mode.clock;

sys/dev/drm/amd/amdgpu/amdgpu_dpm.c

177

if (crtc->enabled && amdgpu_crtc->enabled && amdgpu_crtc->hw_mode.clock) {

sys/dev/drm/amd/amdgpu/amdgpu_encoders.c

160

adjusted_mode->clock = native_mode->clock;

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

129

static void amdgpu_i2c_set_clock(void *i2c_priv, int clock)

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

138

val |= clock ? 0 : rec->en_clk_mask;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

703

dev_info.max_engine_clock = adev->clock.default_sclk * 10;

sys/dev/drm/amd/amdgpu/amdgpu_kms.c

704

dev_info.max_memory_clock = adev->clock.default_mclk * 10;

sys/dev/drm/amd/amdgpu/amdgpu_pll.c

343

if ((crtc->mode.clock == test_crtc->mode.clock) &&

sys/dev/drm/amd/amdgpu/atombios_crtc.c

314

u32 adjusted_clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

316

u32 dp_clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

317

u32 clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

319

bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

350

adjusted_clock = mode->clock * 2;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

364

clock = (clock * 5) / 4;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

367

clock = (clock * 3) / 2;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

370

clock = clock * 2;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

391

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

403

args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

581

u32 clock,

sys/dev/drm/amd/amdgpu/atombios_crtc.c

606

if (clock == ATOM_DISABLE)

sys/dev/drm/amd/amdgpu/atombios_crtc.c

608

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

618

args.v2.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

628

args.v3.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

645

args.v5.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

675

args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

707

args.v7.ulPixelClock = cpu_to_le32(clock * 10); /* 100 hz units */

sys/dev/drm/amd/amdgpu/atombios_crtc.c

710

(clock > 165000))

sys/dev/drm/amd/amdgpu/atombios_crtc.c

772

amdgpu_connector->pixelclock_for_modeset = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

790

mode->clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

797

mode->clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

804

mode->clock / 10);

sys/dev/drm/amd/amdgpu/atombios_crtc.c

824

u32 pll_clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

825

u32 clock = mode->clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

833

clock = amdgpu_crtc->adjusted_clock;

sys/dev/drm/amd/amdgpu/atombios_crtc.c

837

pll = &adev->clock.ppll[0];

sys/dev/drm/amd/amdgpu/atombios_crtc.c

840

pll = &adev->clock.ppll[1];

sys/dev/drm/amd/amdgpu/atombios_crtc.c

845

pll = &adev->clock.ppll[2];

sys/dev/drm/amd/amdgpu/atombios_crtc.c

861

encoder_mode, amdgpu_encoder->encoder_id, clock,

sys/dev/drm/amd/amdgpu/atombios_crtc.h

47

u32 clock,

sys/dev/drm/amd/amdgpu/atombios_dp.c

412

mode->clock,

sys/dev/drm/amd/amdgpu/atombios_dp.c

435

mode->clock, &dp_lanes, &dp_clock);

sys/dev/drm/amd/amdgpu/atombios_encoders.c

1039

if (is_dp && adev->clock.dp_extclk)

sys/dev/drm/amd/amdgpu/atombios_encoders.c

1099

if (adev->clock.dp_extclk)

sys/dev/drm/amd/amdgpu/atombios_encoders.c

1166

if (is_dp && adev->clock.dp_extclk)

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2091

lvds->native_mode.clock =

sys/dev/drm/amd/amdgpu/ci_dpm.c

2122

u32 ref_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

2572

u32 clock, u32 *voltage)

sys/dev/drm/amd/amdgpu/ci_dpm.c

2580

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/drm/amd/amdgpu/ci_dpm.c

2970

u32 reference_clock = adev->clock.mpll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3152

table->ACPILevel.SclkFrequency = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3313

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/ci_dpm.c

3943

if (adev->clock.current_dispclk == disp_voltage_table->entries[i].clk)

sys/dev/drm/amd/amdgpu/ci_dpm.c

6294

adev->pm.default_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6295

adev->pm.default_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6296

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6297

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6548

uint32_t clock, pcie_speed;

sys/dev/drm/amd/amdgpu/ci_dpm.c

6553

clock = RREG32(mmSMC_MSG_ARG_0);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6556

if (clock > sclk_table->dpm_levels[i].value)

sys/dev/drm/amd/amdgpu/ci_dpm.c

6569

clock = RREG32(mmSMC_MSG_ARG_0);

sys/dev/drm/amd/amdgpu/ci_dpm.c

6572

if (clock > mclk_table->dpm_levels[i].value)

sys/dev/drm/amd/amdgpu/cik.c

1298

static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/drm/amd/amdgpu/cik.c

1307

clock, false, &dividers);

sys/dev/drm/amd/amdgpu/cik.c

842

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1026

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1028

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1042

wm_high.disp_clk = mode->clock;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1081

wm_low.disp_clk = mode->clock;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1458

static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1462

struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1513

static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1521

u32 dto_modulo = clock;

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1574

dce_v10_0_audio_set_dto(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1657

dce_v10_0_afmt_update_ACR(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2233

if (adev->clock.dp_extclk)

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2840

amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3302

amdgpu_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1052

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1054

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1068

wm_high.disp_clk = mode->clock;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1107

wm_low.disp_clk = mode->clock;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1500

static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1504

struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1555

static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1563

u32 dto_modulo = clock;

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1616

dce_v11_0_audio_set_dto(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1699

dce_v11_0_afmt_update_ACR(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2302

if (adev->clock.dp_extclk)

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2698

adjusted_mode->clock, 0, 0, 0, 0,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2967

amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2972

amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3428

amdgpu_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1016

wm_low.disp_clk = mode->clock;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1421

static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1425

struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1464

static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1472

u32 dto_modulo = clock;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1523

dce_v8_0_audio_set_dto(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1593

dce_v8_0_afmt_update_ACR(encoder, mode->clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2123

if (adev->clock.dp_extclk)

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2735

amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3190

amdgpu_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/drm/amd/amdgpu/dce_v8_0.c

961

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

963

(u32)mode->clock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

977

wm_high.disp_clk = mode->clock;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4158

uint64_t clock;

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4162

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4165

return clock;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5217

uint64_t clock;

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5221

clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5224

return clock;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3543

uint64_t clock;

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3547

clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

3550

return clock;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3012

adev->pm.default_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3013

adev->pm.default_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3014

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/kv_dpm.c

3015

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

3251

u32 i, clock = 0;

sys/dev/drm/amd/amdgpu/si_dpm.c

3254

*max_clock = clock;

sys/dev/drm/amd/amdgpu/si_dpm.c

3259

if (clock < table->entries[i].clk)

sys/dev/drm/amd/amdgpu/si_dpm.c

3260

clock = table->entries[i].clk;

sys/dev/drm/amd/amdgpu/si_dpm.c

3262

*max_clock = clock;

sys/dev/drm/amd/amdgpu/si_dpm.c

3266

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/drm/amd/amdgpu/si_dpm.c

3274

if (clock <= table->entries[i].clk) {

sys/dev/drm/amd/amdgpu/si_dpm.c

3622

adev->clock.current_dispclk,

sys/dev/drm/amd/amdgpu/si_dpm.c

5257

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/si_dpm.c

5379

u32 reference_clock = adev->clock.mpll.reference_freq;

sys/dev/drm/amd/amdgpu/si_dpm.c

5622

if (adev->clock.current_dispclk <=

sys/dev/drm/amd/amdgpu/si_dpm.c

7189

pl->mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

7190

pl->sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

7702

adev->pm.default_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

7703

adev->pm.default_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

7704

adev->pm.current_sclk = adev->clock.default_sclk;

sys/dev/drm/amd/amdgpu/si_dpm.c

7705

adev->pm.current_mclk = adev->clock.default_mclk;

sys/dev/drm/amd/amdgpu/soc15.c

215

return adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/vi.c

328

u32 reference_clock = adev->clock.spll.reference_freq;

sys/dev/drm/amd/amdgpu/vi.c

718

static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,

sys/dev/drm/amd/amdgpu/vi.c

727

clock, false, &dividers);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2776

} else if (native_mode->clock == drm_mode->clock &&

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3345

mode->clock,

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3784

amdgpu_encoder->native_mode.clock = 0;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

193

int clock;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

210

clock = stream->timing.pix_clk_khz;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

241

pbn = drm_dp_calc_pbn_mode(clock, bpp);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

237

DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

238

dc_clks->clocks_in_khz[i] = pp_clks->clock[i];

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

483

struct pp_display_clock_request clock = {0};

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

488

clock.clock_type = amd_pp_dcf_clock;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

489

clock.clock_freq_in_khz = req->hard_min_dcefclk_khz;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

490

pp_funcs->display_clock_voltage_request(pp_handle, &clock);

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

492

clock.clock_type = amd_pp_f_clock;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

493

clock.clock_freq_in_khz = req->hard_min_fclk_khz;

sys/dev/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c

494

pp_funcs->display_clock_voltage_request(pp_handle, &clock);

sys/dev/drm/amd/include/dm_pp_interface.h

165

uint32_t clock[MAX_NUM_CLOCKS];

sys/dev/drm/amd/include/kgd_pp_interface.h

274

struct pp_display_clock_request *clock);

sys/dev/drm/amd/powerplay/amd_powerplay.c

1172

struct pp_display_clock_request *clock)

sys/dev/drm/amd/powerplay/amd_powerplay.c

1177

if (!hwmgr || !hwmgr->pm_en ||!clock)

sys/dev/drm/amd/powerplay/amd_powerplay.c

1181

ret = phm_display_clock_voltage_request(hwmgr, clock);

sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c

454

struct pp_display_clock_request *clock)

sys/dev/drm/amd/powerplay/hwmgr/hardwaremanager.c

461

return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1168

uint32_t clock;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1178

clock = 2700;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1184

clock = (uint32_t)(le16_to_cpu(fwInfo_2_1->usMemoryReferenceClock));

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1188

clock = (uint32_t)(le16_to_cpu(fwInfo_0_0->usReferenceClock));

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

1192

return clock;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

487

uint32_t clock;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

495

clock = 2700;

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

497

clock = (uint32_t)(le16_to_cpu(fw_info->usReferenceClock));

sys/dev/drm/amd/powerplay/hwmgr/ppatomctrl.c

499

return clock;

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

214

static inline uint32_t convert_10k_to_mhz(uint32_t clock)

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

216

return (clock + 99) / 100;

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

219

static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

224

smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

225

smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

964

uint32_t clock)

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

966

if (clock >= MEM_FREQ_LOW_LATENCY &&

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

967

clock < MEM_FREQ_HIGH_LATENCY)

sys/dev/drm/amd/powerplay/hwmgr/smu10_hwmgr.c

969

else if (clock >= MEM_FREQ_HIGH_LATENCY)

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3749

dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

3756

dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4414

uint32_t clock, pcie_speed;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4419

clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4422

if (clock > sclk_table->dpm_levels[i].value)

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4435

clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4438

if (clock > mclk_table->dpm_levels[i].value)

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4470

i, odn_sclk_table->entries[i].clock/100,

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4479

i, odn_mclk_table->entries[i].clock/100,

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4626

clocks->clock[i] = dep_sclk_table->entries[i].clk * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4631

clocks->clock[i] = sclk_table->entries[i].clk * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4663

clocks->clock[i] = dep_mclk_table->entries[i].clk * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4671

clocks->clock[i] = mclk_table->entries[i].clk * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

4864

podn_dpm_table_in_backend->entries[input_level].clock = input_clk;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

5118

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

5125

PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0);

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

5127

temp = clock >> i;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

839

entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

851

entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value;

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

905

if (odn_table->odn_core_clock_dpm_levels.entries[i].clock !=

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

913

if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock !=

sys/dev/drm/amd/powerplay/hwmgr/smu7_hwmgr.h

365

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

100

uint32_t clock, uint32_t msg)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

110

if (clock <= table->entries[i].clk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1148

unsigned long clock = 0, level;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1161

clock = table->entries[level].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1163

clock = table->entries[table->count - 1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1165

data->sclk_dpm.soft_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1166

data->sclk_dpm.hard_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

118

if (clock >= table->entries[i].clk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

130

uint32_t clock, uint32_t msg)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

140

if (clock <= ptable->entries[i].vclk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

148

if (clock >= ptable->entries[i].vclk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1617

clocks->clock[i] = data->sys_info.display_clock[i] * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1622

clocks->clock[i] = table->entries[i].clk * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

1627

clocks->clock[i] = data->sys_info.nbp_memory_clock[clocks->count - 1 - i] * 10;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

559

unsigned long clock = 0, level;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

570

clock = table->entries[level].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

572

clock = table->entries[table->count - 1].clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

574

data->sclk_dpm.soft_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

575

data->sclk_dpm.hard_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

585

unsigned long clock = 0, level;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

597

clock = table->entries[level].vclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

599

clock = table->entries[table->count - 1].vclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

601

data->uvd_dpm.soft_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

602

data->uvd_dpm.hard_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

612

unsigned long clock = 0, level;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

624

clock = table->entries[level].ecclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

626

clock = table->entries[table->count - 1].ecclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

628

data->vce_dpm.soft_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

629

data->vce_dpm.hard_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

639

unsigned long clock = 0, level;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

651

clock = table->entries[level].acpclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

653

clock = table->entries[table->count - 1].acpclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

655

data->acp_dpm.soft_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

656

data->acp_dpm.hard_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

689

unsigned long clock = 0;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

69

uint32_t clock, uint32_t msg)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

702

clock = hwmgr->display_config->min_core_set_clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

703

if (clock == 0)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

706

if (data->sclk_dpm.hard_min_clk != clock) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

707

data->sclk_dpm.hard_min_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

716

clock = data->sclk_dpm.soft_min_clk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

726

if (clock < stable_pstate_sclk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

727

clock = stable_pstate_sclk;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

730

if (data->sclk_dpm.soft_min_clk != clock) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

731

data->sclk_dpm.soft_min_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

741

data->sclk_dpm.soft_max_clk != clock) {

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

742

data->sclk_dpm.soft_max_clk = clock;

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

79

if (clock <= ptable->entries[i].ecclk)

sys/dev/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

87

if (clock >= ptable->entries[i].ecclk)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1614

uint32_t *clock,

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1621

*clock = data->clk_range[clock_select].ACMax;

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1623

*clock = data->clk_range[clock_select].ACMin;

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

1656

uint32_t clock)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

489

PPCLK_e clkID, uint32_t index, uint32_t *clock)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

502

*clock = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

53

uint32_t *clock,

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

876

PPCLK_e clkid, struct vega12_clock_range *clock)

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

883

clock->ACMax = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

890

clock->ACMin = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega12_hwmgr.c

897

clock->DCMax = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1433

PP_Clock *clock, PPCLK_e clock_select)

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1442

*clock = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1445

if (*clock == 0) {

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1451

*clock = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1841

uint32_t *clock,

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1846

*clock = 0;

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1853

*clock = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

1860

*clock = smum_get_argument(hwmgr);

sys/dev/drm/amd/powerplay/hwmgr/vega20_hwmgr.c

2418

uint32_t clock)

sys/dev/drm/amd/powerplay/inc/hardwaremanager.h

374

uint32_t clock[MAX_NUM_CLOCKS];

sys/dev/drm/amd/powerplay/inc/hardwaremanager.h

385

uint32_t clock;

sys/dev/drm/amd/powerplay/inc/hardwaremanager.h

462

struct pp_display_clock_request *clock);

sys/dev/drm/amd/powerplay/inc/hwmgr.h

299

struct pp_display_clock_request *clock);

sys/dev/drm/amd/powerplay/inc/hwmgr.h

313

int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

277

uint32_t clock, uint32_t *vol)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

285

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

296

uint32_t clock, struct SMU7_Discrete_GraphicsLevel *sclk)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

311

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

341

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

359

sclk->SclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

386

static uint8_t ci_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

393

if (clock < min) {

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

398

temp = clock >> i;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

407

uint32_t clock, struct SMU7_Discrete_GraphicsLevel *level)

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

413

result = ci_calculate_sclk_params(hwmgr, clock, level);

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

417

hwmgr->dyn_state.vddc_dependency_on_sclk, clock,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

424

level->SclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

430

clock,

sys/dev/drm/amd/powerplay/smumgr/ci_smumgr.c

448

ci_get_sleep_divider_id_from_clock(clock,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1147

uint32_t clock, struct SMU73_Discrete_MemoryLevel *mclk)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1152

result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1158

mclk->MclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1160

mclk->FreqRange = fiji_get_mclk_frequency_ratio(clock);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1166

uint32_t clock, struct SMU73_Discrete_MemoryLevel *mem_level)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1182

vdd_dep_table, clock,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1207

(clock <= mclk_stutter_mode_threshold) &&

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

1213

result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

356

uint32_t clock, uint32_t *voltage, uint32_t *mvdd)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

370

if (dep_table->entries[i].clk >= clock) {

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

858

uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

873

result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

904

uint32_t vco_freq = clock * dividers.uc_pll_post_div;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

928

sclk->SclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

939

uint32_t clock, struct SMU73_Discrete_GraphicsLevel *level)

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

949

result = fiji_calculate_sclk_params(hwmgr, clock, level);

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

958

vdd_dep_table, clock,

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

965

level->SclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

976

threshold = clock * data->fast_watermark_threshold / 100;

sys/dev/drm/amd/powerplay/smumgr/fiji_smumgr.c

981

level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

508

uint32_t clock, uint32_t *vol)

sys/dev/drm/amd/powerplay/smumgr/iceland_smumgr.c

518

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1071

uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1088

vdd_dep_table, clock,

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1095

mem_level->MclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

1109

(clock <= mclk_stutter_mode_threshold) &&

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

353

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

367

if (dep_table->entries[i].clk >= clock) {

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

841

uint32_t clock, SMU_SclkSetting *sclk_setting)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

852

sclk_setting->SclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

854

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

873

if (clock > smu_data->range_table[i].trans_lower_frequency

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

874

&& clock <= smu_data->range_table[i].trans_upper_frequency) {

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

880

sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

881

temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

887

pcc_target_freq = clock - (clock * pcc_target_percent / 100);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

894

ss_target_freq = clock - (clock * ss_target_percent / 100);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

906

uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

917

result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

926

vdd_dep_table, clock,

sys/dev/drm/amd/powerplay/smumgr/polaris10_smumgr.c

946

level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

247

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/drm/amd/powerplay/smumgr/tonga_smumgr.c

260

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

1015

(clock <= mclk_stutter_mode_threshold) &&

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

602

uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

616

if (dep_table->entries[i].clk >= clock) {

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

718

uint32_t clock, SMU_SclkSetting *sclk_setting)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

729

sclk_setting->SclkFrequency = clock;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

731

result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, &dividers);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

750

if (clock > smu_data->range_table[i].trans_lower_frequency

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

751

&& clock <= smu_data->range_table[i].trans_upper_frequency) {

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

758

((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

760

temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

766

pcc_target_freq = clock - (clock * pcc_target_percent / 100);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

775

ss_target_freq = clock - (clock * ss_target_percent / 100);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

788

static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

795

PP_ASSERT_WITH_CODE((clock >= min),

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

799

temp = clock / (i + 1);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

808

uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

818

result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

822

table_info->vdd_dep_on_sclk, clock,

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

840

level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

962

uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

967

clock, &mpll_param),

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

980

uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

991

table_info->vdd_dep_on_mclk, clock,

sys/dev/drm/amd/powerplay/smumgr/vegam_smumgr.c

998

result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);

sys/dev/drm/drm_dp_mst_topology.c

2894

int drm_dp_calc_pbn_mode(int clock, int bpp)

sys/dev/drm/drm_dp_mst_topology.c

2901

kbps = clock * bpp;

sys/dev/drm/drm_edid.c

2306

mode->clock = le16_to_cpu(timing->pixel_clock) * 10;

sys/dev/drm/drm_edid.c

2419

if (mode->clock > max_clock)

sys/dev/drm/drm_edid.c

2922

unsigned int clock = cea_mode->clock;

sys/dev/drm/drm_edid.c

2925

return clock;

sys/dev/drm/drm_edid.c

2933

clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);

sys/dev/drm/drm_edid.c

2935

clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);

sys/dev/drm/drm_edid.c

2937

return clock;

sys/dev/drm/drm_edid.c

2981

if (!to_match->clock)

sys/dev/drm/drm_edid.c

2992

clock1 = cea_mode.clock;

sys/dev/drm/drm_edid.c

2995

if (abs(to_match->clock - clock1) > clock_tolerance &&

sys/dev/drm/drm_edid.c

2996

abs(to_match->clock - clock2) > clock_tolerance)

sys/dev/drm/drm_edid.c

3020

if (!to_match->clock)

sys/dev/drm/drm_edid.c

3031

clock1 = cea_mode.clock;

sys/dev/drm/drm_edid.c

3034

if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&

sys/dev/drm/drm_edid.c

3035

KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))

sys/dev/drm/drm_edid.c

3078

return hdmi_mode->clock;

sys/dev/drm/drm_edid.c

3089

if (!to_match->clock)

sys/dev/drm/drm_edid.c

3097

clock1 = hdmi_mode->clock;

sys/dev/drm/drm_edid.c

3100

if (abs(to_match->clock - clock1) > clock_tolerance &&

sys/dev/drm/drm_edid.c

3101

abs(to_match->clock - clock2) > clock_tolerance)

sys/dev/drm/drm_edid.c

3124

if (!to_match->clock)

sys/dev/drm/drm_edid.c

3132

clock1 = hdmi_mode->clock;

sys/dev/drm/drm_edid.c

3135

if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||

sys/dev/drm/drm_edid.c

3136

KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&

sys/dev/drm/drm_edid.c

3184

clock1 = cea_mode->clock;

sys/dev/drm/drm_edid.c

3189

if (mode->clock != clock1 && mode->clock != clock2)

sys/dev/drm/drm_edid.c

3203

if (mode->clock != clock1)

sys/dev/drm/drm_edid.c

3204

newmode->clock = clock1;

sys/dev/drm/drm_edid.c

3206

newmode->clock = clock2;

sys/dev/drm/drm_edid.c

3799

int clock1, clock2, clock;

sys/dev/drm/drm_edid.c

3811

clock1 = cea_mode->clock;

sys/dev/drm/drm_edid.c

3818

clock1 = cea_mode->clock;

sys/dev/drm/drm_edid.c

3826

if (abs(mode->clock - clock1) < abs(mode->clock - clock2))

sys/dev/drm/drm_edid.c

3827

clock = clock1;

sys/dev/drm/drm_edid.c

3829

clock = clock2;

sys/dev/drm/drm_edid.c

3831

if (mode->clock == clock)

sys/dev/drm/drm_edid.c

3835

type, vic, mode->clock, clock);

sys/dev/drm/drm_edid.c

3836

mode->clock = clock;

sys/dev/drm/drm_edid.c

4635

mode->clock = pixel_clock * 10;

sys/dev/drm/drm_modes.c

1114

if (mode->clock == 0)

sys/dev/drm/drm_modes.c

1336

diff = b->clock - a->clock;

sys/dev/drm/drm_modes.c

1641

out->clock = in->clock;

sys/dev/drm/drm_modes.c

1695

if (in->clock > INT_MAX || in->vrefresh > INT_MAX)

sys/dev/drm/drm_modes.c

1698

out->clock = in->clock;

sys/dev/drm/drm_modes.c

323

tmp -= drm_mode->clock % CVT_CLOCK_STEP;

sys/dev/drm/drm_modes.c

324

drm_mode->clock = tmp;

sys/dev/drm/drm_modes.c

515

drm_mode->clock = pixel_freq;

sys/dev/drm/drm_modes.c

597

dmode->clock = vm->pixelclock / 1000;

sys/dev/drm/drm_modes.c

637

vm->pixelclock = dmode->clock * 1000;

sys/dev/drm/drm_modes.c

761

calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */

sys/dev/drm/drm_modes.c

786

num = mode->clock * 1000;

sys/dev/drm/drm_modes.c

842

p->crtc_clock = p->clock;

sys/dev/drm/drm_modes.c

968

if (mode1->clock && mode2->clock)

sys/dev/drm/drm_modes.c

969

return KHZ2PICOS(mode1->clock) == KHZ2PICOS(mode2->clock);

sys/dev/drm/drm_modes.c

971

return mode1->clock == mode2->clock;

sys/dev/drm/i915/dvo_ch7017.c

251

if (mode->clock > 160000)

sys/dev/drm/i915/dvo_ch7017.c

271

if (mode->clock < 100000) {

sys/dev/drm/i915/dvo_ch7xxx.c

269

if (mode->clock > 165000)

sys/dev/drm/i915/dvo_ch7xxx.c

281

if (mode->clock <= 65000) {

sys/dev/drm/i915/dvo_ivch.c

318

if (mode->clock > 112000)

sys/dev/drm/i915/dvo_ns2501.c

539

if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||

sys/dev/drm/i915/dvo_ns2501.c

540

(mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||

sys/dev/drm/i915/dvo_ns2501.c

541

(mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {

sys/dev/drm/i915/i915_irq.c

896

u32 clock = mode->crtc_clock;

sys/dev/drm/i915/i915_irq.c

923

clock), 1000 * htotal);

sys/dev/drm/i915/intel_audio.c

121

crtc_state->port_clock == dp_aud_n_m[i].clock)

sys/dev/drm/i915/intel_audio.c

129

int clock;

sys/dev/drm/i915/intel_audio.c

152

int clock;

sys/dev/drm/i915/intel_audio.c

194

if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)

sys/dev/drm/i915/intel_audio.c

205

hdmi_audio_clock[i].clock,

sys/dev/drm/i915/intel_audio.c

220

adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {

sys/dev/drm/i915/intel_audio.c

69

int clock;

sys/dev/drm/i915/intel_bios.c

131

panel_fixed_mode->clock = dvo_timing->clock * 10;

sys/dev/drm/i915/intel_crt.c

314

if (mode->clock < 25000)

sys/dev/drm/i915/intel_crt.c

329

if (mode->clock > max_clock)

sys/dev/drm/i915/intel_crt.c

332

if (mode->clock > max_dotclk)

sys/dev/drm/i915/intel_crt.c

337

(ironlake_get_lanes_required(mode->clock, 270000, 24) > 2))

sys/dev/drm/i915/intel_ddi.c

1066

int clock = crtc->config->port_clock;

sys/dev/drm/i915/intel_ddi.c

1077

switch (clock) {

sys/dev/drm/i915/intel_ddi.c

1087

MISSING_CASE(clock);

sys/dev/drm/i915/intel_ddi.c

1708

struct dpll clock;

sys/dev/drm/i915/intel_ddi.c

1716

clock.m1 = 2;

sys/dev/drm/i915/intel_ddi.c

1717

clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;

sys/dev/drm/i915/intel_ddi.c

1719

clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;

sys/dev/drm/i915/intel_ddi.c

1720

clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;

sys/dev/drm/i915/intel_ddi.c

1721

clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;

sys/dev/drm/i915/intel_ddi.c

1722

clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;

sys/dev/drm/i915/intel_ddi.c

1724

return chv_calc_dpll_params(100000, &clock);

sys/dev/drm/i915/intel_display.c

10507

struct dpll clock;

sys/dev/drm/i915/intel_display.c

10516

clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

10518

clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;

sys/dev/drm/i915/intel_display.c

10519

clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

10521

clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

10522

clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

10527

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

sys/dev/drm/i915/intel_display.c

10530

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

sys/dev/drm/i915/intel_display.c

10535

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

sys/dev/drm/i915/intel_display.c

10539

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

sys/dev/drm/i915/intel_display.c

10549

port_clock = pnv_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

10551

port_clock = i9xx_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

10557

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

sys/dev/drm/i915/intel_display.c

10561

clock.p2 = 7;

sys/dev/drm/i915/intel_display.c

10563

clock.p2 = 14;

sys/dev/drm/i915/intel_display.c

10566

clock.p1 = 2;

sys/dev/drm/i915/intel_display.c

10568

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

sys/dev/drm/i915/intel_display.c

10572

clock.p2 = 4;

sys/dev/drm/i915/intel_display.c

10574

clock.p2 = 2;

sys/dev/drm/i915/intel_display.c

10577

port_clock = i9xx_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

15482

struct dpll clock = {

sys/dev/drm/i915/intel_display.c

15492

WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154);

sys/dev/drm/i915/intel_display.c

15495

pipe_name(pipe), clock.vco, clock.dot);

sys/dev/drm/i915/intel_display.c

15497

fp = i9xx_dpll_compute_fp(&clock);

sys/dev/drm/i915/intel_display.c

15500

((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |

sys/dev/drm/i915/intel_display.c

4507

int clock = crtc->config->base.adjusted_mode.crtc_clock;

sys/dev/drm/i915/intel_display.c

4525

clock << auxdiv);

sys/dev/drm/i915/intel_display.c

4544

clock,

sys/dev/drm/i915/intel_display.c

550

static int pnv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

552

clock->m = clock->m2 + 2;

sys/dev/drm/i915/intel_display.c

553

clock->p = clock->p1 * clock->p2;

sys/dev/drm/i915/intel_display.c

554

if (WARN_ON(clock->n == 0 || clock->p == 0))

sys/dev/drm/i915/intel_display.c

556

clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);

sys/dev/drm/i915/intel_display.c

557

clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/drm/i915/intel_display.c

559

return clock->dot;

sys/dev/drm/i915/intel_display.c

567

static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

569

clock->m = i9xx_dpll_compute_m(clock);

sys/dev/drm/i915/intel_display.c

570

clock->p = clock->p1 * clock->p2;

sys/dev/drm/i915/intel_display.c

571

if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))

sys/dev/drm/i915/intel_display.c

573

clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);

sys/dev/drm/i915/intel_display.c

574

clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/drm/i915/intel_display.c

576

return clock->dot;

sys/dev/drm/i915/intel_display.c

579

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

581

clock->m = clock->m1 * clock->m2;

sys/dev/drm/i915/intel_display.c

582

clock->p = clock->p1 * clock->p2;

sys/dev/drm/i915/intel_display.c

583

if (WARN_ON(clock->n == 0 || clock->p == 0))

sys/dev/drm/i915/intel_display.c

585

clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);

sys/dev/drm/i915/intel_display.c

586

clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/drm/i915/intel_display.c

588

return clock->dot / 5;

sys/dev/drm/i915/intel_display.c

591

int chv_calc_dpll_params(int refclk, struct dpll *clock)

sys/dev/drm/i915/intel_display.c

593

clock->m = clock->m1 * clock->m2;

sys/dev/drm/i915/intel_display.c

594

clock->p = clock->p1 * clock->p2;

sys/dev/drm/i915/intel_display.c

595

if (WARN_ON(clock->n == 0 || clock->p == 0))

sys/dev/drm/i915/intel_display.c

597

clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,

sys/dev/drm/i915/intel_display.c

598

clock->n << 22);

sys/dev/drm/i915/intel_display.c

599

clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);

sys/dev/drm/i915/intel_display.c

601

return clock->dot / 5;

sys/dev/drm/i915/intel_display.c

612

const struct dpll *clock)

sys/dev/drm/i915/intel_display.c

614

if (clock->n < limit->n.min || limit->n.max < clock->n)

sys/dev/drm/i915/intel_display.c

616

if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)

sys/dev/drm/i915/intel_display.c

618

if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)

sys/dev/drm/i915/intel_display.c

620

if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)

sys/dev/drm/i915/intel_display.c

625

if (clock->m1 <= clock->m2)

sys/dev/drm/i915/intel_display.c

630

if (clock->p < limit->p.min || limit->p.max < clock->p)

sys/dev/drm/i915/intel_display.c

632

if (clock->m < limit->m.min || limit->m.max < clock->m)

sys/dev/drm/i915/intel_display.c

636

if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)

sys/dev/drm/i915/intel_display.c

641

if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)

sys/dev/drm/i915/intel_display.c

689

struct dpll clock;

sys/dev/drm/i915/intel_display.c

694

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

sys/dev/drm/i915/intel_display.c

696

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

sys/dev/drm/i915/intel_display.c

697

clock.m1++) {

sys/dev/drm/i915/intel_display.c

698

for (clock.m2 = limit->m2.min;

sys/dev/drm/i915/intel_display.c

699

clock.m2 <= limit->m2.max; clock.m2++) {

sys/dev/drm/i915/intel_display.c

700

if (clock.m2 >= clock.m1)

sys/dev/drm/i915/intel_display.c

702

for (clock.n = limit->n.min;

sys/dev/drm/i915/intel_display.c

703

clock.n <= limit->n.max; clock.n++) {

sys/dev/drm/i915/intel_display.c

704

for (clock.p1 = limit->p1.min;

sys/dev/drm/i915/intel_display.c

705

clock.p1 <= limit->p1.max; clock.p1++) {

sys/dev/drm/i915/intel_display.c

708

i9xx_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

711

&clock))

sys/dev/drm/i915/intel_display.c

714

clock.p != match_clock->p)

sys/dev/drm/i915/intel_display.c

717

this_err = abs(clock.dot - target);

sys/dev/drm/i915/intel_display.c

719

*best_clock = clock;

sys/dev/drm/i915/intel_display.c

7298

struct dpll *clock = &crtc_state->dpll;

sys/dev/drm/i915/intel_display.c

7324

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

sys/dev/drm/i915/intel_display.c

7326

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7330

switch (clock->p2) {

sys/dev/drm/i915/intel_display.c

7372

struct dpll *clock = &crtc_state->dpll;

sys/dev/drm/i915/intel_display.c

7379

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7381

if (clock->p1 == 2)

sys/dev/drm/i915/intel_display.c

7384

dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

sys/dev/drm/i915/intel_display.c

7385

if (clock->p2 == 4)

sys/dev/drm/i915/intel_display.c

747

struct dpll clock;

sys/dev/drm/i915/intel_display.c

752

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

sys/dev/drm/i915/intel_display.c

754

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;

sys/dev/drm/i915/intel_display.c

7544

mode->clock = pipe_config->base.adjusted_mode.crtc_clock;

sys/dev/drm/i915/intel_display.c

755

clock.m1++) {

sys/dev/drm/i915/intel_display.c

756

for (clock.m2 = limit->m2.min;

sys/dev/drm/i915/intel_display.c

757

clock.m2 <= limit->m2.max; clock.m2++) {

sys/dev/drm/i915/intel_display.c

758

for (clock.n = limit->n.min;

sys/dev/drm/i915/intel_display.c

759

clock.n <= limit->n.max; clock.n++) {

sys/dev/drm/i915/intel_display.c

760

for (clock.p1 = limit->p1.min;

sys/dev/drm/i915/intel_display.c

761

clock.p1 <= limit->p1.max; clock.p1++) {

sys/dev/drm/i915/intel_display.c

764

pnv_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

767

&clock))

sys/dev/drm/i915/intel_display.c

770

clock.p != match_clock->p)

sys/dev/drm/i915/intel_display.c

773

this_err = abs(clock.dot - target);

sys/dev/drm/i915/intel_display.c

775

*best_clock = clock;

sys/dev/drm/i915/intel_display.c

7828

struct dpll clock;

sys/dev/drm/i915/intel_display.c

7840

clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;

sys/dev/drm/i915/intel_display.c

7841

clock.m2 = mdiv & DPIO_M2DIV_MASK;

sys/dev/drm/i915/intel_display.c

7842

clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;

sys/dev/drm/i915/intel_display.c

7843

clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;

sys/dev/drm/i915/intel_display.c

7844

clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;

sys/dev/drm/i915/intel_display.c

7846

pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

7939

struct dpll clock;

sys/dev/drm/i915/intel_display.c

7955

clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;

sys/dev/drm/i915/intel_display.c

7956

clock.m2 = (pll_dw0 & 0xff) << 22;

sys/dev/drm/i915/intel_display.c

7958

clock.m2 |= pll_dw2 & 0x3fffff;

sys/dev/drm/i915/intel_display.c

7959

clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;

sys/dev/drm/i915/intel_display.c

7960

clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;

sys/dev/drm/i915/intel_display.c

7961

clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;

sys/dev/drm/i915/intel_display.c

7963

pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

803

struct dpll clock;

sys/dev/drm/i915/intel_display.c

811

clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);

sys/dev/drm/i915/intel_display.c

815

for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {

sys/dev/drm/i915/intel_display.c

817

for (clock.m1 = limit->m1.max;

sys/dev/drm/i915/intel_display.c

818

clock.m1 >= limit->m1.min; clock.m1--) {

sys/dev/drm/i915/intel_display.c

819

for (clock.m2 = limit->m2.max;

sys/dev/drm/i915/intel_display.c

820

clock.m2 >= limit->m2.min; clock.m2--) {

sys/dev/drm/i915/intel_display.c

821

for (clock.p1 = limit->p1.max;

sys/dev/drm/i915/intel_display.c

822

clock.p1 >= limit->p1.min; clock.p1--) {

sys/dev/drm/i915/intel_display.c

825

i9xx_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

828

&clock))

sys/dev/drm/i915/intel_display.c

831

this_err = abs(clock.dot - target);

sys/dev/drm/i915/intel_display.c

833

*best_clock = clock;

sys/dev/drm/i915/intel_display.c

835

max_n = clock.n;

sys/dev/drm/i915/intel_display.c

898

struct dpll clock;

sys/dev/drm/i915/intel_display.c

909

for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {

sys/dev/drm/i915/intel_display.c

910

for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {

sys/dev/drm/i915/intel_display.c

911

for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;

sys/dev/drm/i915/intel_display.c

912

clock.p2 -= clock.p2 > 10 ? 2 : 1) {

sys/dev/drm/i915/intel_display.c

913

clock.p = clock.p1 * clock.p2;

sys/dev/drm/i915/intel_display.c

915

for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {

sys/dev/drm/i915/intel_display.c

918

clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,

sys/dev/drm/i915/intel_display.c

919

refclk * clock.m1);

sys/dev/drm/i915/intel_display.c

921

vlv_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

925

&clock))

sys/dev/drm/i915/intel_display.c

929

&clock,

sys/dev/drm/i915/intel_display.c

934

*best_clock = clock;

sys/dev/drm/i915/intel_display.c

959

struct dpll clock;

sys/dev/drm/i915/intel_display.c

971

clock.n = 1, clock.m1 = 2;

sys/dev/drm/i915/intel_display.c

974

for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {

sys/dev/drm/i915/intel_display.c

975

for (clock.p2 = limit->p2.p2_fast;

sys/dev/drm/i915/intel_display.c

976

clock.p2 >= limit->p2.p2_slow;

sys/dev/drm/i915/intel_display.c

977

clock.p2 -= clock.p2 > 10 ? 2 : 1) {

sys/dev/drm/i915/intel_display.c

980

clock.p = clock.p1 * clock.p2;

sys/dev/drm/i915/intel_display.c

982

m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *

sys/dev/drm/i915/intel_display.c

983

clock.n) << 22, refclk * clock.m1);

sys/dev/drm/i915/intel_display.c

985

if (m2 > INT_MAX/clock.m1)

sys/dev/drm/i915/intel_display.c

988

clock.m2 = m2;

sys/dev/drm/i915/intel_display.c

990

chv_calc_dpll_params(refclk, &clock);

sys/dev/drm/i915/intel_display.c

992

if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))

sys/dev/drm/i915/intel_display.c

995

if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,

sys/dev/drm/i915/intel_display.c

999

*best_clock = clock;

sys/dev/drm/i915/intel_dp.c

1270

int try, clock = 0;

sys/dev/drm/i915/intel_dp.c

1323

while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {

sys/dev/drm/i915/intel_dp.c

1772

if (pipe_config->port_clock == divisor[i].clock) {

sys/dev/drm/i915/intel_dp.c

1929

int bpp, clock, lane_count;

sys/dev/drm/i915/intel_dp.c

1936

for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {

sys/dev/drm/i915/intel_dp.c

1940

link_clock = intel_dp->common_rates[clock];

sys/dev/drm/i915/intel_dp.c

2108

intel_connector->panel.downclock_mode->clock,

sys/dev/drm/i915/intel_dp.c

56

int clock;

sys/dev/drm/i915/intel_dp.c

569

mode_rate = intel_dp_link_required(fixed_mode->clock, 18);

sys/dev/drm/i915/intel_dp.c

620

int target_clock = mode->clock;

sys/dev/drm/i915/intel_dp.c

636

target_clock = fixed_mode->clock;

sys/dev/drm/i915/intel_dp.c

648

if (mode->clock < 10000)

sys/dev/drm/i915/intel_dp_mst.c

385

mode_rate = intel_dp_link_required(mode->clock, bpp);

sys/dev/drm/i915/intel_dp_mst.c

388

if (mode->clock < 10000)

sys/dev/drm/i915/intel_dp_mst.c

394

if (mode_rate > max_rate || mode->clock > max_dotclk)

sys/dev/drm/i915/intel_dpll_mgr.c

1230

skl_ddi_calculate_wrpll(int clock /* in Hz */,

sys/dev/drm/i915/intel_dpll_mgr.c

1233

uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */

sys/dev/drm/i915/intel_dpll_mgr.c

1286

DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);

sys/dev/drm/i915/intel_dpll_mgr.c

1304

int clock)

sys/dev/drm/i915/intel_dpll_mgr.c

1317

if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))

sys/dev/drm/i915/intel_dpll_mgr.c

1340

skl_ddi_dp_set_dpll_hw_state(int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

1350

switch (clock / 2) {

sys/dev/drm/i915/intel_dpll_mgr.c

1381

int clock = crtc_state->port_clock;

sys/dev/drm/i915/intel_dpll_mgr.c

1388

bret = skl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);

sys/dev/drm/i915/intel_dpll_mgr.c

1394

bret = skl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);

sys/dev/drm/i915/intel_dpll_mgr.c

1660

int clock;

sys/dev/drm/i915/intel_dpll_mgr.c

1684

struct intel_crtc_state *crtc_state, int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

1694

if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {

sys/dev/drm/i915/intel_dpll_mgr.c

1696

clock, pipe_name(intel_crtc->pipe));

sys/dev/drm/i915/intel_dpll_mgr.c

1713

static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)

sys/dev/drm/i915/intel_dpll_mgr.c

1719

if (bxt_dp_clk_val[i].clock == clock) {

sys/dev/drm/i915/intel_dpll_mgr.c

1725

clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;

sys/dev/drm/i915/intel_dpll_mgr.c

1728

static bool bxt_ddi_set_dpll_hw_state(int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

1757

if (clock > 270000)

sys/dev/drm/i915/intel_dpll_mgr.c

1759

else if (clock > 135000)

sys/dev/drm/i915/intel_dpll_mgr.c

1761

else if (clock > 67000)

sys/dev/drm/i915/intel_dpll_mgr.c

1763

else if (clock > 33000)

sys/dev/drm/i915/intel_dpll_mgr.c

1795

bxt_ddi_dp_set_dpll_hw_state(int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

1800

bxt_ddi_dp_pll_dividers(clock, &clk_div);

sys/dev/drm/i915/intel_dpll_mgr.c

1802

return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);

sys/dev/drm/i915/intel_dpll_mgr.c

1807

struct intel_crtc_state *crtc_state, int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

1812

bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div);

sys/dev/drm/i915/intel_dpll_mgr.c

1814

return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);

sys/dev/drm/i915/intel_dpll_mgr.c

1825

int i, clock = crtc_state->port_clock;

sys/dev/drm/i915/intel_dpll_mgr.c

1828

!bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock,

sys/dev/drm/i915/intel_dpll_mgr.c

1833

!bxt_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state))

sys/dev/drm/i915/intel_dpll_mgr.c

2230

cnl_ddi_calculate_wrpll(int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2234

u32 afe_clock = clock * 5;

sys/dev/drm/i915/intel_dpll_mgr.c

2278

int clock)

sys/dev/drm/i915/intel_dpll_mgr.c

2286

if (!cnl_ddi_calculate_wrpll(clock, dev_priv, &wrpll_params))

sys/dev/drm/i915/intel_dpll_mgr.c

2307

cnl_ddi_dp_set_dpll_hw_state(int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2314

switch (clock / 2) {

sys/dev/drm/i915/intel_dpll_mgr.c

2353

int clock = crtc_state->port_clock;

sys/dev/drm/i915/intel_dpll_mgr.c

2360

bret = cnl_ddi_hdmi_pll_dividers(crtc, crtc_state, clock);

sys/dev/drm/i915/intel_dpll_mgr.c

2366

bret = cnl_ddi_dp_set_dpll_hw_state(clock, &dpll_hw_state);

sys/dev/drm/i915/intel_dpll_mgr.c

2472

static bool icl_calc_dp_combo_pll(struct drm_i915_private *dev_priv, int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2481

switch (clock) {

sys/dev/drm/i915/intel_dpll_mgr.c

2507

MISSING_CASE(clock);

sys/dev/drm/i915/intel_dpll_mgr.c

2514

static bool icl_calc_tbt_pll(struct drm_i915_private *dev_priv, int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2523

struct intel_encoder *encoder, int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2532

ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);

sys/dev/drm/i915/intel_dpll_mgr.c

2534

ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);

sys/dev/drm/i915/intel_dpll_mgr.c

2536

ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);

sys/dev/drm/i915/intel_dpll_mgr.c

2711

struct intel_encoder *encoder, int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2725

if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,

sys/dev/drm/i915/intel_dpll_mgr.c

2727

DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock);

sys/dev/drm/i915/intel_dpll_mgr.c

2738

clock);

sys/dev/drm/i915/intel_dpll_mgr.c

2883

int clock = crtc_state->port_clock;

sys/dev/drm/i915/intel_dpll_mgr.c

2891

ret = icl_calc_dpll_state(crtc_state, encoder, clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2901

ret = icl_calc_dpll_state(crtc_state, encoder, clock,

sys/dev/drm/i915/intel_dpll_mgr.c

2906

ret = icl_calc_mg_pll_state(crtc_state, encoder, clock,

sys/dev/drm/i915/intel_dpll_mgr.c

566

static unsigned hsw_wrpll_get_budget_for_freq(int clock)

sys/dev/drm/i915/intel_dpll_mgr.c

570

switch (clock) {

sys/dev/drm/i915/intel_dpll_mgr.c

700

hsw_ddi_calculate_wrpll(int clock /* in Hz */,

sys/dev/drm/i915/intel_dpll_mgr.c

708

freq2k = clock / 100;

sys/dev/drm/i915/intel_dpll_mgr.c

710

budget = hsw_wrpll_get_budget_for_freq(clock);

sys/dev/drm/i915/intel_dpll_mgr.c

764

static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock,

sys/dev/drm/i915/intel_dpll_mgr.c

772

hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);

sys/dev/drm/i915/intel_dpll_mgr.c

790

hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock)

sys/dev/drm/i915/intel_dpll_mgr.c

796

switch (clock / 2) {

sys/dev/drm/i915/intel_dpll_mgr.c

807

DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock);

sys/dev/drm/i915/intel_dpll_mgr.c

824

int clock = crtc_state->port_clock;

sys/dev/drm/i915/intel_dpll_mgr.c

830

pll = hsw_ddi_hdmi_get_dpll(clock, crtc, crtc_state);

sys/dev/drm/i915/intel_dpll_mgr.c

832

pll = hsw_ddi_dp_get_dpll(encoder, clock);

sys/dev/drm/i915/intel_dsi_vbt.c

544

pclk = mode->clock;

sys/dev/drm/i915/intel_dvo.c

216

int target_clock = mode->clock;

sys/dev/drm/i915/intel_dvo.c

229

target_clock = fixed_mode->clock;

sys/dev/drm/i915/intel_hdmi.c

1523

int clock, bool respect_downstream_limits,

sys/dev/drm/i915/intel_hdmi.c

1528

if (clock < 25000)

sys/dev/drm/i915/intel_hdmi.c

1530

if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))

sys/dev/drm/i915/intel_hdmi.c

1534

if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)

sys/dev/drm/i915/intel_hdmi.c

1538

if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)

sys/dev/drm/i915/intel_hdmi.c

1552

int clock;

sys/dev/drm/i915/intel_hdmi.c

1560

clock = mode->clock;

sys/dev/drm/i915/intel_hdmi.c

1563

clock *= 2;

sys/dev/drm/i915/intel_hdmi.c

1565

if (clock > max_dotclk)

sys/dev/drm/i915/intel_hdmi.c

1569

clock *= 2;

sys/dev/drm/i915/intel_hdmi.c

1572

clock /= 2;

sys/dev/drm/i915/intel_hdmi.c

1575

status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);

sys/dev/drm/i915/intel_hdmi.c

1580

status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,

sys/dev/drm/i915/intel_hdmi.c

1585

status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,

sys/dev/drm/i915/intel_lvds.c

386

if (fixed_mode->clock > max_pixclk)

sys/dev/drm/i915/intel_lvds.c

806

if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock

sys/dev/drm/i915/intel_panel.c

1345

u32 mul, clock;

sys/dev/drm/i915/intel_panel.c

1353

clock = MHz(135); /* LPT:H */

sys/dev/drm/i915/intel_panel.c

1355

clock = MHz(24); /* LPT:LP */

sys/dev/drm/i915/intel_panel.c

1357

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);

sys/dev/drm/i915/intel_panel.c

1382

int clock;

sys/dev/drm/i915/intel_panel.c

1385

clock = KHz(dev_priv->rawclk_freq);

sys/dev/drm/i915/intel_panel.c

1387

clock = KHz(dev_priv->cdclk.hw.cdclk);

sys/dev/drm/i915/intel_panel.c

1389

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);

sys/dev/drm/i915/intel_panel.c

1400

int clock;

sys/dev/drm/i915/intel_panel.c

1403

clock = KHz(dev_priv->rawclk_freq);

sys/dev/drm/i915/intel_panel.c

1405

clock = KHz(dev_priv->cdclk.hw.cdclk);

sys/dev/drm/i915/intel_panel.c

1407

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);

sys/dev/drm/i915/intel_panel.c

1418

int mul, clock;

sys/dev/drm/i915/intel_panel.c

1422

clock = KHz(19200);

sys/dev/drm/i915/intel_panel.c

1424

clock = MHz(25);

sys/dev/drm/i915/intel_panel.c

1427

clock = KHz(dev_priv->rawclk_freq);

sys/dev/drm/i915/intel_panel.c

1431

return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);

sys/dev/drm/i915/intel_panel.c

66

temp_downclock = fixed_mode->clock;

sys/dev/drm/i915/intel_panel.c

85

if (scan->clock < temp_downclock) {

sys/dev/drm/i915/intel_panel.c

90

temp_downclock = scan->clock;

sys/dev/drm/i915/intel_panel.c

96

if (temp_downclock < fixed_mode->clock)

sys/dev/drm/i915/intel_pm.c

1099

unsigned int clock, htotal, cpp, width, wm;

sys/dev/drm/i915/intel_pm.c

1124

clock = adjusted_mode->crtc_clock;

sys/dev/drm/i915/intel_pm.c

1133

wm = intel_wm_method2(clock, htotal, width, cpp, latency);

sys/dev/drm/i915/intel_pm.c

1136

wm = intel_wm_method1(clock, cpp, latency);

sys/dev/drm/i915/intel_pm.c

1140

small = intel_wm_method1(clock, cpp, latency);

sys/dev/drm/i915/intel_pm.c

1141

large = intel_wm_method2(clock, htotal, width, cpp, latency);

sys/dev/drm/i915/intel_pm.c

1608

unsigned int clock, htotal, cpp, width, wm;

sys/dev/drm/i915/intel_pm.c

1617

clock = adjusted_mode->crtc_clock;

sys/dev/drm/i915/intel_pm.c

1630

wm = vlv_wm_method2(clock, htotal, width, cpp,

sys/dev/drm/i915/intel_pm.c

2205

int clock = adjusted_mode->crtc_clock;

sys/dev/drm/i915/intel_pm.c

2211

entries = intel_wm_method2(clock, htotal,

sys/dev/drm/i915/intel_pm.c

2221

entries = intel_wm_method2(clock, htotal,

sys/dev/drm/i915/intel_pm.c

2361

int clock = adjusted_mode->crtc_clock;

sys/dev/drm/i915/intel_pm.c

2372

entries = intel_wm_method2(clock, htotal, hdisplay, cpp,

sys/dev/drm/i915/intel_pm.c

865

int clock = adjusted_mode->crtc_clock;

sys/dev/drm/i915/intel_pm.c

868

wm = intel_calculate_wm(clock, &pineview_display_wm,

sys/dev/drm/i915/intel_pm.c

878

wm = intel_calculate_wm(clock, &pineview_cursor_wm,

sys/dev/drm/i915/intel_pm.c

887

wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,

sys/dev/drm/i915/intel_pm.c

896

wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,

sys/dev/drm/i915/intel_sdvo.c

1069

mode->clock / 10,

sys/dev/drm/i915/intel_sdvo.c

1087

struct dpll *clock = &pipe_config->dpll;

sys/dev/drm/i915/intel_sdvo.c

1094

clock->p1 = 2;

sys/dev/drm/i915/intel_sdvo.c

1095

clock->p2 = 10;

sys/dev/drm/i915/intel_sdvo.c

1096

clock->n = 3;

sys/dev/drm/i915/intel_sdvo.c

1097

clock->m1 = 16;

sys/dev/drm/i915/intel_sdvo.c

1098

clock->m2 = 8;

sys/dev/drm/i915/intel_sdvo.c

1100

clock->p1 = 1;

sys/dev/drm/i915/intel_sdvo.c

1101

clock->p2 = 10;

sys/dev/drm/i915/intel_sdvo.c

1102

clock->n = 6;

sys/dev/drm/i915/intel_sdvo.c

1103

clock->m1 = 12;

sys/dev/drm/i915/intel_sdvo.c

1104

clock->m2 = 8;

sys/dev/drm/i915/intel_sdvo.c

1637

if (intel_sdvo->pixel_clock_min > mode->clock)

sys/dev/drm/i915/intel_sdvo.c

1640

if (intel_sdvo->pixel_clock_max < mode->clock)

sys/dev/drm/i915/intel_sdvo.c

1643

if (mode->clock > max_dotclk)

sys/dev/drm/i915/intel_sdvo.c

756

uint16_t clock,

sys/dev/drm/i915/intel_sdvo.c

763

args.clock = clock;

sys/dev/drm/i915/intel_sdvo.c

817

mode_clock = mode->clock;

sys/dev/drm/i915/intel_sdvo.c

819

dtd->part1.clock = mode_clock;

sys/dev/drm/i915/intel_sdvo.c

875

mode.clock = dtd->part1.clock * 10;

sys/dev/drm/i915/intel_sdvo_regs.h

105

u16 clock;

sys/dev/drm/i915/intel_sdvo_regs.h

72

u16 clock; /* pixel clock, in 10kHz units */

sys/dev/drm/i915/intel_tv.c

1116

.clock = 107520,

sys/dev/drm/i915/intel_tv.c

1369

mode_ptr->clock = (int) tmp;

sys/dev/drm/i915/intel_tv.c

308

u32 clock;

sys/dev/drm/i915/intel_tv.c

380

.clock = 108000,

sys/dev/drm/i915/intel_tv.c

423

.clock = 108000,

sys/dev/drm/i915/intel_tv.c

465

.clock = 108000,

sys/dev/drm/i915/intel_tv.c

508

.clock = 108000,

sys/dev/drm/i915/intel_tv.c

552

.clock = 108000,

sys/dev/drm/i915/intel_tv.c

597

.clock = 108000,

sys/dev/drm/i915/intel_tv.c

639

.clock = 107520,

sys/dev/drm/i915/intel_tv.c

663

.clock = 107520,

sys/dev/drm/i915/intel_tv.c

687

.clock = 148800,

sys/dev/drm/i915/intel_tv.c

711

.clock = 148800,

sys/dev/drm/i915/intel_tv.c

736

.clock = 148800,

sys/dev/drm/i915/intel_tv.c

762

.clock = 148800,

sys/dev/drm/i915/intel_tv.c

852

if (mode->clock > max_dotclk)

sys/dev/drm/i915/intel_tv.c

888

adjusted_mode->crtc_clock = tv_mode->clock;

sys/dev/drm/i915/intel_vbt_defs.h

524

u16 clock; /**< In 10khz */

sys/dev/drm/i915/vlv_dsi.c

1293

if (fixed_mode->clock > max_dotclk)

sys/dev/drm/include/drm/drm_dp_mst_helper.h

594

int drm_dp_calc_pbn_mode(int clock, int bpp);

sys/dev/drm/include/drm/drm_modes.h

135

.name = nm, .status = 0, .type = (t), .clock = (c), \

sys/dev/drm/include/drm/drm_modes.h

278

int clock; /* in kHz */

sys/dev/drm/include/drm/drm_modes.h

439

(m)->base.id, (m)->name, (m)->vrefresh, (m)->clock, \

sys/dev/drm/include/uapi/drm/drm_mode.h

214

__u32 clock;

sys/dev/drm/radeon/atombios_crtc.c

1026

mode->clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

1039

mode->clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

1047

mode->clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

1067

u32 pll_clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

1068

u32 clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

1077

clock = radeon_crtc->adjusted_clock;

sys/dev/drm/radeon/atombios_crtc.c

1081

pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/atombios_crtc.c

1084

pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/atombios_crtc.c

1089

pll = &rdev->clock.dcpll;

sys/dev/drm/radeon/atombios_crtc.c

1113

encoder_mode, radeon_encoder->encoder_id, clock,

sys/dev/drm/radeon/atombios_crtc.c

1800

if ((crtc->mode.clock == test_crtc->mode.clock) &&

sys/dev/drm/radeon/atombios_crtc.c

1859

if (rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_crtc.c

1907

if (rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_crtc.c

1933

if (rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_crtc.c

1956

if (rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_crtc.c

2009

atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);

sys/dev/drm/radeon/atombios_crtc.c

2014

rdev->clock.default_dispclk);

sys/dev/drm/radeon/atombios_crtc.c

2018

atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);

sys/dev/drm/radeon/atombios_crtc.c

564

u32 adjusted_clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

566

u32 dp_clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

567

u32 clock = mode->clock;

sys/dev/drm/radeon/atombios_crtc.c

569

bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);

sys/dev/drm/radeon/atombios_crtc.c

581

if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */

sys/dev/drm/radeon/atombios_crtc.c

595

if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)

sys/dev/drm/radeon/atombios_crtc.c

600

if (mode->clock > 200000) /* range limits??? */

sys/dev/drm/radeon/atombios_crtc.c

641

adjusted_clock = mode->clock * 2;

sys/dev/drm/radeon/atombios_crtc.c

660

clock = (clock * 5) / 4;

sys/dev/drm/radeon/atombios_crtc.c

663

clock = (clock * 3) / 2;

sys/dev/drm/radeon/atombios_crtc.c

666

clock = clock * 2;

sys/dev/drm/radeon/atombios_crtc.c

692

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

704

args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

825

u32 clock,

sys/dev/drm/radeon/atombios_crtc.c

850

if (clock == ATOM_DISABLE)

sys/dev/drm/radeon/atombios_crtc.c

852

args.v1.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

862

args.v2.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

872

args.v3.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

889

args.v5.usPixelClock = cpu_to_le16(clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

918

args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);

sys/dev/drm/radeon/atombios_crtc.c

986

radeon_connector->pixelclock_for_modeset = mode->clock;

sys/dev/drm/radeon/atombios_dp.c

466

mode->clock,

sys/dev/drm/radeon/atombios_dp.c

484

if ((mode->clock > 340000) &&

sys/dev/drm/radeon/atombios_dp.c

493

mode->clock,

sys/dev/drm/radeon/atombios_encoders.c

1277

if (is_dp && rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_encoders.c

1337

if (rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_encoders.c

1404

if (is_dp && rdev->clock.dp_extclk)

sys/dev/drm/radeon/atombios_encoders.c

2337

radeon_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/drm/radeon/btc_dpm.c

1174

u32 i, clock = 0;

sys/dev/drm/radeon/btc_dpm.c

1177

*max_clock = clock;

sys/dev/drm/radeon/btc_dpm.c

1182

if (clock < table->entries[i].clk)

sys/dev/drm/radeon/btc_dpm.c

1183

clock = table->entries[i].clk;

sys/dev/drm/radeon/btc_dpm.c

1185

*max_clock = clock;

sys/dev/drm/radeon/btc_dpm.c

1189

u32 clock, u16 max_voltage, u16 *voltage)

sys/dev/drm/radeon/btc_dpm.c

1197

if (clock <= table->entries[i].clk) {

sys/dev/drm/radeon/btc_dpm.c

2213

rdev->clock.current_dispclk, max_limits->vddc, &ps->low.vddc);

sys/dev/drm/radeon/btc_dpm.c

2222

rdev->clock.current_dispclk, max_limits->vddc, &ps->medium.vddc);

sys/dev/drm/radeon/btc_dpm.c

2231

rdev->clock.current_dispclk, max_limits->vddc, &ps->high.vddc);

sys/dev/drm/radeon/btc_dpm.h

48

u32 clock, u16 max_voltage, u16 *voltage);

sys/dev/drm/radeon/ci_dpm.c

2024

u32 ref_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

2467

u32 clock, u32 *voltage)

sys/dev/drm/radeon/ci_dpm.c

2475

if (allowed_clock_voltage_table->entries[i].clk >= clock) {

sys/dev/drm/radeon/ci_dpm.c

2865

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

3044

table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

3203

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ci_dpm.c

3832

if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)

sys/dev/drm/radeon/cik.c

1702

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/cik.c

9276

(u32)mode->clock);

sys/dev/drm/radeon/cik.c

9278

(u32)mode->clock);

sys/dev/drm/radeon/cik.c

9293

wm_high.disp_clk = mode->clock;

sys/dev/drm/radeon/cik.c

9333

wm_low.disp_clk = mode->clock;

sys/dev/drm/radeon/cik.c

9431

uint64_t clock;

sys/dev/drm/radeon/cik.c

9435

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/radeon/cik.c

9438

return clock;

sys/dev/drm/radeon/cik.c

9441

static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/drm/radeon/cik.c

9449

clock, false, &dividers);

sys/dev/drm/radeon/cypress_dpm.c

443

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/cypress_dpm.c

559

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/dce3_1_afmt.c

123

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/dce3_1_afmt.c

125

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/dce3_1_afmt.c

129

unsigned int max_ratio = clock / 24000;

sys/dev/drm/radeon/dce3_1_afmt.c

166

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/drm/radeon/dce3_1_afmt.c

173

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/dce6_afmt.c

282

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/dce6_afmt.c

284

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/dce6_afmt.c

299

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/drm/radeon/dce6_afmt.c

303

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/dce6_afmt.c

305

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/dce6_afmt.c

327

clock = clock * 100 / div;

sys/dev/drm/radeon/dce6_afmt.c

330

WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/dce6_afmt.c

333

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/evergreen.c

1127

static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,

sys/dev/drm/radeon/evergreen.c

1134

clock, false, &dividers);

sys/dev/drm/radeon/evergreen.c

2153

(u32)mode->clock);

sys/dev/drm/radeon/evergreen.c

2155

(u32)mode->clock);

sys/dev/drm/radeon/evergreen.c

2172

wm_high.disp_clk = mode->clock;

sys/dev/drm/radeon/evergreen.c

2199

wm_low.disp_clk = mode->clock;

sys/dev/drm/radeon/evergreen.c

2238

b.full = dfixed_const(mode->clock);

sys/dev/drm/radeon/evergreen.c

2250

b.full = dfixed_const(mode->clock);

sys/dev/drm/radeon/evergreen_hdmi.c

243

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/evergreen_hdmi.c

245

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/evergreen_hdmi.c

247

unsigned int max_ratio = clock / 24000;

sys/dev/drm/radeon/evergreen_hdmi.c

284

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/drm/radeon/evergreen_hdmi.c

288

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/evergreen_hdmi.c

290

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/evergreen_hdmi.c

318

clock = 100 * clock / div;

sys/dev/drm/radeon/evergreen_hdmi.c

322

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/ni_dpm.c

2010

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/ni_dpm.c

2240

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/ni_dpm.c

3970

pl->mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/ni_dpm.c

3971

pl->sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/ni_dpm.c

883

rdev->clock.current_dispclk,

sys/dev/drm/radeon/r100.c

3283

pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */

sys/dev/drm/radeon/r100.c

3290

pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */

sys/dev/drm/radeon/r600.c

190

return rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/r600.c

217

if (rdev->clock.spll.reference_freq == 10000)

sys/dev/drm/radeon/r600.c

4626

uint64_t clock;

sys/dev/drm/radeon/r600.c

4630

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/radeon/r600.c

4633

return clock;

sys/dev/drm/radeon/r600_dpm.c

168

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/drm/radeon/r600_dpm.c

175

vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock;

sys/dev/drm/radeon/r600_dpm.c

194

if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {

sys/dev/drm/radeon/r600_hdmi.c

319

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/r600_hdmi.c

321

struct radeon_crtc *crtc, unsigned int clock)

sys/dev/drm/radeon/r600_hdmi.c

337

WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);

sys/dev/drm/radeon/r600_hdmi.c

341

WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);

sys/dev/drm/radeon/radeon.h

2376

struct radeon_clock clock;

sys/dev/drm/radeon/radeon.h

2921

u32 clock;

sys/dev/drm/radeon/radeon.h

2934

extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);

sys/dev/drm/radeon/radeon.h

298

u32 clock,

sys/dev/drm/radeon/radeon.h

302

u32 clock,

sys/dev/drm/radeon/radeon_asic.h

403

void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);

sys/dev/drm/radeon/radeon_asic.h

406

void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);

sys/dev/drm/radeon/radeon_atombios.c

1121

rdev->clock.vco_freq =

sys/dev/drm/radeon/radeon_atombios.c

1133

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_atombios.c

1134

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_atombios.c

1135

struct radeon_pll *dcpll = &rdev->clock.dcpll;

sys/dev/drm/radeon/radeon_atombios.c

1136

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/drm/radeon/radeon_atombios.c

1137

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/drm/radeon/radeon_atombios.c

1241

rdev->clock.default_sclk =

sys/dev/drm/radeon/radeon_atombios.c

1243

rdev->clock.default_mclk =

sys/dev/drm/radeon/radeon_atombios.c

1247

rdev->clock.default_dispclk =

sys/dev/drm/radeon/radeon_atombios.c

1249

if (rdev->clock.default_dispclk == 0) {

sys/dev/drm/radeon/radeon_atombios.c

1251

rdev->clock.default_dispclk = 60000; /* 600 Mhz */

sys/dev/drm/radeon/radeon_atombios.c

1253

rdev->clock.default_dispclk = 54000; /* 540 Mhz */

sys/dev/drm/radeon/radeon_atombios.c

1255

rdev->clock.default_dispclk = 60000; /* 600 Mhz */

sys/dev/drm/radeon/radeon_atombios.c

1258

if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {

sys/dev/drm/radeon/radeon_atombios.c

1260

rdev->clock.default_dispclk / 100);

sys/dev/drm/radeon/radeon_atombios.c

1261

rdev->clock.default_dispclk = 60000;

sys/dev/drm/radeon/radeon_atombios.c

1263

rdev->clock.dp_extclk =

sys/dev/drm/radeon/radeon_atombios.c

1265

rdev->clock.current_dispclk = rdev->clock.default_dispclk;

sys/dev/drm/radeon/radeon_atombios.c

1269

rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);

sys/dev/drm/radeon/radeon_atombios.c

1270

if (rdev->clock.max_pixel_clock == 0)

sys/dev/drm/radeon/radeon_atombios.c

1271

rdev->clock.max_pixel_clock = 40000;

sys/dev/drm/radeon/radeon_atombios.c

1278

rdev->clock.vco_freq =

sys/dev/drm/radeon/radeon_atombios.c

1281

rdev->clock.vco_freq = rdev->clock.current_dispclk;

sys/dev/drm/radeon/radeon_atombios.c

1285

rdev->clock.vco_freq = rdev->clock.current_dispclk;

sys/dev/drm/radeon/radeon_atombios.c

1287

if (rdev->clock.vco_freq == 0)

sys/dev/drm/radeon/radeon_atombios.c

1288

rdev->clock.vco_freq = 360000; /* 3.6 GHz */

sys/dev/drm/radeon/radeon_atombios.c

1508

int id, u32 clock)

sys/dev/drm/radeon/radeon_atombios.c

1542

(clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {

sys/dev/drm/radeon/radeon_atombios.c

1560

(clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {

sys/dev/drm/radeon/radeon_atombios.c

1582

(clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {

sys/dev/drm/radeon/radeon_atombios.c

1641

lvds->native_mode.clock =

sys/dev/drm/radeon/radeon_atombios.c

1835

mode->crtc_clock = mode->clock =

sys/dev/drm/radeon/radeon_atombios.c

1879

mode->crtc_clock = mode->clock =

sys/dev/drm/radeon/radeon_atombios.c

2459

rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_atombios.c

2461

rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_atombios.c

2629

rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_atombios.c

2631

rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_atombios.c

2723

rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_atombios.c

2725

rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_atombios.c

2793

rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_atombios.c

2794

rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_atombios.c

2829

u32 clock,

sys/dev/drm/radeon/radeon_atombios.c

2847

args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/radeon/radeon_atombios.c

2861

args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/radeon/radeon_atombios.c

2876

args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/drm/radeon/radeon_atombios.c

2894

args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

sys/dev/drm/radeon/radeon_atombios.c

2915

args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/radeon/radeon_atombios.c

2926

args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/radeon/radeon_atombios.c

2945

u32 clock,

sys/dev/drm/radeon/radeon_atombios.c

2964

args.ulClock = cpu_to_le32(clock); /* 10 khz */

sys/dev/drm/radeon/radeon_audio.c

501

static void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock)

sys/dev/drm/radeon/radeon_audio.c

508

radeon_encoder->audio->set_dto(rdev, crtc, clock);

sys/dev/drm/radeon/radeon_audio.c

559

static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq)

sys/dev/drm/radeon/radeon_audio.c

566

cts = clock * 1000;

sys/dev/drm/radeon/radeon_audio.c

596

static const struct radeon_hdmi_acr* radeon_audio_acr(unsigned int clock)

sys/dev/drm/radeon/radeon_audio.c

618

if (hdmi_predefined_acr[i].clock == clock)

sys/dev/drm/radeon/radeon_audio.c

622

radeon_audio_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000);

sys/dev/drm/radeon/radeon_audio.c

623

radeon_audio_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100);

sys/dev/drm/radeon/radeon_audio.c

624

radeon_audio_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000);

sys/dev/drm/radeon/radeon_audio.c

632

static void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock)

sys/dev/drm/radeon/radeon_audio.c

634

const struct radeon_hdmi_acr *acr = radeon_audio_acr(clock);

sys/dev/drm/radeon/radeon_audio.c

721

radeon_audio_set_dto(encoder, mode->clock);

sys/dev/drm/radeon/radeon_audio.c

724

radeon_audio_update_acr(encoder, mode->clock);

sys/dev/drm/radeon/radeon_audio.c

73

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

75

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

759

radeon_audio_set_dto(encoder, rdev->clock.vco_freq * 10);

sys/dev/drm/radeon/radeon_audio.c

77

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

79

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

81

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.c

83

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_audio.h

55

struct radeon_crtc *crtc, unsigned int clock);

sys/dev/drm/radeon/radeon_clocks.c

105

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_clocks.c

106

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_clocks.c

107

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/drm/radeon/radeon_clocks.c

108

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/drm/radeon/radeon_clocks.c

144

rdev->clock.max_pixel_clock = 35000;

sys/dev/drm/radeon/radeon_clocks.c

153

rdev->clock.default_sclk = (*val) / 10;

sys/dev/drm/radeon/radeon_clocks.c

155

rdev->clock.default_sclk =

sys/dev/drm/radeon/radeon_clocks.c

160

rdev->clock.default_mclk = (*val) / 10;

sys/dev/drm/radeon/radeon_clocks.c

162

rdev->clock.default_mclk =

sys/dev/drm/radeon/radeon_clocks.c

179

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_clocks.c

180

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_clocks.c

181

struct radeon_pll *dcpll = &rdev->clock.dcpll;

sys/dev/drm/radeon/radeon_clocks.c

182

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/drm/radeon/radeon_clocks.c

183

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/drm/radeon/radeon_clocks.c

224

rdev->clock.max_pixel_clock = 35000;

sys/dev/drm/radeon/radeon_clocks.c

267

rdev->clock.default_sclk =

sys/dev/drm/radeon/radeon_clocks.c

269

rdev->clock.default_mclk =

sys/dev/drm/radeon/radeon_clocks.c

336

if (!rdev->clock.default_sclk)

sys/dev/drm/radeon/radeon_clocks.c

337

rdev->clock.default_sclk = radeon_get_engine_clock(rdev);

sys/dev/drm/radeon/radeon_clocks.c

338

if ((!rdev->clock.default_mclk) && rdev->asic->pm.get_memory_clock)

sys/dev/drm/radeon/radeon_clocks.c

339

rdev->clock.default_mclk = radeon_get_memory_clock(rdev);

sys/dev/drm/radeon/radeon_clocks.c

341

rdev->pm.current_sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_clocks.c

342

rdev->pm.current_mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_clocks.c

351

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/drm/radeon/radeon_clocks.c

38

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/drm/radeon/radeon_clocks.c

68

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/drm/radeon/radeon_combios.c

1272

lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;

sys/dev/drm/radeon/radeon_combios.c

2801

rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_combios.c

2802

rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_combios.c

729

struct radeon_pll *p1pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_combios.c

730

struct radeon_pll *p2pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_combios.c

731

struct radeon_pll *spll = &rdev->clock.spll;

sys/dev/drm/radeon/radeon_combios.c

732

struct radeon_pll *mpll = &rdev->clock.mpll;

sys/dev/drm/radeon/radeon_combios.c

795

rdev->clock.default_sclk = sclk;

sys/dev/drm/radeon/radeon_combios.c

796

rdev->clock.default_mclk = mclk;

sys/dev/drm/radeon/radeon_combios.c

799

rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);

sys/dev/drm/radeon/radeon_combios.c

801

rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */

sys/dev/drm/radeon/radeon_connectors.c

1017

if ((mode->clock / 10) > rdev->clock.max_pixel_clock)

sys/dev/drm/radeon/radeon_connectors.c

1501

(mode->clock > 135000))

sys/dev/drm/radeon/radeon_connectors.c

1504

if (radeon_connector->use_digital && (mode->clock > 165000)) {

sys/dev/drm/radeon/radeon_connectors.c

1511

if (mode->clock > 340000)

sys/dev/drm/radeon/radeon_connectors.c

1521

if ((mode->clock / 10) > rdev->clock.max_pixel_clock)

sys/dev/drm/radeon/radeon_connectors.c

1656

(rdev->clock.default_dispclk >= 53900) &&

sys/dev/drm/radeon/radeon_connectors.c

1821

if (mode->clock > 340000)

sys/dev/drm/radeon/radeon_connectors.c

1824

if (mode->clock > 165000)

sys/dev/drm/radeon/radeon_connectors.c

408

radeon_encoder->native_mode.clock = 0;

sys/dev/drm/radeon/radeon_connectors.c

477

native_mode->clock != 0) {

sys/dev/drm/radeon/radeon_connectors.c

737

(radeon_encoder->native_mode.clock == 0))

sys/dev/drm/radeon/radeon_connectors.c

792

if (!native_mode->clock) {

sys/dev/drm/radeon/radeon_connectors.c

804

if (!native_mode->clock) {

sys/dev/drm/radeon/radeon_dp_mst.c

216

if (mode->clock < 10000)

sys/dev/drm/radeon/radeon_dp_mst.c

369

radeon_connector->pixelclock_for_modeset = mode->clock;

sys/dev/drm/radeon/radeon_dp_mst.c

523

mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp);

sys/dev/drm/radeon/radeon_encoders.c

326

adjusted_mode->clock = native_mode->clock;

sys/dev/drm/radeon/radeon_i2c.c

208

static void set_clock(void *i2c_priv, int clock)

sys/dev/drm/radeon/radeon_i2c.c

217

val |= clock ? 0 : rec->en_clk_mask;

sys/dev/drm/radeon/radeon_kms.c

338

*value = rdev->clock.spll.reference_freq * 10;

sys/dev/drm/radeon/radeon_legacy_crtc.c

771

pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_legacy_crtc.c

773

pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_legacy_crtc.c

777

if (mode->clock > 200000) /* range limits??? */

sys/dev/drm/radeon/radeon_legacy_crtc.c

815

radeon_compute_pll_legacy(pll, mode->clock,

sys/dev/drm/radeon/radeon_legacy_encoders.c

194

radeon_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/drm/radeon/radeon_legacy_encoders.c

807

if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {

sys/dev/drm/radeon/radeon_legacy_encoders.c

958

radeon_encoder->pixel_clock = adjusted_mode->clock;

sys/dev/drm/radeon/radeon_legacy_tv.c

246

pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_legacy_tv.c

248

pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_legacy_tv.c

438

pll = &rdev->clock.p2pll;

sys/dev/drm/radeon/radeon_legacy_tv.c

440

pll = &rdev->clock.p1pll;

sys/dev/drm/radeon/radeon_mode.h

811

int id, u32 clock);

sys/dev/drm/radeon/radeon_pm.c

1364

rdev->pm.default_sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_pm.c

1365

rdev->pm.default_mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_pm.c

1366

rdev->pm.current_sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_pm.c

1367

rdev->pm.current_mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_pm.c

1430

rdev->pm.default_sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_pm.c

1431

rdev->pm.default_mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_pm.c

1432

rdev->pm.current_sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/radeon_pm.c

1433

rdev->pm.current_mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/radeon_uvd.c

969

unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rs690.c

326

a.full = dfixed_const(mode->clock);

sys/dev/drm/radeon/rs690.c

84

else if (rdev->clock.default_mclk) {

sys/dev/drm/radeon/rs690.c

85

rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);

sys/dev/drm/radeon/rs690.c

98

else if (rdev->clock.default_mclk)

sys/dev/drm/radeon/rs690.c

99

rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);

sys/dev/drm/radeon/rs780_dpm.c

1012

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/drm/radeon/rs780_dpm.c

782

ps->sclk_low = rdev->clock.default_sclk;

sys/dev/drm/radeon/rs780_dpm.c

783

ps->sclk_high = rdev->clock.default_sclk;

sys/dev/drm/radeon/rs780_dpm.c

990

u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) /

sys/dev/drm/radeon/rv515.c

1001

a.full = dfixed_const(mode->clock);

sys/dev/drm/radeon/rv6xx_dpm.c

140

u32 clock, struct rv6xx_sclk_stepping *step)

sys/dev/drm/radeon/rv6xx_dpm.c

146

clock, false, &dividers);

sys/dev/drm/radeon/rv6xx_dpm.c

155

step->vco_frequency = clock * step->post_divider;

sys/dev/drm/radeon/rv6xx_dpm.c

164

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

1867

pl->mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/rv6xx_dpm.c

1868

pl->sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/rv6xx_dpm.c

298

u32 clock, u32 index)

sys/dev/drm/radeon/rv6xx_dpm.c

302

rv6xx_convert_clock_to_stepping(rdev, clock, &step);

sys/dev/drm/radeon/rv6xx_dpm.c

429

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

550

u32 clock, enum r600_power_level level)

sys/dev/drm/radeon/rv6xx_dpm.c

552

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

560

if (clock && pi->sclk_ss) {

sys/dev/drm/radeon/rv6xx_dpm.c

561

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, &dividers) == 0) {

sys/dev/drm/radeon/rv6xx_dpm.c

599

u32 entry, u32 clock)

sys/dev/drm/radeon/rv6xx_dpm.c

603

if (radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, clock, false, &dividers))

sys/dev/drm/radeon/rv6xx_dpm.c

656

u32 ref_clk = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv6xx_dpm.c

841

u32 ref_clk = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv730_dpm.c

172

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv730_dpm.c

52

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv740_dpm.c

132

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv740_dpm.c

252

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv770.c

789

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/rv770_dpm.c

2256

pl->mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/rv770_dpm.c

2257

pl->sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/rv770_dpm.c

408

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/rv770_dpm.c

505

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/si.c

1331

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/si.c

2302

(u32)mode->clock);

sys/dev/drm/radeon/si.c

2304

(u32)mode->clock);

sys/dev/drm/radeon/si.c

2325

wm_high.disp_clk = mode->clock;

sys/dev/drm/radeon/si.c

2352

wm_low.disp_clk = mode->clock;

sys/dev/drm/radeon/si.c

2393

b.full = dfixed_const(mode->clock);

sys/dev/drm/radeon/si.c

2405

b.full = dfixed_const(mode->clock);

sys/dev/drm/radeon/si.c

6982

uint64_t clock;

sys/dev/drm/radeon/si.c

6986

clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |

sys/dev/drm/radeon/si.c

6989

return clock;

sys/dev/drm/radeon/si_dpm.c

3167

rdev->clock.current_dispclk,

sys/dev/drm/radeon/si_dpm.c

4798

u32 reference_clock = rdev->clock.spll.reference_freq;

sys/dev/drm/radeon/si_dpm.c

4920

u32 reference_clock = rdev->clock.mpll.reference_freq;

sys/dev/drm/radeon/si_dpm.c

5163

if (rdev->clock.current_dispclk <=

sys/dev/drm/radeon/si_dpm.c

6792

pl->mclk = rdev->clock.default_mclk;

sys/dev/drm/radeon/si_dpm.c

6793

pl->sclk = rdev->clock.default_sclk;

sys/dev/drm/radeon/trinity_dpm.c

1643

u64 disp_clk = rdev->clock.default_dispclk / 100;

sys/dev/netif/bwn/siba/siba_core.c

780

siba_cc_clock(struct siba_cc *scc, enum siba_clock clock)

sys/dev/netif/bwn/siba/siba_core.c

797

switch (clock) {

sys/dev/netif/bwn/siba/siba_core.c

822

("%s: unsupported clock %#x", __func__, clock));

sys/dev/video/cxm/cxm.h

661

const struct cxm_saa7115_command *clock;

sys/dev/video/cxm/cxm_saa7115.c

902

nsettings = saa7115_audio_clock[i].clock->nsettings;

sys/dev/video/cxm/cxm_saa7115.c

903

settings = saa7115_audio_clock[i].clock->settings;

sys/kern/kern_cputimer.c

269

sysclock_t clock;

sys/kern/kern_cputimer.c

272

clock = sys_cputimer->count();

sys/kern/kern_cputimer.c

273

error = SYSCTL_OUT(req, &clock, sizeof(clock));

sys/kern/kern_cputimer.c

293

SYSCTL_PROC(_kern_cputimer, OID_AUTO, clock, CTLTYPE_ULONG|CTLFLAG_RD,

sys/netbt/hci.h

1778

uint8_t clock; /* which clock */

sys/netbt/hci.h

1784

uint32_t clock; /* clock value */

usr.sbin/cron/lib/misc.c

599

arpadate(time_t *clock)

usr.sbin/cron/lib/misc.c

601

time_t t = clock ?*clock :time(0L);

usr.sbin/spray/spray.c

167

xmit_time = host_stats.clock.sec +

usr.sbin/spray/spray.c

168

(host_stats.clock.usec / 1000000.0);