__u64
__u64 handle;
__u64 low_gm_sz; /* in MB */
__u64 high_gm_sz; /* in MB */
__u64 fence_sz;
__u64 resolution;
__u64 vgpu_id;
static inline __u64 drm_vma_node_offset_addr(struct drm_vma_offset_node *node)
return ((__u64)node->vm_node.start) << PAGE_SHIFT;
fls64(__u64 x)
__u64 bo_size;
__u64 alignment;
__u64 domains;
__u64 domain_flags;
__u64 bo_info_ptr;
__u64 flags;
__u64 flags;
__u64 addr;
__u64 size;
(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
__u64 flags;
__u64 tiling_info;
__u64 addr_ptr;
__u64 timeout;
__u64 handle;
__u64 timeout;
__u64 status;
__u64 seq_no;
__u64 fences;
__u64 timeout_ns;
__u64 value;
__u64 va_address;
__u64 offset_in_bo;
__u64 map_size;
__u64 chunk_data;
__u64 chunks;
__u64 handle;
__u64 va_start;
__u64 handle;
__u64 return_pointer;
__u64 vram_size;
__u64 vram_cpu_accessible_size;
__u64 gtt_size;
__u64 total_heap_size;
__u64 usable_heap_size;
__u64 heap_usage;
__u64 max_allocation;
__u64 max_engine_clock;
__u64 max_memory_clock;
__u64 ids_flags;
__u64 virtual_address_offset;
__u64 virtual_address_max;
__u64 prim_buf_gpu_addr;
__u64 pos_buf_gpu_addr;
__u64 cntl_sb_buf_gpu_addr;
__u64 param_buf_gpu_addr;
__u64 high_va_offset;
__u64 high_va_max;
__u64 capabilities_flags;
__u64 size;
__u64 capability;
__u64 value;
__u64 capability;
__u64 value;
__u64 handles;
__u64 handles;
__u64 sequence; /* return: most recent vblank sequence */
__u64 sequence; /* on input, target sequence. on output, actual sequence */
__u64 user_data; /* user data passed to event */
__u64 user_data;
__u64 user_data;
__u64 sequence;
((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
__u64 fb_id_ptr;
__u64 crtc_id_ptr;
__u64 connector_id_ptr;
__u64 encoder_id_ptr;
__u64 set_connectors_ptr;
__u64 format_type_ptr;
__u64 plane_id_ptr;
__u64 encoders_ptr;
__u64 modes_ptr;
__u64 props_ptr;
__u64 prop_values_ptr;
__u64 value;
__u64 values_ptr; /* values and blob lengths */
__u64 enum_blob_ptr; /* enum and blob id ptrs */
__u64 value;
__u64 props_ptr;
__u64 prop_values_ptr;
__u64 value;
__u64 data;
__u64 modifier[4]; /* ie, tiling, compress */
__u64 clips_ptr;
__u64 red;
__u64 green;
__u64 blue;
__u64 matrix[9];
__u64 user_data;
__u64 user_data;
__u64 size;
__u64 offset;
__u64 objs_ptr;
__u64 count_props_ptr;
__u64 props_ptr;
__u64 prop_values_ptr;
__u64 reserved;
__u64 user_data;
__u64 formats;
__u64 modifier;
__u64 data;
__u64 object_ids;
__u64 lessees_ptr;
__u64 objects_ptr;
__u64 alignment;
__u64 offset;
__u64 aper_size;
__u64 aper_available_size;
__u64 offset;
__u64 val; /* Return value */
__u64 user_ptr;
__u64 user_size;
__u64 param;
__u64 value;
__u64 properties_ptr;
__u64 mux_regs_ptr;
__u64 boolean_regs_ptr;
__u64 flex_regs_ptr;
__u64 query_id;
__u64 data_ptr;
__u64 items_ptr;
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
__u64 addr;
__u64 gtt_start;
__u64 gtt_end;
__u64 size;
__u64 offset;
__u64 size;
__u64 data_ptr;
__u64 offset;
__u64 size;
__u64 data_ptr;
__u64 offset;
__u64 size;
__u64 addr_ptr;
__u64 flags;
__u64 offset;
__u64 offset;
__u64 presumed_offset;
__u64 relocs_ptr;
__u64 alignment;
__u64 offset;
__u64 buffers_ptr;
__u64 cliprects_ptr;
__u64 relocs_ptr;
__u64 alignment;
__u64 offset;
__u64 flags;
__u64 rsvd1;
__u64 pad_to_size;
__u64 rsvd2;
__u64 buffers_ptr;
__u64 cliprects_ptr;
__u64 flags;
__u64 rsvd1; /* now used for context info */
__u64 rsvd2;
__u64 value;
__u64 gart_size;
__u64 vram_size;
__u64 vram_visible;
__u64 size;
__u64 alignment;
__u64 addr;
__u64 size;
__u64 offset;
__u64 size;
__u64 addr_ptr;
__u64 offset;
__u64 size;
__u64 data_ptr;
__u64 offset;
__u64 size;
__u64 data_ptr;
__u64 value; /* input or return value */
__u64 offset;
__u64 chunk_data;
__u64 chunks;
__u64 gart_limit;
__u64 vram_limit;