__iomem
u32 __iomem *ptr;
void __iomem *rmmio;
void __iomem *rio_mem;
uint8_t __iomem *bios;
uint8_t __iomem *bios;
uint8_t __iomem *bios;
ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
void __iomem *aper_base_kaddr;
void __iomem *ptr = (void *)cpu_pt_addr;
void __iomem *ptr = (void *)cpu_pt_addr;
void __iomem *ptr = (void *)cpu_pt_addr;
void __iomem *regs;
void __iomem *vaddr;
void __iomem *vaddr;
io_mapping_unmap_atomic((void __force __iomem *) unmask_page(cache->vaddr));
io_mapping_unmap_atomic((void __iomem *)vaddr);
ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + ggtt_offset;
static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
gen8_pte_t __iomem *pte =
(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
gen8_pte_t __iomem *gtt_entries;
gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
gen6_pte_t __iomem *pte =
(gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
gen8_pte_t __iomem *gtt_base =
(gen8_pte_t __iomem *)ggtt->gsm + first_entry;
gen6_pte_t scratch_pte, __iomem *gtt_base =
(gen6_pte_t __iomem *)ggtt->gsm + first_entry;
void __iomem *gsm;
gen6_pte_t __iomem *pd_addr;
void __iomem *s;
void __iomem * const regs = i915->regs;
void __iomem * const regs = i915->regs;
void __iomem * const regs = i915->regs;
void __iomem * const regs = i915->regs;
void __iomem * const regs = dev_priv->regs;
void __iomem * const regs = i915->regs;
void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
void __iomem *ptr;
void __iomem *i915_vma_pin_iomap(struct i915_vma *vma);
#define IO_ERR_PTR(x) ((void __iomem *)ERR_PTR(x))
void __iomem *iomap;
static const struct vbt_header *find_vbt(void __iomem *bios, size_t size)
u8 __iomem *bios = NULL;
void __iomem *vaddr;
vaddr = (void __iomem *)engine->buffer->vaddr;
void __iomem *vaddr;
struct overlay_registers __iomem *regs)
struct overlay_registers __iomem *regs;
static void update_polyphase_filter(struct overlay_registers __iomem *regs)
struct overlay_registers __iomem *regs,
struct overlay_registers __iomem *regs)
struct overlay_registers __iomem *regs = overlay->regs;
u32 __iomem *submit_reg;
u32 __iomem *ctrl_reg;
u32 __iomem *csb_read;
void __iomem *
static inline void __iomem *
static inline void __iomem *
static inline void __iomem *
static inline void __iomem *
void iounmap(void __iomem *ptr);
readb(const volatile void __iomem *addr)
readw(const volatile void __iomem *addr)
readl(const volatile void __iomem *addr)
writeb(u8 value, volatile void __iomem *addr)
writew(u16 value, volatile void __iomem *addr)
writel(u32 value, volatile void __iomem *addr)
writeq(u64 value, volatile void __iomem *addr)
#define DRM_READ8(map, offset) readb(((void __iomem *)(map)->handle) + (offset))
#define DRM_READ16(map, offset) readw(((void __iomem *)(map)->handle) + (offset))
#define DRM_READ32(map, offset) readl(((void __iomem *)(map)->handle) + (offset))
#define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset))
#define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset))
#define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset))
#define DRM_READ64(map, offset) readq(((void __iomem *)(map)->handle) + (offset))
#define DRM_WRITE64(map, offset, val) writeq(val, ((void __iomem *)(map)->handle) + (offset))
static inline void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
static inline void __iomem __must_check *
pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
void __iomem *
void iounmap(void __iomem *ptr)
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
void __iomem *ptr = rdev->gart.ptr;
writel(entry, ((uint8_t __iomem *)ptr) + (i * 4));
void __iomem *ptr = (void *)rdev->gart.ptr;
tmp = readl((void __iomem *)ptr);
void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
tmp = readl((void __iomem *)ptr);
void __iomem *rmmio;
return readl(((void __iomem *)rdev->rmmio) + reg);
writel(v, ((void __iomem *)rdev->rmmio) + reg);
u32 __iomem *ptr;
uint8_t __iomem *bios;
uint8_t __iomem *bios, val1, val2;
memcpy_toio((void __iomem *)rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->datasize);
memset_io((void __iomem *)ptr, 0, size);
void __iomem *ptr = (void *)rdev->gart.ptr;
io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar
(u8 __iomem *)((uintptr_t)ena_dev->mem_bar +
io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +
u8 __iomem *pbuf_dev_addr; /* LLQ address */
u32 __iomem *unmask_reg;
u32 __iomem *cq_head_db_reg;
u32 __iomem *numa_node_cfg_reg;
u32 __iomem *db_addr;
u8 __iomem *header_addr;
u32 __iomem *db_addr;
u8 __iomem *reg_bar;
void __iomem *mem_bar;