__BITS
#define PCI_CORE_CAPID0_A_DMFC __BITS(0, 2) /* v1 */
#define PCI_CORE_CAPID0_B_DMFC __BITS(4, 6) /* v2/v3 */
#define MCH_E3_ERRLOG0_ERRSYND __BITS(16, 23)
#define MCH_E3_ERRLOG0_ERRCHUNK __BITS(24, 26)
#define MCH_E3_ERRLOG0_ERRRANK __BITS(27, 28)
#define MCH_E3_ERRLOG0_ERRBANK __BITS(29, 31)
#define MCH_E3_ERRLOG1_ERRROW __BITS(0, 15)
#define MCH_E3_ERRLOG1_ERRCOL __BITS(16, 31)
#define MCH_CORE_DIMM_A_SIZE __BITS(0, 7)
#define MCH_CORE_DIMM_B_SIZE __BITS(8, 15)
#define MCH_E3_DIMM_ECC __BITS(24, 25)
#define MCH_CORE_DIMM_HORIADDR __BITS(27, 29) /* v3 */
#define MCH_CORE_DIMM_TEMP_DIMM0 __BITS(0, 7)
#define MCH_CORE_DIMM_TEMP_DIMM1 __BITS(8, 15)
#define PCI_E5_IMC_ERROR_COR_ERR_CNT_HI __BITS(16, 30)
#define PCI_E5_IMC_ERROR_COR_ERR_CNT_LO __BITS(0, 14)
#define PCI_E5_IMC_ERROR_COR_ERR_TH_HI __BITS(16, 30)
#define PCI_E5_IMC_ERROR_COR_ERR_TH_LO __BITS(0, 14)
#define PCI_E5_IMC_ERROR_COR_ERR_STAT_RANKS __BITS(0, 7)
#define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPHI __BITS(16, 23)
#define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPMID __BITS(8, 15)
#define PCI_E5_IMC_THERMAL_DIMM_TEMP_TH_TEMPLO __BITS(0, 7)
#define PCI_E5_IMC_THERMAL_DIMMTEMPSTAT_TEMP __BITS(0, 7)
#define PCI_E5_UBOX0_CPUNODEID_LCLNODEID __BITS(0, 2) /* local socket */
#define PCI_E5_IMC_CPGC_MCMTR_IMC_MODE __BITS(12, 13)
#define PCI_E5_IMC_CTAD_DIMMMTR_RANK_DISABLE_ALL __BITS(16, 19)
#define PCI_E5_IMC_CTAD_DIMMMTR_RANK_CNT __BITS(12, 13)
#define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_WIDTH __BITS(7, 8)
#define PCI_E5_IMC_CTAD_DIMMMTR_DDR3_DNSTY __BITS(5, 6)
#define PCI_X3400UC_MC_MAX_DOD_DIMMS __BITS(0, 1)
#define PCI_X3400UC_MCT2_COR_DIMM0 __BITS(0, 14)
#define PCI_X3400UC_MCT2_COR_DIMM1 __BITS(16, 30)
#define ET_TXDMA_CTRL_CACHE_THR __BITS(7, 4)
#define ET_TX_READY_POS_INDEX __BITS(9, 0)
#define ET_TX_DONE_POS_INDEX __BITS(9, 0)
#define ET_RXDMA_CTRL_RING0_SIZE __BITS(9, 8)
#define ET_RXDMA_CTRL_RING1_SIZE __BITS(12, 11)
#define ET_RXSTAT_POS_INDEX __BITS(11, 0)
#define ET_RX_RING0_POS_INDEX __BITS(9, 0)
#define ET_RX_RING1_POS_INDEX __BITS(9, 0)
#define ET_PKTFILT_MINLEN __BITS(22, 16)
#define ET_RXMAC_MC_SEGSZ_MAX __BITS(9, 2)
#define ET_MAC_CFG2_PREAMBLE_LEN __BITS(15, 12)
#define ET_IPG_B2B __BITS(6, 0)
#define ET_IPG_MINIFG __BITS(15, 8)
#define ET_IPG_NONB2B_2 __BITS(22, 16)
#define ET_IPG_NONB2B_1 __BITS(30, 24)
#define ET_MAC_HDX_COLLWIN __BITS(9, 0)
#define ET_MAC_HDX_REXMIT_MAX __BITS(15, 12)
#define ET_MAC_HDX_ALT_BEB_TRUNC __BITS(23, 20)
#define ET_MII_CFG_CLKRST __BITS(2, 0)
#define ET_MII_ADDR_REG __BITS(4, 0)
#define ET_MII_ADDR_PHY __BITS(12, 8)
#define ET_MII_CTRL_VALUE __BITS(15, 0)
#define ET_MII_STAT_VALUE __BITS(15, 0)
#define ET_RX_RING_POS_INDEX __BITS(9, 0)
#define ET_PCIM_L0S_LATENCY __BITS(2, 0)
#define ET_PCIM_L1_LATENCY __BITS(5, 3)
#define ET_RXST_INFO2_RINGIDX __BITS(27, 26)
#define ET_RXS_STATRING_INDEX __BITS(27, 16)
#define ET_TDCTRL1_LEN __BITS(15, 0)
#define ET_RDCTRL_BUFIDX __BITS(9, 0)
#define ET_RXST_INFO2_LEN __BITS(15, 0)
#define ET_RXST_INFO2_BUFIDX __BITS(25, 16)
if (__predict_false(pat[i] & ~__BITS(2,0)))
#define CPUID_0_01_EBX_BRAND_INDEX __BITS(7,0)
#define CPUID_0_01_EBX_CLFLUSH_SIZE __BITS(15,8)
#define CPUID_0_01_EBX_HTT_CORES __BITS(23,16)
#define CPUID_0_01_EBX_LOCAL_APIC_ID __BITS(31,24)
#define CPUID_0_04_EAX_CACHETYPE __BITS(4, 0)
#define CPUID_0_04_EAX_CACHELEVEL __BITS(7, 5)
#define CPUID_0_04_EAX_SHARING __BITS(25, 14)
#define CPUID_0_04_EAX_CORE_P_PKG __BITS(31, 26)
#define CPUID_0_07_ECX_MAWAU __BITS(21, 17)
#define CPUID_0_0B_EAX_SHIFTNUM __BITS(4, 0)
#define CPUID_0_0B_ECX_LVLNUM __BITS(7, 0)
#define CPUID_0_0B_ECX_LVLTYPE __BITS(15, 8)
#define CPUID_8_08_ECX_NC __BITS(7,0)
#define CPUID_8_08_ECX_ApicIdSize __BITS(15,12)
#define CPUID_8_08_ECX_PerfTscSize __BITS(17,16)
#define CPUID_8_0A_EAX_SvmRev __BITS(7,0)
#define SVM_EXIT_CR_GPR __BITS(3,0) /* GPR number */
#define SVM_EXIT_IO_PORT __BITS(31,16)
#define SVM_EXIT_IO_SEG __BITS(12,10)
#define SVM_SEG_ATTRIB_TYPE __BITS(3,0)
#define SVM_SEG_ATTRIB_DPL __BITS(6,5)
#define VMCB_CTRL_V_TPR __BITS(3,0)
#define VMCB_CTRL_V_INTR_PRIO __BITS(19,16)
#define VMCB_CTRL_V_INTR_VECTOR __BITS(39,32)
#define VMCB_CTRL_EXITINTINFO_VECTOR __BITS(7,0)
#define VMCB_CTRL_EXITINTINFO_TYPE __BITS(10,8)
#define VMCB_CTRL_EXITINTINFO_ERRORCODE __BITS(63,32)
#define VMCB_CTRL_AVIC_APIC_BAR __BITS(51,0)
#define VMCB_CTRL_EVENTINJ_VECTOR __BITS(7,0)
#define VMCB_CTRL_EVENTINJ_TYPE __BITS(10,8)
#define VMCB_CTRL_EVENTINJ_ERRORCODE __BITS(63,32)
#define VMCB_CTRL_AVIC_PHYS_TABLE_PTR __BITS(51,12)
#define VMCB_CTRL_AVIC_PHYS_MAX_INDEX __BITS(7,0)
#define VMX_QUAL_CR_NUM __BITS(3,0)
#define VMX_QUAL_CR_TYPE __BITS(5,4)
#define VMX_QUAL_CR_GPR __BITS(11,8)
#define VMX_QUAL_IO_SIZE __BITS(2,0)
#define VMX_QUAL_IO_PORT __BITS(31,16)
#define VMX_INFO_IO_ADRSIZE __BITS(9,7)
#define VMX_INFO_IO_SEG __BITS(17,15)
#define IA32_VMX_BASIC_IDENT __BITS(30,0)
#define IA32_VMX_BASIC_DATA_SIZE __BITS(44,32)
#define IA32_VMX_BASIC_MEM_TYPE __BITS(53,50)
exitcode &= __BITS(15,0);
#define VMX_SEG_ATTRIB_TYPE __BITS(3,0)
#define VMX_SEG_ATTRIB_DPL __BITS(6,5)
#define EPTP_TYPE __BITS(2,0)
#define EPTP_WALKLEN __BITS(5,3)
#define EPTP_PHYSADDR __BITS(63,12)
#define INTR_INFO_VECTOR __BITS(7,0)
#define INTR_INFO_TYPE __BITS(10,8)
#define VMXON_IDENT_REVISION __BITS(30,0)
#define VMCS_IDENT_REVISION __BITS(30,0)