sys/dev/drm/amd/amdgpu/amdgpu.h

1127

WREG32(reg, tmp_); \

sys/dev/drm/amd/amdgpu/amdgpu.h

1158

WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu.h

1161

WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

200

WREG32(mmSRBM_GFX_CNTL, value);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

207

WREG32(mmSRBM_GFX_CNTL, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

237

WREG32(mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

238

WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

239

WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

240

WREG32(mmSH_MEM_BASES, sh_mem_bases);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

260

WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

264

WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

267

WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

283

WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

339

WREG32(mmRLC_CP_SCHEDULERS, value);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

346

WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

354

WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

355

WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

356

WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

360

WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

367

WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

377

WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

380

WREG32(mmCP_HQD_ACTIVE, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

434

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

450

WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

455

WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

460

WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

461

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

464

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

466

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

469

WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

471

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

472

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

474

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

476

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

481

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

648

WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

681

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

692

WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

693

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

745

WREG32(mmGRBM_GFX_INDEX, gfx_index_val);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

746

WREG32(mmSQ_CMD, sq_cmd);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

755

WREG32(mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

774

WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

844

WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

864

WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

882

WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1031

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1032

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1034

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1036

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1039

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1040

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1042

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1043

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1045

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1047

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1050

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

1051

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base));

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

284

WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

285

WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

312

WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

321

WREG32(SOC15_REG_OFFSET(ATHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

326

WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

329

WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

338

WREG32(SOC15_REG_OFFSET(ATHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

343

WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

363

WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

428

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

437

WREG32(reg, mqd_hqd[reg - hqd_base]);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

443

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

472

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

474

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

476

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

478

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

480

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

485

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

490

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

547

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

562

WREG32(sdmax_gfx_context_cntl, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

564

WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

569

WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

570

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

571

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

574

WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

576

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

578

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

581

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

583

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

586

WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

588

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

589

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

591

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

593

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

598

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

706

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

740

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

751

WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

752

WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

813

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

815

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

818

WREG32(SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

821

WREG32(SOC15_REG_OFFSET(MMHUB, 0,

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

825

WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_REQ), req);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

827

WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_INVALIDATE_ENG16_REQ),

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

933

WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

934

WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);

sys/dev/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

943

WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1701

WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1722

WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1723

WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1736

WREG32(adev->bios_scratch_reg_offset + 3, tmp);

sys/dev/drm/amd/amdgpu/amdgpu_atombios.c

1903

WREG32(reg, val);

sys/dev/drm/amd/amdgpu/amdgpu_cgs.c

53

WREG32(offset, value);

sys/dev/drm/amd/amdgpu/amdgpu_debugfs.c

170

WREG32(*pos >> 2, value);

sys/dev/drm/amd/amdgpu/amdgpu_device.c

485

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

139

WREG32(rec->en_clk_reg, val);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

152

WREG32(rec->en_data_reg, val);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

52

WREG32(rec->mask_clk_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

57

WREG32(rec->a_clk_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

60

WREG32(rec->a_data_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

64

WREG32(rec->en_clk_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

67

WREG32(rec->en_data_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

71

WREG32(rec->mask_clk_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

75

WREG32(rec->mask_data_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

90

WREG32(rec->mask_clk_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_i2c.c

94

WREG32(rec->mask_data_reg, temp);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

436

WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/amdgpu_vcn.c

790

WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9), 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2058

WREG32(mmBIOS_SCRATCH_0, bios_0_scratch);

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2059

WREG32(mmBIOS_SCRATCH_3, bios_3_scratch);

sys/dev/drm/amd/amdgpu/atombios_encoders.c

2060

WREG32(mmBIOS_SCRATCH_6, bios_6_scratch);

sys/dev/drm/amd/amdgpu/atombios_encoders.c

64

WREG32(mmBIOS_SCRATCH_2, bios_2_scratch);

sys/dev/drm/amd/amdgpu/ci_dpm.c

1813

WREG32(mmSMC_MSG_ARG_0, parameter);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2061

WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);

sys/dev/drm/amd/amdgpu/ci_dpm.c

2072

WREG32(mmSMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);

sys/dev/drm/amd/amdgpu/ci_dpm.c

230

WREG32(mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);

sys/dev/drm/amd/amdgpu/ci_dpm.c

231

WREG32(mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

236

WREG32(mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);

sys/dev/drm/amd/amdgpu/ci_dpm.c

237

WREG32(mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);

sys/dev/drm/amd/amdgpu/ci_dpm.c

246

WREG32(mmMC_CG_CONFIG, mc_cg_config);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4763

WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4766

WREG32(mmMC_SEQ_IO_DEBUG_INDEX, 3);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4767

WREG32(mmMC_SEQ_IO_DEBUG_DATA, tmp);

sys/dev/drm/amd/amdgpu/ci_dpm.c

4785

WREG32(mmMC_SEQ_RAS_TIMING_LP, RREG32(mmMC_SEQ_RAS_TIMING));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4786

WREG32(mmMC_SEQ_CAS_TIMING_LP, RREG32(mmMC_SEQ_CAS_TIMING));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4787

WREG32(mmMC_SEQ_DLL_STBY_LP, RREG32(mmMC_SEQ_DLL_STBY));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4788

WREG32(mmMC_SEQ_G5PDX_CMD0_LP, RREG32(mmMC_SEQ_G5PDX_CMD0));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4789

WREG32(mmMC_SEQ_G5PDX_CMD1_LP, RREG32(mmMC_SEQ_G5PDX_CMD1));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4790

WREG32(mmMC_SEQ_G5PDX_CTRL_LP, RREG32(mmMC_SEQ_G5PDX_CTRL));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4791

WREG32(mmMC_SEQ_PMG_DVS_CMD_LP, RREG32(mmMC_SEQ_PMG_DVS_CMD));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4792

WREG32(mmMC_SEQ_PMG_DVS_CTL_LP, RREG32(mmMC_SEQ_PMG_DVS_CTL));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4793

WREG32(mmMC_SEQ_MISC_TIMING_LP, RREG32(mmMC_SEQ_MISC_TIMING));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4794

WREG32(mmMC_SEQ_MISC_TIMING2_LP, RREG32(mmMC_SEQ_MISC_TIMING2));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4795

WREG32(mmMC_SEQ_PMG_CMD_EMRS_LP, RREG32(mmMC_PMG_CMD_EMRS));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4796

WREG32(mmMC_SEQ_PMG_CMD_MRS_LP, RREG32(mmMC_PMG_CMD_MRS));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4797

WREG32(mmMC_SEQ_PMG_CMD_MRS1_LP, RREG32(mmMC_PMG_CMD_MRS1));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4798

WREG32(mmMC_SEQ_WR_CTL_D0_LP, RREG32(mmMC_SEQ_WR_CTL_D0));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4799

WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4800

WREG32(mmMC_SEQ_RD_CTL_D0_LP, RREG32(mmMC_SEQ_RD_CTL_D0));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4801

WREG32(mmMC_SEQ_RD_CTL_D1_LP, RREG32(mmMC_SEQ_RD_CTL_D1));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4802

WREG32(mmMC_SEQ_PMG_TIMING_LP, RREG32(mmMC_SEQ_PMG_TIMING));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4803

WREG32(mmMC_SEQ_PMG_CMD_MRS2_LP, RREG32(mmMC_PMG_CMD_MRS2));

sys/dev/drm/amd/amdgpu/ci_dpm.c

4804

WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2));

sys/dev/drm/amd/amdgpu/ci_dpm.c

729

WREG32(config_regs->offset, data);

sys/dev/drm/amd/amdgpu/ci_smc.c

108

WREG32(mmSMC_IND_DATA_0, data);

sys/dev/drm/amd/amdgpu/ci_smc.c

177

WREG32(mmSMC_MESSAGE_0, msg);

sys/dev/drm/amd/amdgpu/ci_smc.c

233

WREG32(mmSMC_IND_INDEX_0, ucode_start_address);

sys/dev/drm/amd/amdgpu/ci_smc.c

240

WREG32(mmSMC_IND_DATA_0, data);

sys/dev/drm/amd/amdgpu/ci_smc.c

275

WREG32(mmSMC_IND_DATA_0, value);

sys/dev/drm/amd/amdgpu/ci_smc.c

44

WREG32(mmSMC_IND_INDEX_0, smc_address);

sys/dev/drm/amd/amdgpu/ci_smc.c

76

WREG32(mmSMC_IND_DATA_0, data);

sys/dev/drm/amd/amdgpu/cik.c

106

WREG32(mmSMC_IND_INDEX_0, (reg));

sys/dev/drm/amd/amdgpu/cik.c

1154

WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &

sys/dev/drm/amd/amdgpu/cik.c

1156

WREG32(mmGMCON_MISC, save->gmcon_misc &

sys/dev/drm/amd/amdgpu/cik.c

1166

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1167

WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);

sys/dev/drm/amd/amdgpu/cik.c

117

WREG32(mmSMC_IND_INDEX_0, (reg));

sys/dev/drm/amd/amdgpu/cik.c

1170

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1172

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1173

WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);

sys/dev/drm/amd/amdgpu/cik.c

1176

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1178

WREG32(mmGMCON_PGFSM_WRITE, 0x210000);

sys/dev/drm/amd/amdgpu/cik.c

1179

WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);

sys/dev/drm/amd/amdgpu/cik.c

118

WREG32(mmSMC_IND_DATA_0, (v));

sys/dev/drm/amd/amdgpu/cik.c

1182

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1184

WREG32(mmGMCON_PGFSM_WRITE, 0x21003);

sys/dev/drm/amd/amdgpu/cik.c

1185

WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);

sys/dev/drm/amd/amdgpu/cik.c

1188

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1190

WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);

sys/dev/drm/amd/amdgpu/cik.c

1191

WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);

sys/dev/drm/amd/amdgpu/cik.c

1194

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1196

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1197

WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);

sys/dev/drm/amd/amdgpu/cik.c

1200

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1202

WREG32(mmGMCON_PGFSM_WRITE, 0x420000);

sys/dev/drm/amd/amdgpu/cik.c

1203

WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);

sys/dev/drm/amd/amdgpu/cik.c

1206

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1208

WREG32(mmGMCON_PGFSM_WRITE, 0x120202);

sys/dev/drm/amd/amdgpu/cik.c

1209

WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);

sys/dev/drm/amd/amdgpu/cik.c

1212

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1214

WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);

sys/dev/drm/amd/amdgpu/cik.c

1215

WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);

sys/dev/drm/amd/amdgpu/cik.c

1218

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1220

WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);

sys/dev/drm/amd/amdgpu/cik.c

1221

WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);

sys/dev/drm/amd/amdgpu/cik.c

1224

WREG32(mmGMCON_PGFSM_WRITE, 0);

sys/dev/drm/amd/amdgpu/cik.c

1226

WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);

sys/dev/drm/amd/amdgpu/cik.c

1227

WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);

sys/dev/drm/amd/amdgpu/cik.c

1229

WREG32(mmGMCON_MISC3, save->gmcon_misc3);

sys/dev/drm/amd/amdgpu/cik.c

1230

WREG32(mmGMCON_MISC, save->gmcon_misc);

sys/dev/drm/amd/amdgpu/cik.c

1231

WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);

sys/dev/drm/amd/amdgpu/cik.c

128

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/cik.c

139

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/cik.c

140

WREG32(mmUVD_CTX_DATA, (v));

sys/dev/drm/amd/amdgpu/cik.c

150

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/cik.c

161

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/cik.c

162

WREG32(mmDIDT_IND_DATA, (v));

sys/dev/drm/amd/amdgpu/cik.c

1724

WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);

sys/dev/drm/amd/amdgpu/cik.c

1735

WREG32(mmHDP_DEBUG0, 1);

sys/dev/drm/amd/amdgpu/cik.c

81

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/cik.c

875

WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);

sys/dev/drm/amd/amdgpu/cik.c

887

WREG32(mmCONFIG_CNTL, tmp);

sys/dev/drm/amd/amdgpu/cik.c

908

WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));

sys/dev/drm/amd/amdgpu/cik.c

911

WREG32(mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/cik.c

914

WREG32(mmD2VGA_CONTROL,

sys/dev/drm/amd/amdgpu/cik.c

917

WREG32(mmVGA_RENDER_CONTROL,

sys/dev/drm/amd/amdgpu/cik.c

925

WREG32(mmBUS_CNTL, bus_cntl);

sys/dev/drm/amd/amdgpu/cik.c

927

WREG32(mmD1VGA_CONTROL, d1vga_control);

sys/dev/drm/amd/amdgpu/cik.c

928

WREG32(mmD2VGA_CONTROL, d2vga_control);

sys/dev/drm/amd/amdgpu/cik.c

929

WREG32(mmVGA_RENDER_CONTROL, vga_render_control);

sys/dev/drm/amd/amdgpu/cik.c

93

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/cik.c

95

WREG32(mmPCIE_DATA, v);

sys/dev/drm/amd/amdgpu/cik.c

955

WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);

sys/dev/drm/amd/amdgpu/cik.c

956

WREG32(mmSMC_IND_DATA_0, 0);

sys/dev/drm/amd/amdgpu/cik.c

958

WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);

sys/dev/drm/amd/amdgpu/cik_ih.c

114

WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/cik_ih.c

122

WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

124

WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/cik_ih.c

135

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/cik_ih.c

136

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/cik_ih.c

138

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

141

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/cik_ih.c

142

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/cik_ih.c

151

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

203

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/cik_ih.c

299

WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);

sys/dev/drm/amd/amdgpu/cik_ih.c

417

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/cik_ih.c

423

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/cik_ih.c

65

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

66

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

84

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

85

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/cik_ih.c

87

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/cik_ih.c

88

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1095

WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1102

WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1110

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1116

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1139

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1144

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1155

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

1160

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

195

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],

sys/dev/drm/amd/amdgpu/cik_sdma.c

316

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

317

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

378

WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/cik_sdma.c

380

WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/cik_sdma.c

388

WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

416

WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

444

WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

445

WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

451

WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/cik_sdma.c

454

WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

455

WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

464

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

467

WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

468

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

469

WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

470

WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

473

WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/cik_sdma.c

475

WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/cik_sdma.c

480

WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/cik_sdma.c

481

WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);

sys/dev/drm/amd/amdgpu/cik_sdma.c

484

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/cik_sdma.c

487

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/cik_sdma.c

495

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/cik_sdma.c

561

WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/cik_sdma.c

563

WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/cik_sdma.c

564

WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);

sys/dev/drm/amd/amdgpu/cik_sdma.c

903

WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/amd/amdgpu/cik_sdma.c

904

WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/amd/amdgpu/cik_sdma.c

909

WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

914

WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

927

WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

932

WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

937

WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cik_sdma.c

942

WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/amd/amdgpu/cz_ih.c

114

WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/cz_ih.c

122

WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

125

WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/cz_ih.c

137

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/cz_ih.c

138

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/cz_ih.c

140

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

143

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/cz_ih.c

144

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/cz_ih.c

152

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

205

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/cz_ih.c

278

WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);

sys/dev/drm/amd/amdgpu/cz_ih.c

396

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/cz_ih.c

402

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/cz_ih.c

65

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

66

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

84

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

85

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/cz_ih.c

87

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/cz_ih.c

88

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1114

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1118

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1121

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1125

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1127

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1209

WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1469

WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1472

WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1476

WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1479

WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1483

WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1486

WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1503

WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1505

WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1507

WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1509

WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1535

WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1536

WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1537

WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1578

WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1580

WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1607

WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1613

WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1620

WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1625

WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1630

WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1632

WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1639

WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1644

WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1655

WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1661

WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1665

WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1674

WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1678

WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1704

WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1708

WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1713

WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1715

WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1716

WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1717

WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1718

WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

178

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1805

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1807

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1817

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1819

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

191

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

192

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

1999

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2001

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2003

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2005

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2007

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2009

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2010

WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2022

WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2027

WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2028

WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2029

WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2030

WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2031

WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2032

WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2035

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2039

WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2044

WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2048

WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2052

WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2082

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2099

WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2103

WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2107

WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2112

WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2114

WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2116

WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2117

WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2118

WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2120

WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2121

WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2122

WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2124

WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2125

WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2127

WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2132

WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2142

WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2147

WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2152

WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2157

WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2160

WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2166

WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2272

WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2292

WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2294

WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2327

WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2328

WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2329

WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

242

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

244

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

247

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2930

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2936

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2961

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2967

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2990

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

2996

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3019

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3024

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3095

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3098

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/drm/amd/amdgpu/dce_v10_0.c

311

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3123

WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3169

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3184

WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

3199

WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

343

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

349

WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

358

WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

388

WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

441

WREG32(mmVGA_HDP_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

449

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

481

WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

484

WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

485

WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

564

WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

617

WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v10_0.c

621

WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1140

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1144

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1147

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1151

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1153

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1235

WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1511

WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1514

WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1518

WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1521

WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1525

WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1528

WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1545

WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1547

WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1549

WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1551

WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1577

WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1578

WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1579

WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1620

WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1622

WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1649

WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1655

WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1662

WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1667

WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1672

WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1674

WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1681

WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1686

WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1697

WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1703

WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1707

WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1716

WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1720

WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1746

WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1750

WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1755

WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1757

WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1758

WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1759

WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1760

WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1847

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1849

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1859

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

1861

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

196

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2041

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2043

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2045

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2047

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2049

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2051

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2052

WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2064

WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2069

WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2070

WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2071

WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2072

WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2073

WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2074

WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2077

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2081

WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2086

WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

209

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2090

WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2094

WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

210

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2124

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2140

WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2144

WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2148

WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2150

WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2152

WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2153

WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2154

WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2156

WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2157

WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2158

WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2160

WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2161

WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2163

WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2168

WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2178

WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2182

WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2186

WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2190

WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2193

WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2199

WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2351

WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2371

WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2373

WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2406

WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2407

WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

2408

WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

260

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

262

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

265

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3056

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3062

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3087

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3093

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3116

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3122

WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3145

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3150

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3221

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3224

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3249

WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],

sys/dev/drm/amd/amdgpu/dce_v11_0.c

329

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3295

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3310

WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

3325

WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

361

WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

367

WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

376

WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

405

WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

457

WREG32(mmVGA_HDP_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

465

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

507

WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

510

WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

511

WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

590

WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

643

WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v11_0.c

647

WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1051

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1052

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1059

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1060

WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1064

WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1146

WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

126

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

139

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

140

WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1430

WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1431

WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1433

WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1434

WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1436

WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1437

WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1454

WREG32(mmAFMT_AVI_INFO0 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1456

WREG32(mmAFMT_AVI_INFO1 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1458

WREG32(mmAFMT_AVI_INFO2 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1460

WREG32(mmAFMT_AVI_INFO3 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1482

WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT));

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1483

WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1484

WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1525

WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1528

WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1557

WREG32(mmHDMI_CONTROL + offset, val);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1559

WREG32(mmHDMI_VBI_PACKET_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1564

WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1568

WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1571

WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1574

WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1576

WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1580

WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1586

WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1589

WREG32(mmHDMI_ACR_PACKET_CONTROL + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1595

WREG32(mmAFMT_60958_0 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1598

WREG32(mmAFMT_60958_1 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1601

WREG32(mmAFMT_60958_2 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1612

WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1644

WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1645

WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1646

WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1647

WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1734

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1736

WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1746

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1748

WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

186

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?

sys/dev/drm/amd/amdgpu/dce_v8_0.c

189

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1911

WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1913

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1915

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1917

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1919

WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

192

WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1921

WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1922

WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1936

WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1937

WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1938

WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1939

WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1940

WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1941

WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1944

WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1948

WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1953

WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1957

WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1961

WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1986

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

1989

WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2002

WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2005

WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2007

WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2009

WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2013

WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2015

WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2016

WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2017

WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2019

WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2020

WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2021

WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2023

WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2024

WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2026

WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2031

WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2037

WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2041

WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2044

WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2047

WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2051

WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2055

WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2175

WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2193

WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2195

WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2228

WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2229

WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2230

WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

256

WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

281

WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2818

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2824

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2872

WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2877

WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

292

WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2923

WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2928

WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2951

WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

2956

WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3025

WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3036

WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3064

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3067

WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3092

WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],

sys/dev/drm/amd/amdgpu/dce_v8_0.c

3145

WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

323

WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

374

WREG32(mmVGA_HDP_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

382

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

421

WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

424

WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

425

WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

501

WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);

sys/dev/drm/amd/amdgpu/dce_v8_0.c

552

WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset,

sys/dev/drm/amd/amdgpu/dce_v8_0.c

556

WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1215

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1218

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1398

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1401

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1568

WREG32(mmGB_TILE_MODE0 + reg_offset, tile[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1571

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, macrotile[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1609

WREG32(mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1769

WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1770

WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1817

WREG32(mmPA_SC_RASTER_CONFIG, raster_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1818

WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1874

WREG32(mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1875

WREG32(mmSH_MEM_APE1_BASE, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1876

WREG32(mmSH_MEM_APE1_LIMIT, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1877

WREG32(mmSH_MEM_BASES, sh_mem_bases);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1902

WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1904

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1905

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1906

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1915

WREG32(mmCP_MEQ_THRESHOLDS,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1942

WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1952

WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1953

WREG32(mmSH_MEM_APE1_BASE, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1954

WREG32(mmSH_MEM_APE1_LIMIT, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1955

WREG32(mmSH_MEM_BASES, sh_mem_base);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1962

WREG32(mmSX_DEBUG_1, 0x20);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1964

WREG32(mmTA_CNTL_AUX, 0x00010000);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1968

WREG32(mmSPI_CONFIG_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1970

WREG32(mmSQ_CONFIG, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1972

WREG32(mmDB_DEBUG, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1976

WREG32(mmDB_DEBUG2, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1980

WREG32(mmDB_DEBUG3, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1984

WREG32(mmCB_HW_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1986

WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1988

WREG32(mmPA_SC_FIFO_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1994

WREG32(mmVGT_NUM_INSTANCES, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1996

WREG32(mmCP_PERFMON_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

1998

WREG32(mmSQ_CONFIG, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2000

WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2004

WREG32(mmVGT_CACHE_INVALIDATION,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2008

WREG32(mmVGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2009

WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2011

WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2013

WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2020

WREG32(mmSPI_ARB_PRIORITY, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2071

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2323

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2402

WREG32(mmCP_ME_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2404

WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2451

WREG32(mmCP_PFP_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2453

WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2454

WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2461

WREG32(mmCP_CE_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2463

WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2464

WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2471

WREG32(mmCP_ME_RAM_WADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2473

WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2474

WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2496

WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2497

WREG32(mmCP_ENDIAN_SWAP, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2498

WREG32(mmCP_DEVICE_ID, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2572

WREG32(mmCP_SEM_WAIT_TIMER, 0x0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2574

WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2577

WREG32(mmCP_RB_WPTR_DELAY, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2580

WREG32(mmCP_RB_VMID, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2582

WREG32(mmSCRATCH_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2592

WREG32(mmCP_RB0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2595

WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2597

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2601

WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2602

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2605

WREG32(mmSCRATCH_UMSK, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2608

WREG32(mmCP_RB0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2611

WREG32(mmCP_RB0_BASE, rb_addr);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2612

WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2642

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2674

WREG32(mmCP_MEC_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2676

WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2713

WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2715

WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2716

WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2735

WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2737

WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2738

WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2856

WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2857

WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2860

WREG32(mmCP_HPD_EOP_VMID, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2866

WREG32(mmCP_HPD_EOP_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2878

WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2888

WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2889

WREG32(mmCP_HQD_PQ_RPTR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

2890

WREG32(mmCP_HQD_PQ_WPTR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3029

WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3033

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3037

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3090

WREG32(mmCP_CPF_DEBUG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3150

WREG32(mmCP_INT_CNTL_RING0, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3384

WREG32(mmRLC_LB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3423

WREG32(mmRLC_CNTL, rlc);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3436

WREG32(mmRLC_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3455

WREG32(mmRLC_GPR_REG2, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3477

WREG32(mmRLC_GPR_REG2, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3489

WREG32(mmRLC_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3505

WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3517

WREG32(mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3520

WREG32(mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3553

WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3559

WREG32(mmRLC_LB_CNTR_INIT, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3560

WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3564

WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3565

WREG32(mmRLC_LB_PARAMS, 0x00600408);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3566

WREG32(mmRLC_LB_CNTL, 0x80000004);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3569

WREG32(mmRLC_MC_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3570

WREG32(mmRLC_UCODE_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3575

WREG32(mmRLC_GPM_UCODE_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3577

WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3578

WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3584

WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3604

WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3605

WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3609

WREG32(mmRLC_SERDES_WR_CTRL, tmp2);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3616

WREG32(mmRLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3628

WREG32(mmRLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3644

WREG32(mmCP_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3652

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3658

WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3659

WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3662

WREG32(mmRLC_SERDES_WR_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3680

WREG32(mmCGTS_SM_CTRL_REG, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3686

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3691

WREG32(mmRLC_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3697

WREG32(mmCP_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3703

WREG32(mmCGTS_SM_CTRL_REG, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3709

WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3710

WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3712

WREG32(mmRLC_SERDES_WR_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3745

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3759

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3772

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3785

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3865

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3870

WREG32(mmRLC_AUTO_PG_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3875

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3880

WREG32(mmRLC_AUTO_PG_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3897

WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3919

WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3924

WREG32(mmRLC_MAX_PG_CU, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3938

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3952

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3964

WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3965

WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3966

WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3967

WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3969

WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3971

WREG32(mmRLC_GPM_SCRATCH_DATA, 0);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3974

WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3976

WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3982

WREG32(mmRLC_PG_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3984

WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3985

WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3990

WREG32(mmCP_RB_WPTR_POLL_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3993

WREG32(mmRLC_PG_DELAY, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

3998

WREG32(mmRLC_PG_DELAY_2, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4003

WREG32(mmRLC_AUTO_PG_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4161

WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4216

WREG32(mmSQ_CMD, value);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4221

WREG32(mmSQ_IND_INDEX,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4233

WREG32(mmSQ_IND_INDEX,

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4737

WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4740

WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4746

WREG32(mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4752

WREG32(mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4760

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4766

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4784

WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4789

WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4835

WREG32(mec_int_cntl_reg, mec_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4840

WREG32(mec_int_cntl_reg, mec_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4858

WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4863

WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4883

WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v7_0.c

4888

WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1636

WREG32(mmGB_EDC_MODE, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1762

WREG32(mmGB_EDC_MODE, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

1766

WREG32(mmCC_GC_EDC_CONFIG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2380

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2384

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2570

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2574

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2759

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2763

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2962

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

2966

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3164

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3168

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3335

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3339

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3511

WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3515

WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3541

WREG32(mmGRBM_GFX_INDEX, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3707

WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3708

WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3746

WREG32(mmPA_SC_RASTER_CONFIG, raster_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3747

WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3808

WREG32(mmSH_MEM_CONFIG, sh_mem_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3809

WREG32(mmSH_MEM_APE1_BASE, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3810

WREG32(mmSH_MEM_APE1_LIMIT, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3811

WREG32(mmSH_MEM_BASES, sh_mem_bases);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3836

WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3837

WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3838

WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3853

WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3864

WREG32(mmSH_MEM_CONFIG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3865

WREG32(mmSH_MEM_BASES, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3871

WREG32(mmSH_MEM_CONFIG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3873

WREG32(mmSH_MEM_BASES, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3876

WREG32(mmSH_MEM_APE1_BASE, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3877

WREG32(mmSH_MEM_APE1_LIMIT, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3891

WREG32(mmPA_SC_FIFO_SIZE,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3906

WREG32(mmSPI_ARB_PRIORITY, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3960

WREG32(mmCP_INT_CNTL_RING0, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3966

WREG32(mmRLC_CSIB_ADDR_HI,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3968

WREG32(mmRLC_CSIB_ADDR_LO,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

3970

WREG32(mmRLC_CSIB_LENGTH,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4053

WREG32(mmRLC_SRM_ARAM_ADDR, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4055

WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4058

WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4060

WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4064

WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4065

WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4068

WREG32(mmRLC_GPM_SCRATCH_ADDR,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4071

WREG32(mmRLC_GPM_SCRATCH_DATA,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4079

WREG32(temp + i, unique_indices[i] & 0x3FFFF);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4080

WREG32(data + i, unique_indices[i] >> 20);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4103

WREG32(mmRLC_PG_DELAY, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4134

WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4136

WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4202

WREG32(mmCP_ME_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4243

WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4244

WREG32(mmCP_ENDIAN_SWAP, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4245

WREG32(mmCP_DEVICE_ID, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4318

WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4326

WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4328

WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4341

WREG32(mmCP_RB_WPTR_DELAY, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4344

WREG32(mmCP_RB_VMID, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4356

WREG32(mmCP_RB0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4359

WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4361

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4365

WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4366

WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4369

WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4370

WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4372

WREG32(mmCP_RB0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4375

WREG32(mmCP_RB0_BASE, rb_addr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4376

WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4395

WREG32(mmCP_MEC_CNTL, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4397

WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4415

WREG32(mmRLC_CP_SCHEDULERS, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4417

WREG32(mmRLC_CP_SCHEDULERS, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4498

WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4499

WREG32(mmCP_HQD_PQ_RPTR, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4500

WREG32(mmCP_HQD_PQ_WPTR, 0);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4664

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4672

WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4673

WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4674

WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4678

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4682

WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR]);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4760

WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

4761

WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, AMDGPU_DOORBELL_MEC_RING7 << 2);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5122

WREG32(mmGMCON_DEBUG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5130

WREG32(mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5136

WREG32(mmGRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5144

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5150

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5158

WREG32(mmGMCON_DEBUG, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5220

WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5268

WREG32(mmSQ_IND_INDEX,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5280

WREG32(mmSQ_IND_INDEX,

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5557

WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5558

WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5588

WREG32(mmRLC_SERDES_WR_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5611

WREG32(mmRLC_SAFE_MODE, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5645

WREG32(mmRLC_SAFE_MODE, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5693

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5714

WREG32(mmCGTS_SM_CTRL_REG, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5728

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5734

WREG32(mmRLC_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5741

WREG32(mmCP_MEM_SLP_CNTL, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5749

WREG32(mmCGTS_SM_CTRL_REG, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5779

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5804

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5810

WREG32(mmRLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5825

WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

5849

WREG32(mmRLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6086

WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6275

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6338

WREG32(mmCP_HQD_PIPE_PRIORITY, pipe_priority);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6339

WREG32(mmCP_HQD_QUEUE_PRIORITY, queue_priority);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6518

WREG32(mmSQ_CMD, value);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6567

WREG32(mec_int_cntl_reg, mec_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

6572

WREG32(mec_int_cntl_reg, mec_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

7091

WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);

sys/dev/drm/amd/amdgpu/gfx_v8_0.c

846

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2076

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2078

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2080

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2154

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2157

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2160

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2164

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2169

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2197

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2199

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2202

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2205

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2211

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2215

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2241

WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2247

WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2252

WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2267

WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2275

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2280

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2285

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2292

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2309

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2323

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2337

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2350

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2363

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2380

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2393

WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

2415

WREG32(mmRLC_JUMP_TABLE_RESTORE,

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

403

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4215

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4521

WREG32(mmSQ_CMD, value);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4579

WREG32(mec_int_cntl_reg, mec_int_cntl);

sys/dev/drm/amd/amdgpu/gfx_v9_0.c

4585

WREG32(mec_int_cntl_reg, mec_int_cntl);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

100

WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

113

WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

117

WREG32(mmBIF_FB_EN, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1225

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1231

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1262

WREG32(mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1266

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1272

WREG32(mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

1276

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

204

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

205

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

209

WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

210

WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

214

WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

217

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

218

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

219

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

264

WREG32((0xb05 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

265

WREG32((0xb06 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

266

WREG32((0xb07 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

267

WREG32((0xb08 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

268

WREG32((0xb09 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

270

WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

279

WREG32(mmVGA_HDP_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

284

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

287

WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

289

WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

291

WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

293

WREG32(mmMC_VM_AGP_BASE, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

294

WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

295

WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

300

WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

304

WREG32(mmHDP_MISC_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

307

WREG32(mmHDP_HOST_PATH_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

436

WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

532

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

565

WREG32(mmVM_PRT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

572

WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

573

WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

574

WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

575

WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

576

WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

577

WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

578

WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

579

WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

581

WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

582

WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

583

WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

584

WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

585

WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

586

WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

587

WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

588

WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

626

WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

636

WREG32(mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

639

WREG32(mmVM_L2_CNTL2, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

646

WREG32(mmVM_L2_CNTL3, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

648

WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

649

WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

650

WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

651

WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

653

WREG32(mmVM_CONTEXT0_CNTL2, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

658

WREG32(mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

660

WREG32(0x575, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

661

WREG32(0x576, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

662

WREG32(0x577, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

669

WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

670

WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

673

WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

676

WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

681

WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

683

WREG32(mmVM_CONTEXT1_CNTL2, 4);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

689

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

698

WREG32(mmCHUB_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

738

WREG32(mmVM_CONTEXT0_CNTL, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

739

WREG32(mmVM_CONTEXT1_CNTL, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

745

WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

749

WREG32(mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

750

WREG32(mmVM_L2_CNTL2, 0);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

833

WREG32(mc_cg_registers[i], data);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

850

WREG32(mc_cg_registers[i], data);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

890

WREG32(mmHDP_HOST_PATH_CNTL, data);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

906

WREG32(mmHDP_MEM_POWER_LS, data);

sys/dev/drm/amd/amdgpu/gmc_v7_0.c

96

WREG32(mmBIF_FB_EN, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1388

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1394

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1434

WREG32(mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1438

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1444

WREG32(mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1448

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1532

WREG32(mmMC_HUB_MISC_HUB_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1536

WREG32(mmMC_HUB_MISC_SIP_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1540

WREG32(mmMC_HUB_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1544

WREG32(mmMC_XPB_CLK_GAT, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1548

WREG32(mmATC_MISC_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1552

WREG32(mmMC_CITF_MISC_WR_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1556

WREG32(mmMC_CITF_MISC_RD_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1560

WREG32(mmMC_CITF_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1564

WREG32(mmVM_L2_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1568

WREG32(mmMC_HUB_MISC_HUB_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1572

WREG32(mmMC_HUB_MISC_SIP_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1576

WREG32(mmMC_HUB_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1580

WREG32(mmMC_XPB_CLK_GAT, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1584

WREG32(mmATC_MISC_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1588

WREG32(mmMC_CITF_MISC_WR_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1592

WREG32(mmMC_CITF_MISC_RD_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1596

WREG32(mmMC_CITF_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1600

WREG32(mmVM_L2_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1612

WREG32(mmMC_HUB_MISC_HUB_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1616

WREG32(mmMC_HUB_MISC_SIP_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1620

WREG32(mmMC_HUB_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1624

WREG32(mmMC_XPB_CLK_GAT, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1628

WREG32(mmATC_MISC_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1632

WREG32(mmMC_CITF_MISC_WR_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1636

WREG32(mmMC_CITF_MISC_RD_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1640

WREG32(mmMC_CITF_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1644

WREG32(mmVM_L2_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1648

WREG32(mmMC_HUB_MISC_HUB_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1652

WREG32(mmMC_HUB_MISC_SIP_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1656

WREG32(mmMC_HUB_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1660

WREG32(mmMC_XPB_CLK_GAT, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1664

WREG32(mmATC_MISC_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1668

WREG32(mmMC_CITF_MISC_WR_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1672

WREG32(mmMC_CITF_MISC_RD_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1676

WREG32(mmMC_CITF_MISC_VM_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

1680

WREG32(mmVM_L2_CG, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

184

WREG32(mmBIF_FB_EN, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

188

WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

201

WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

205

WREG32(mmBIF_FB_EN, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

329

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

330

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

334

WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

335

WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

339

WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

342

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

343

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

344

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

396

WREG32(mmMC_SEQ_MISC0, data);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

400

WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

401

WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

404

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

405

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

409

WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

412

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

413

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

414

WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

455

WREG32((0xb05 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

456

WREG32((0xb06 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

457

WREG32((0xb07 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

458

WREG32((0xb08 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

459

WREG32((0xb09 + j), 0x00000000);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

461

WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

470

WREG32(mmVGA_HDP_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

475

WREG32(mmVGA_RENDER_CONTROL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

478

WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

480

WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

482

WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

488

WREG32(mmMC_VM_FB_LOCATION, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

490

WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

491

WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

492

WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

495

WREG32(mmMC_VM_AGP_BASE, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

496

WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

497

WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

502

WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

506

WREG32(mmHDP_MISC_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

509

WREG32(mmHDP_HOST_PATH_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

639

WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

759

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

792

WREG32(mmVM_PRT_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

799

WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

800

WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

801

WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

802

WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

803

WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

804

WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

805

WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

806

WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

808

WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

809

WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

810

WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

811

WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

812

WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

813

WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

814

WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

815

WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

853

WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

863

WREG32(mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

867

WREG32(mmVM_L2_CNTL2, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

874

WREG32(mmVM_L2_CNTL3, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

889

WREG32(mmVM_L2_CNTL4, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

891

WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

892

WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

893

WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

894

WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

896

WREG32(mmVM_CONTEXT0_CNTL2, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

901

WREG32(mmVM_CONTEXT0_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

903

WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

904

WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

905

WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

912

WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

913

WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

916

WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

919

WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

924

WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

926

WREG32(mmVM_CONTEXT1_CNTL2, 4);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

939

WREG32(mmVM_CONTEXT1_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

982

WREG32(mmVM_CONTEXT0_CNTL, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

983

WREG32(mmVM_CONTEXT1_CNTL, 0);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

989

WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

993

WREG32(mmVM_L2_CNTL, tmp);

sys/dev/drm/amd/amdgpu/gmc_v8_0.c

994

WREG32(mmVM_L2_CNTL2, 0);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

226

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/gmc_v9_0.c

237

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/iceland_ih.c

114

WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/iceland_ih.c

122

WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

125

WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/iceland_ih.c

137

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/iceland_ih.c

138

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/iceland_ih.c

140

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

143

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

144

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

152

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

205

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/iceland_ih.c

278

WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);

sys/dev/drm/amd/amdgpu/iceland_ih.c

396

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/iceland_ih.c

402

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/iceland_ih.c

65

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

66

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

84

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

85

WREG32(mmIH_CNTL, ih_cntl);

sys/dev/drm/amd/amdgpu/iceland_ih.c

87

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/iceland_ih.c

88

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/kv_dpm.c

133

WREG32(mmDOUT_SCRATCH3, v);

sys/dev/drm/amd/amdgpu/kv_dpm.c

450

WREG32(config_regs->offset, data);

sys/dev/drm/amd/amdgpu/kv_smc.c

169

WREG32(mmSMC_IND_DATA_0, data);

sys/dev/drm/amd/amdgpu/kv_smc.c

182

WREG32(mmSMC_IND_DATA_0, data);

sys/dev/drm/amd/amdgpu/kv_smc.c

215

WREG32(mmSMC_IND_DATA_0, data);

sys/dev/drm/amd/amdgpu/kv_smc.c

38

WREG32(mmSMC_MESSAGE_0, id & SMC_MESSAGE_0__SMC_MSG_MASK);

sys/dev/drm/amd/amdgpu/kv_smc.c

73

WREG32(mmSMC_MSG_ARG_0, parameter);

sys/dev/drm/amd/amdgpu/kv_smc.c

86

WREG32(mmSMC_IND_INDEX_0, smc_address);

sys/dev/drm/amd/amdgpu/nbio_v6_1.c

87

WREG32(reg, doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v7_0.c

85

WREG32(reg, doorbell_range);

sys/dev/drm/amd/amdgpu/nbio_v7_4.c

83

WREG32(reg, doorbell_range);

sys/dev/drm/amd/amdgpu/psp_v10_0.c

431

WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

496

WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);

sys/dev/drm/amd/amdgpu/psp_v11_0.c

530

WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

551

WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);

sys/dev/drm/amd/amdgpu/psp_v3_1.c

596

WREG32(offset, 0x70000);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1002

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1008

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1031

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1036

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1047

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

1052

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

223

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

347

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

350

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

392

WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

420

WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

421

WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

426

WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

429

WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

440

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

443

WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

444

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

445

WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

446

WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

449

WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

451

WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

456

WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

457

WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

460

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

464

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

472

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

987

WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v2_4.c

994

WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1337

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1343

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1366

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1371

WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1382

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1387

WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1467

WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1482

WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1500

WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

1508

WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

396

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

521

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

524

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

587

WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

589

WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

599

WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

627

WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

658

WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

659

WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

664

WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

667

WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

678

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

682

WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

684

WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

685

WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

688

WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

690

WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

695

WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

696

WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

707

WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

712

WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

714

WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

719

WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

728

WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

732

WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v3_0.c

740

WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1464

WREG32(reg_offset, sdma_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1539

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1552

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1567

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1580

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_CLK_CTRL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1597

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1604

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1611

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

1618

WREG32(SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

421

WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

422

WREG32(sdma_v4_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

574

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

577

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

638

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

640

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

642

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

645

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

671

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

699

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

710

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

713

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

714

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

715

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

716

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

719

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

721

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

726

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

727

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

732

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

735

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

736

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

749

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

750

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

758

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

763

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

769

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

774

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

776

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

783

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

787

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

795

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

829

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

835

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

847

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

853

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

863

WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

926

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

929

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));

sys/dev/drm/amd/amdgpu/sdma_v4_0.c

931

WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);

sys/dev/drm/amd/amdgpu/si_dpm.c

2769

WREG32(CG_CAC_CTRL, reg);

sys/dev/drm/amd/amdgpu/si_dpm.c

2866

WREG32(config_regs->offset, data);

sys/dev/drm/amd/amdgpu/si_dpm.c

3114

WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);

sys/dev/drm/amd/amdgpu/si_dpm.c

3115

WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);

sys/dev/drm/amd/amdgpu/si_dpm.c

3119

WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);

sys/dev/drm/amd/amdgpu/si_dpm.c

3120

WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);

sys/dev/drm/amd/amdgpu/si_dpm.c

3124

WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);

sys/dev/drm/amd/amdgpu/si_dpm.c

3125

WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);

sys/dev/drm/amd/amdgpu/si_dpm.c

3129

WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);

sys/dev/drm/amd/amdgpu/si_dpm.c

3130

WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);

sys/dev/drm/amd/amdgpu/si_dpm.c

3138

WREG32(MC_CG_CONFIG, mc_cg_config);

sys/dev/drm/amd/amdgpu/si_dpm.c

3673

WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);

sys/dev/drm/amd/amdgpu/si_dpm.c

3845

WREG32(SMC_SCRATCH0, parameter);

sys/dev/drm/amd/amdgpu/si_dpm.c

4064

WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);

sys/dev/drm/amd/amdgpu/si_dpm.c

4075

WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);

sys/dev/drm/amd/amdgpu/si_dpm.c

4162

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4181

WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4225

WREG32(CG_BSP, pi->dsp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4239

WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));

sys/dev/drm/amd/amdgpu/si_dpm.c

4255

WREG32(CG_TPC, R600_TPC_DFLT);

sys/dev/drm/amd/amdgpu/si_dpm.c

4260

WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));

sys/dev/drm/amd/amdgpu/si_dpm.c

4274

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

4281

WREG32(CG_FTV, pi->vrc);

sys/dev/drm/amd/amdgpu/si_dpm.c

4286

WREG32(CG_FTV, 0);

sys/dev/drm/amd/amdgpu/si_dpm.c

5229

WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);

sys/dev/drm/amd/amdgpu/si_dpm.c

5230

WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);

sys/dev/drm/amd/amdgpu/si_dpm.c

5998

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

sys/dev/drm/amd/amdgpu/si_dpm.c

5999

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

sys/dev/drm/amd/amdgpu/si_dpm.c

6000

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

sys/dev/drm/amd/amdgpu/si_dpm.c

6001

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

sys/dev/drm/amd/amdgpu/si_dpm.c

6002

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

sys/dev/drm/amd/amdgpu/si_dpm.c

6003

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

sys/dev/drm/amd/amdgpu/si_dpm.c

6004

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

sys/dev/drm/amd/amdgpu/si_dpm.c

6005

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

sys/dev/drm/amd/amdgpu/si_dpm.c

6006

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

sys/dev/drm/amd/amdgpu/si_dpm.c

6007

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

sys/dev/drm/amd/amdgpu/si_dpm.c

6008

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

sys/dev/drm/amd/amdgpu/si_dpm.c

6009

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

sys/dev/drm/amd/amdgpu/si_dpm.c

6010

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

sys/dev/drm/amd/amdgpu/si_dpm.c

6011

WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));

sys/dev/drm/amd/amdgpu/si_dpm.c

6401

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/amd/amdgpu/si_dpm.c

6409

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/amd/amdgpu/si_dpm.c

6455

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6459

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6615

WREG32(CG_FDO_CTRL0, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6695

WREG32(CG_TACH_CTRL, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6711

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6715

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6735

WREG32(CG_TACH_CTRL, tmp);

sys/dev/drm/amd/amdgpu/si_dpm.c

6740

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/amd/amdgpu/soc15.c

101

WREG32(address, reg);

sys/dev/drm/amd/amdgpu/soc15.c

103

WREG32(data, v);

sys/dev/drm/amd/amdgpu/soc15.c

117

WREG32(address, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/soc15.c

131

WREG32(address, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/soc15.c

132

WREG32(data, (v));

sys/dev/drm/amd/amdgpu/soc15.c

145

WREG32(address, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

159

WREG32(address, (reg));

sys/dev/drm/amd/amdgpu/soc15.c

160

WREG32(data, (v));

sys/dev/drm/amd/amdgpu/soc15.c

228

WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);

sys/dev/drm/amd/amdgpu/soc15.c

260

WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);

sys/dev/drm/amd/amdgpu/soc15.c

383

WREG32(reg, tmp);

sys/dev/drm/amd/amdgpu/soc15.c

86

WREG32(address, reg);

sys/dev/drm/amd/amdgpu/soc15.c

898

WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data);

sys/dev/drm/amd/amdgpu/soc15.c

908

WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data);

sys/dev/drm/amd/amdgpu/soc15.c

938

WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0), data);

sys/dev/drm/amd/amdgpu/soc15.c

953

WREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_LIGHT_SLEEP_CTRL), data);

sys/dev/drm/amd/amdgpu/soc15.c

971

WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0), data);

sys/dev/drm/amd/amdgpu/soc15_common.h

31

WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \

sys/dev/drm/amd/amdgpu/soc15_common.h

42

WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)

sys/dev/drm/amd/amdgpu/soc15_common.h

48

WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)

sys/dev/drm/amd/amdgpu/tonga_ih.c

110

WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);

sys/dev/drm/amd/amdgpu/tonga_ih.c

118

WREG32(mmINTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

122

WREG32(mmIH_RB_BASE, adev->irq.ih.rb_dma_addr >> 8);

sys/dev/drm/amd/amdgpu/tonga_ih.c

124

WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);

sys/dev/drm/amd/amdgpu/tonga_ih.c

136

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

143

WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

sys/dev/drm/amd/amdgpu/tonga_ih.c

144

WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

sys/dev/drm/amd/amdgpu/tonga_ih.c

147

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

148

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

160

WREG32(mmIH_DOORBELL_RPTR, ih_doorbell_rtpr);

sys/dev/drm/amd/amdgpu/tonga_ih.c

216

WREG32(mmIH_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/tonga_ih.c

297

WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);

sys/dev/drm/amd/amdgpu/tonga_ih.c

459

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/tonga_ih.c

465

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/tonga_ih.c

64

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

81

WREG32(mmIH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/amd/amdgpu/tonga_ih.c

83

WREG32(mmIH_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/tonga_ih.c

84

WREG32(mmIH_RB_WPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

271

WREG32(mmUVD_CGC_GATE, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

278

WREG32(mmUVD_VCPU_CNTL, 1 << 9);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

288

WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

289

WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

291

WREG32(mmUVD_LMI_CTRL, 0x203108);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

294

WREG32(mmUVD_MPC_CNTL, tmp | 0x10);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

296

WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

297

WREG32(mmUVD_MPC_SET_MUXA1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

298

WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

299

WREG32(mmUVD_MPC_SET_MUXB1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

300

WREG32(mmUVD_MPC_SET_ALU, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

301

WREG32(mmUVD_MPC_SET_MUX, 0x88);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

351

WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

354

WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

357

WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

361

WREG32(mmUVD_RBC_RB_RPTR, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

364

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

367

WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

389

WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

432

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

436

WREG32(mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

485

WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

558

WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

559

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

563

WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

564

WREG32(mmUVD_VCPU_CACHE_SIZE1, size);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

569

WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

570

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

574

WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

578

WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

580

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

581

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

582

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

598

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

607

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

634

WREG32(mmUVD_CGC_CTRL, tmp);

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

711

WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

722

WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK |

sys/dev/drm/amd/amdgpu/uvd_v4_2.c

90

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

261

WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

263

WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

268

WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

269

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

273

WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

274

WREG32(mmUVD_VCPU_CACHE_SIZE1, size);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

279

WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

280

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

282

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

283

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

284

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

319

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

331

WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

339

WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

340

WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

342

WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

343

WREG32(mmUVD_MPC_SET_MUXA1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

344

WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

345

WREG32(mmUVD_MPC_SET_MUXB1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

346

WREG32(mmUVD_MPC_SET_ALU, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

347

WREG32(mmUVD_MPC_SET_MUX, 0x88);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

350

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

354

WREG32(mmUVD_VCPU_CNTL, 1 << 9);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

360

WREG32(mmUVD_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

403

WREG32(mmUVD_RBC_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

406

WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

409

WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

412

WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

414

WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

418

WREG32(mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

421

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

438

WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

445

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

449

WREG32(mmUVD_VCPU_CNTL, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

454

WREG32(mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

501

WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

653

WREG32(mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

654

WREG32(mmUVD_CGC_GATE, data3);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

700

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

701

WREG32(mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

740

WREG32(mmUVD_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

741

WREG32(mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

758

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

767

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v5_0.c

87

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1187

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1193

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1307

WREG32(mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1308

WREG32(mmUVD_CGC_GATE, data3);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1355

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1356

WREG32(mmUVD_SUVD_CGC_CTRL, data2);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1397

WREG32(mmUVD_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1398

WREG32(mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1415

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

142

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1424

WREG32(mmUVD_CGC_CTRL, data);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

1462

WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

157

WREG32(mmUVD_RB_WPTR,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

160

WREG32(mmUVD_RB_WPTR2,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

593

WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

595

WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

600

WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

601

WREG32(mmUVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

605

WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

606

WREG32(mmUVD_VCPU_CACHE_SIZE1, size);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

611

WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

612

WREG32(mmUVD_VCPU_CACHE_SIZE2, size);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

614

WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

615

WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

616

WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

618

WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

695

WREG32(mmUVD_CGC_GATE, data);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

696

WREG32(mmUVD_SUVD_CGC_GATE, data1);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

732

WREG32(mmUVD_SOFT_RESET,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

748

WREG32(mmUVD_LMI_CTRL,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

761

WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

762

WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

764

WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

765

WREG32(mmUVD_MPC_SET_MUXA1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

766

WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

767

WREG32(mmUVD_MPC_SET_MUXB1, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

768

WREG32(mmUVD_MPC_SET_ALU, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

769

WREG32(mmUVD_MPC_SET_MUX, 0x88);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

772

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

776

WREG32(mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

782

WREG32(mmUVD_SOFT_RESET, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

826

WREG32(mmUVD_RBC_RB_CNTL, tmp);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

829

WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

832

WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

835

WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

837

WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

841

WREG32(mmUVD_RBC_RB_RPTR, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

844

WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

850

WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

851

WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

852

WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

853

WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

854

WREG32(mmUVD_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

857

WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

858

WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

859

WREG32(mmUVD_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

860

WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

861

WREG32(mmUVD_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

877

WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

884

WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

888

WREG32(mmUVD_VCPU_CNTL, 0x0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

893

WREG32(mmUVD_STATUS, 0);

sys/dev/drm/amd/amdgpu/uvd_v6_0.c

970

WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1508

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/uvd_v7_0.c

1514

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

144

WREG32(mmVCE_CGTT_CLK_OVERRIDE, 7);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

155

WREG32(mmVCE_CLOCK_GATING_A, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

160

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

165

WREG32(mmVCE_CLOCK_GATING_B, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

175

WREG32(mmVCE_CLOCK_GATING_B, 0xf7);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

177

WREG32(mmVCE_LMI_CTRL, 0x00398000);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

179

WREG32(mmVCE_LMI_SWAP_CNTL, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

180

WREG32(mmVCE_LMI_SWAP_CNTL1, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

181

WREG32(mmVCE_LMI_VM_CTRL, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

183

WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

187

WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

188

WREG32(mmVCE_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

192

WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

193

WREG32(mmVCE_VCPU_CACHE_SIZE1, size);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

197

WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

198

WREG32(mmVCE_VCPU_CACHE_SIZE2, size);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

244

WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

245

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

246

WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

247

WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

248

WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

251

WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

252

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

253

WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

254

WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

255

WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

305

WREG32(mmVCE_STATUS, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

317

WREG32(mmVCE_CLOCK_GATING_B, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

321

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

325

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

327

WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

332

WREG32(mmVCE_CLOCK_GATING_B, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

337

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

341

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

358

WREG32(mmVCE_CLOCK_GATING_B, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

362

WREG32(mmVCE_CLOCK_GATING_B, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

369

WREG32(mmVCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

374

WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

377

WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

380

WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);

sys/dev/drm/amd/amdgpu/vce_v2_0.c

94

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v2_0.c

96

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

118

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

120

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

129

WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

149

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

151

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

154

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

156

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

158

WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

160

WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

186

WREG32(mmVCE_CLOCK_GATING_B, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

191

WREG32(mmVCE_UENC_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

196

WREG32(mmVCE_UENC_CLOCK_GATING_2, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

200

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

207

WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

212

WREG32(mmVCE_CLOCK_GATING_B, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

216

WREG32(mmVCE_UENC_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

220

WREG32(mmVCE_UENC_CLOCK_GATING_2, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

224

WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

231

WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

276

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

282

WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

283

WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

284

WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

285

WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

286

WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

289

WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

290

WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

291

WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

292

WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

293

WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

296

WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

297

WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

298

WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

299

WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

300

WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

326

WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

341

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

352

WREG32(mmVCE_STATUS, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

355

WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

537

WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

539

WREG32(mmVCE_LMI_CTRL, 0x00398000);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

541

WREG32(mmVCE_LMI_SWAP_CNTL, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

542

WREG32(mmVCE_LMI_SWAP_CNTL1, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

543

WREG32(mmVCE_LMI_VM_CTRL, 0);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

547

WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

548

WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

549

WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

551

WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

554

WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

555

WREG32(mmVCE_VCPU_CACHE_SIZE0, size);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

560

WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

561

WREG32(mmVCE_VCPU_CACHE_SIZE1, size);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

564

WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

565

WREG32(mmVCE_VCPU_CACHE_SIZE2, size);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

569

WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

570

WREG32(mmVCE_VCPU_CACHE_SIZE1, size);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

573

WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

574

WREG32(mmVCE_VCPU_CACHE_SIZE2, size);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

629

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

634

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

639

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

666

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

672

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

760

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

767

WREG32(mmVCE_CLOCK_GATING_A, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

773

WREG32(mmVCE_UENC_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

779

WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

sys/dev/drm/amd/amdgpu/vce_v3_0.c

86

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

88

WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));

sys/dev/drm/amd/amdgpu/vce_v3_0.c

97

WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

114

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

117

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

120

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

163

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

164

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI), upper_32_bits(addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

170

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_VMID), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

173

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

176

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

184

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST), 0x10000001);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

337

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

338

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

339

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

340

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

341

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

345

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

346

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

347

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

348

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

349

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE2), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

353

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

354

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

355

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

356

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

357

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE3), ring->ring_size / 4);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

609

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

611

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 0x00398000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

613

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

614

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL1), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

615

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

622

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

624

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

626

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), 0);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

628

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

630

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR0),

sys/dev/drm/amd/amdgpu/vce_v4_0.c

632

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), offset & ~0x0f000000);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

636

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

638

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

639

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

642

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

643

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

645

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

646

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xff);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

649

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), (offset & ~0x0f000000) | (2 << 24));

sys/dev/drm/amd/amdgpu/vce_v4_0.c

650

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

751

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

757

WREG32(mmSRBM_SOFT_RESET, tmp);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

803

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_ARB_CTRL), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

823

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

828

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

833

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

837

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

844

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

849

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

853

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

857

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING_2), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

861

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_REG_CLOCK_GATING), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

868

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_DMA_DCLK_CTRL), data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

913

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_A, data);

sys/dev/drm/amd/amdgpu/vce_v4_0.c

919

WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_UENC_CLOCK_GATING, data);

sys/dev/drm/amd/amdgpu/vi.c

102

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/vi.c

104

WREG32(mmPCIE_DATA, v);

sys/dev/drm/amd/amdgpu/vi.c

126

WREG32(mmSMC_IND_INDEX_11, (reg));

sys/dev/drm/amd/amdgpu/vi.c

127

WREG32(mmSMC_IND_DATA_11, (v));

sys/dev/drm/amd/amdgpu/vi.c

1305

WREG32(mmHDP_HOST_PATH_CNTL, data);

sys/dev/drm/amd/amdgpu/vi.c

1321

WREG32(mmHDP_MEM_POWER_LS, data);

sys/dev/drm/amd/amdgpu/vi.c

1337

WREG32(0x157a, data);

sys/dev/drm/amd/amdgpu/vi.c

141

WREG32(mmMP0PUB_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

152

WREG32(mmMP0PUB_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

153

WREG32(mmMP0PUB_IND_DATA, (v));

sys/dev/drm/amd/amdgpu/vi.c

163

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/vi.c

174

WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/amd/amdgpu/vi.c

175

WREG32(mmUVD_CTX_DATA, (v));

sys/dev/drm/amd/amdgpu/vi.c

185

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

196

WREG32(mmDIDT_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

197

WREG32(mmDIDT_IND_DATA, (v));

sys/dev/drm/amd/amdgpu/vi.c

207

WREG32(mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

218

WREG32(mmGC_CAC_IND_INDEX, (reg));

sys/dev/drm/amd/amdgpu/vi.c

219

WREG32(mmGC_CAC_IND_DATA, (v));

sys/dev/drm/amd/amdgpu/vi.c

366

WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);

sys/dev/drm/amd/amdgpu/vi.c

392

WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));

sys/dev/drm/amd/amdgpu/vi.c

395

WREG32(mmD1VGA_CONTROL,

sys/dev/drm/amd/amdgpu/vi.c

398

WREG32(mmD2VGA_CONTROL,

sys/dev/drm/amd/amdgpu/vi.c

401

WREG32(mmVGA_RENDER_CONTROL,

sys/dev/drm/amd/amdgpu/vi.c

409

WREG32(mmBUS_CNTL, bus_cntl);

sys/dev/drm/amd/amdgpu/vi.c

411

WREG32(mmD1VGA_CONTROL, d1vga_control);

sys/dev/drm/amd/amdgpu/vi.c

412

WREG32(mmD2VGA_CONTROL, d2vga_control);

sys/dev/drm/amd/amdgpu/vi.c

413

WREG32(mmVGA_RENDER_CONTROL, vga_render_control);

sys/dev/drm/amd/amdgpu/vi.c

439

WREG32(mmSMC_IND_INDEX_11, ixROM_INDEX);

sys/dev/drm/amd/amdgpu/vi.c

440

WREG32(mmSMC_IND_DATA_11, 0);

sys/dev/drm/amd/amdgpu/vi.c

442

WREG32(mmSMC_IND_INDEX_11, ixROM_DATA);

sys/dev/drm/amd/amdgpu/vi.c

887

WREG32(mmBIF_DOORBELL_APER_EN, tmp);

sys/dev/drm/amd/amdgpu/vi.c

90

WREG32(mmPCIE_INDEX, reg);

sys/dev/drm/amd/amdgpu/vi.c

907

WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);

sys/dev/drm/amd/amdgpu/vi.c

918

WREG32(mmHDP_DEBUG0, 1);

sys/dev/drm/radeon/atombios_crtc.c

1357

WREG32(AVIVO_D1VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1360

WREG32(AVIVO_D2VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1363

WREG32(EVERGREEN_D3VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1366

WREG32(EVERGREEN_D4VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1369

WREG32(EVERGREEN_D5VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1372

WREG32(EVERGREEN_D6VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1381

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1383

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1385

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1387

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1389

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1391

WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

sys/dev/drm/radeon/atombios_crtc.c

1392

WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

sys/dev/drm/radeon/atombios_crtc.c

1406

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1407

WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1408

WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1409

WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1410

WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

sys/dev/drm/radeon/atombios_crtc.c

1411

WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

sys/dev/drm/radeon/atombios_crtc.c

1414

WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/radeon/atombios_crtc.c

1415

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

sys/dev/drm/radeon/atombios_crtc.c

1418

WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1421

WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1425

WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1432

WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1436

WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1574

WREG32(AVIVO_D1VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1576

WREG32(AVIVO_D2VGA_CONTROL, 0);

sys/dev/drm/radeon/atombios_crtc.c

1581

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1585

WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1586

WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1588

WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1589

WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));

sys/dev/drm/radeon/atombios_crtc.c

1592

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1594

WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +

sys/dev/drm/radeon/atombios_crtc.c

1596

WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);

sys/dev/drm/radeon/atombios_crtc.c

1598

WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);

sys/dev/drm/radeon/atombios_crtc.c

1607

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1608

WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1609

WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1610

WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

1611

WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);

sys/dev/drm/radeon/atombios_crtc.c

1612

WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);

sys/dev/drm/radeon/atombios_crtc.c

1615

WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);

sys/dev/drm/radeon/atombios_crtc.c

1616

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);

sys/dev/drm/radeon/atombios_crtc.c

1618

WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1622

WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1626

WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_crtc.c

1630

WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);

sys/dev/drm/radeon/atombios_crtc.c

1688

WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);

sys/dev/drm/radeon/atombios_crtc.c

1693

WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);

sys/dev/drm/radeon/atombios_crtc.c

1694

WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));

sys/dev/drm/radeon/atombios_crtc.c

1695

WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));

sys/dev/drm/radeon/atombios_crtc.c

2153

WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

2155

WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_crtc.c

236

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);

sys/dev/drm/radeon/atombios_crtc.c

245

WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);

sys/dev/drm/radeon/atombios_crtc.c

402

WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);

sys/dev/drm/radeon/atombios_crtc.c

407

WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);

sys/dev/drm/radeon/atombios_crtc.c

418

WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);

sys/dev/drm/radeon/atombios_crtc.c

423

WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);

sys/dev/drm/radeon/atombios_encoders.c

1614

WREG32(reg, (ATOM_S3_TV1_ACTIVE |

sys/dev/drm/radeon/atombios_encoders.c

1617

WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));

sys/dev/drm/radeon/atombios_encoders.c

1619

WREG32(reg, 0);

sys/dev/drm/radeon/atombios_encoders.c

1627

WREG32(reg, temp);

sys/dev/drm/radeon/atombios_encoders.c

1688

WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);

sys/dev/drm/radeon/atombios_encoders.c

1690

WREG32(RADEON_BIOS_3_SCRATCH, reg);

sys/dev/drm/radeon/atombios_encoders.c

2131

WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);

sys/dev/drm/radeon/atombios_encoders.c

2140

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_encoders.c

2143

WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_encoders.c

2146

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_encoders.c

2149

WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_encoders.c

2152

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/atombios_encoders.c

2155

WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/atombios_encoders.c

69

WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);

sys/dev/drm/radeon/atombios_encoders.c

71

WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);

sys/dev/drm/radeon/btc_dpm.c

1343

WREG32(CG_BIF_REQ_AND_RSP, bif);

sys/dev/drm/radeon/btc_dpm.c

1362

WREG32(CG_BIF_REQ_AND_RSP, bif);

sys/dev/drm/radeon/btc_dpm.c

1415

WREG32(CG_ULV_CONTROL, BTC_CGULVCONTROL_DFLT);

sys/dev/drm/radeon/btc_dpm.c

1416

WREG32(CG_ULV_PARAMETER, BTC_CGULVPARAMETER_DFLT);

sys/dev/drm/radeon/btc_dpm.c

1447

WREG32(sequence[i], tmp);

sys/dev/drm/radeon/btc_dpm.c

1768

WREG32(MC_ARB_DRAM_TIMING, arb_registers->mc_arb_dram_timing);

sys/dev/drm/radeon/btc_dpm.c

1769

WREG32(MC_ARB_DRAM_TIMING2, arb_registers->mc_arb_dram_timing2);

sys/dev/drm/radeon/btc_dpm.c

2027

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

sys/dev/drm/radeon/btc_dpm.c

2028

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

sys/dev/drm/radeon/btc_dpm.c

2029

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

sys/dev/drm/radeon/btc_dpm.c

2030

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

sys/dev/drm/radeon/btc_dpm.c

2031

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

sys/dev/drm/radeon/btc_dpm.c

2032

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

sys/dev/drm/radeon/btc_dpm.c

2033

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

sys/dev/drm/radeon/btc_dpm.c

2034

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

sys/dev/drm/radeon/btc_dpm.c

2035

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

sys/dev/drm/radeon/btc_dpm.c

2036

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

sys/dev/drm/radeon/btc_dpm.c

2037

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

sys/dev/drm/radeon/btc_dpm.c

2073

WREG32(MC_PMG_AUTO_CFG, tmp);

sys/dev/drm/radeon/ci_dpm.c

1699

WREG32(SMC_MESSAGE_0, msg);

sys/dev/drm/radeon/ci_dpm.c

1715

WREG32(SMC_MSG_ARG_0, parameter);

sys/dev/drm/radeon/ci_dpm.c

1963

WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);

sys/dev/drm/radeon/ci_dpm.c

1974

WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);

sys/dev/drm/radeon/ci_dpm.c

4648

WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);

sys/dev/drm/radeon/ci_dpm.c

4651

WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);

sys/dev/drm/radeon/ci_dpm.c

4652

WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);

sys/dev/drm/radeon/ci_dpm.c

4670

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

sys/dev/drm/radeon/ci_dpm.c

4671

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

sys/dev/drm/radeon/ci_dpm.c

4672

WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));

sys/dev/drm/radeon/ci_dpm.c

4673

WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));

sys/dev/drm/radeon/ci_dpm.c

4674

WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));

sys/dev/drm/radeon/ci_dpm.c

4675

WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));

sys/dev/drm/radeon/ci_dpm.c

4676

WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));

sys/dev/drm/radeon/ci_dpm.c

4677

WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));

sys/dev/drm/radeon/ci_dpm.c

4678

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

sys/dev/drm/radeon/ci_dpm.c

4679

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

sys/dev/drm/radeon/ci_dpm.c

4680

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

sys/dev/drm/radeon/ci_dpm.c

4681

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

sys/dev/drm/radeon/ci_dpm.c

4682

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

sys/dev/drm/radeon/ci_dpm.c

4683

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

sys/dev/drm/radeon/ci_dpm.c

4684

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

sys/dev/drm/radeon/ci_dpm.c

4685

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

sys/dev/drm/radeon/ci_dpm.c

4686

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

sys/dev/drm/radeon/ci_dpm.c

4687

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

sys/dev/drm/radeon/ci_dpm.c

4688

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

sys/dev/drm/radeon/ci_dpm.c

4689

WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));

sys/dev/drm/radeon/ci_dpm.c

598

WREG32(config_regs->offset << 2, data);

sys/dev/drm/radeon/ci_smc.c

105

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/ci_smc.c

229

WREG32(SMC_IND_INDEX_0, ucode_start_address);

sys/dev/drm/radeon/ci_smc.c

235

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/ci_smc.c

270

WREG32(SMC_IND_DATA_0, value);

sys/dev/drm/radeon/ci_smc.c

41

WREG32(SMC_IND_INDEX_0, smc_address);

sys/dev/drm/radeon/ci_smc.c

73

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/cik.c

176

WREG32(CIK_DIDT_IND_INDEX, (reg));

sys/dev/drm/radeon/cik.c

1843

WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);

sys/dev/drm/radeon/cik.c

187

WREG32(CIK_DIDT_IND_INDEX, (reg));

sys/dev/drm/radeon/cik.c

188

WREG32(CIK_DIDT_IND_DATA, (v));

sys/dev/drm/radeon/cik.c

1901

WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/radeon/cik.c

1902

WREG32(MC_SEQ_SUP_CNTL, 0x00000010);

sys/dev/drm/radeon/cik.c

1907

WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));

sys/dev/drm/radeon/cik.c

1908

WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));

sys/dev/drm/radeon/cik.c

1910

WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);

sys/dev/drm/radeon/cik.c

1911

WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);

sys/dev/drm/radeon/cik.c

1917

WREG32(MC_SEQ_IO_DEBUG_INDEX, 5);

sys/dev/drm/radeon/cik.c

1918

WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023);

sys/dev/drm/radeon/cik.c

1919

WREG32(MC_SEQ_IO_DEBUG_INDEX, 9);

sys/dev/drm/radeon/cik.c

1920

WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0);

sys/dev/drm/radeon/cik.c

1926

WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));

sys/dev/drm/radeon/cik.c

1928

WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

1932

WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/radeon/cik.c

1933

WREG32(MC_SEQ_SUP_CNTL, 0x00000004);

sys/dev/drm/radeon/cik.c

1934

WREG32(MC_SEQ_SUP_CNTL, 0x00000001);

sys/dev/drm/radeon/cik.c

238

WREG32(PCIE_INDEX, reg);

sys/dev/drm/radeon/cik.c

250

WREG32(PCIE_INDEX, reg);

sys/dev/drm/radeon/cik.c

2519

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

sys/dev/drm/radeon/cik.c

252

WREG32(PCIE_DATA, v);

sys/dev/drm/radeon/cik.c

2521

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

sys/dev/drm/radeon/cik.c

2662

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

sys/dev/drm/radeon/cik.c

2664

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

sys/dev/drm/radeon/cik.c

2887

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

sys/dev/drm/radeon/cik.c

2889

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

sys/dev/drm/radeon/cik.c

3030

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

sys/dev/drm/radeon/cik.c

3032

WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);

sys/dev/drm/radeon/cik.c

3064

WREG32(GRBM_GFX_INDEX, data);

sys/dev/drm/radeon/cik.c

3181

WREG32(PA_SC_RASTER_CONFIG, data);

sys/dev/drm/radeon/cik.c

3277

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

3278

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

3279

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/cik.c

3280

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

3281

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

3284

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

sys/dev/drm/radeon/cik.c

3285

WREG32(SRBM_INT_CNTL, 0x1);

sys/dev/drm/radeon/cik.c

3286

WREG32(SRBM_INT_ACK, 0x1);

sys/dev/drm/radeon/cik.c

3288

WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);

sys/dev/drm/radeon/cik.c

3350

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3351

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3352

WREG32(DMIF_ADDR_CALC, gb_addr_config);

sys/dev/drm/radeon/cik.c

3353

WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/drm/radeon/cik.c

3354

WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);

sys/dev/drm/radeon/cik.c

3355

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3356

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3357

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/cik.c

3374

WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));

sys/dev/drm/radeon/cik.c

3376

WREG32(SX_DEBUG_1, 0x20);

sys/dev/drm/radeon/cik.c

3378

WREG32(TA_CNTL_AUX, 0x00010000);

sys/dev/drm/radeon/cik.c

3382

WREG32(SPI_CONFIG_CNTL, tmp);

sys/dev/drm/radeon/cik.c

3384

WREG32(SQ_CONFIG, 1);

sys/dev/drm/radeon/cik.c

3386

WREG32(DB_DEBUG, 0);

sys/dev/drm/radeon/cik.c

3390

WREG32(DB_DEBUG2, tmp);

sys/dev/drm/radeon/cik.c

3394

WREG32(DB_DEBUG3, tmp);

sys/dev/drm/radeon/cik.c

3398

WREG32(CB_HW_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

3400

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));

sys/dev/drm/radeon/cik.c

3402

WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |

sys/dev/drm/radeon/cik.c

3407

WREG32(VGT_NUM_INSTANCES, 1);

sys/dev/drm/radeon/cik.c

3409

WREG32(CP_PERFMON_CNTL, 0);

sys/dev/drm/radeon/cik.c

3411

WREG32(SQ_CONFIG, 0);

sys/dev/drm/radeon/cik.c

3413

WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |

sys/dev/drm/radeon/cik.c

3416

WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |

sys/dev/drm/radeon/cik.c

3419

WREG32(VGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/radeon/cik.c

3420

WREG32(PA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/radeon/cik.c

3424

WREG32(HDP_MISC_CNTL, tmp);

sys/dev/drm/radeon/cik.c

3427

WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);

sys/dev/drm/radeon/cik.c

3429

WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));

sys/dev/drm/radeon/cik.c

3430

WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);

sys/dev/drm/radeon/cik.c

3483

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/radeon/cik.c

3808

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/radeon/cik.c

3892

WREG32(CP_ME_CNTL, 0);

sys/dev/drm/radeon/cik.c

3896

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));

sys/dev/drm/radeon/cik.c

3937

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

3939

WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

3940

WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

3946

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

3948

WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

3949

WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

3955

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/cik.c

3957

WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

3958

WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

3959

WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

3965

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

3967

WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

3968

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

3972

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

3974

WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

3975

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

3979

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/cik.c

3981

WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

3982

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/cik.c

4003

WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);

sys/dev/drm/radeon/cik.c

4004

WREG32(CP_ENDIAN_SWAP, 0);

sys/dev/drm/radeon/cik.c

4005

WREG32(CP_DEVICE_ID, 1);

sys/dev/drm/radeon/cik.c

4080

WREG32(CP_SEM_WAIT_TIMER, 0x0);

sys/dev/drm/radeon/cik.c

4082

WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);

sys/dev/drm/radeon/cik.c

4085

WREG32(CP_RB_WPTR_DELAY, 0);

sys/dev/drm/radeon/cik.c

4088

WREG32(CP_RB_VMID, 0);

sys/dev/drm/radeon/cik.c

4090

WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);

sys/dev/drm/radeon/cik.c

4100

WREG32(CP_RB0_CNTL, tmp);

sys/dev/drm/radeon/cik.c

4103

WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);

sys/dev/drm/radeon/cik.c

4105

WREG32(CP_RB0_WPTR, ring->wptr);

sys/dev/drm/radeon/cik.c

4108

WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/cik.c

4109

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/cik.c

4112

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/cik.c

4118

WREG32(CP_RB0_CNTL, tmp);

sys/dev/drm/radeon/cik.c

4121

WREG32(CP_RB0_BASE, rb_addr);

sys/dev/drm/radeon/cik.c

4122

WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));

sys/dev/drm/radeon/cik.c

4161

WREG32(CP_RB0_WPTR, ring->wptr);

sys/dev/drm/radeon/cik.c

4219

WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);

sys/dev/drm/radeon/cik.c

4222

WREG32(CP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/drm/radeon/cik.c

4228

WREG32(CP_HQD_DEQUEUE_REQUEST, 0);

sys/dev/drm/radeon/cik.c

4229

WREG32(CP_HQD_PQ_RPTR, 0);

sys/dev/drm/radeon/cik.c

4230

WREG32(CP_HQD_PQ_WPTR, 0);

sys/dev/drm/radeon/cik.c

4246

WREG32(CP_MEC_CNTL, 0);

sys/dev/drm/radeon/cik.c

4257

WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));

sys/dev/drm/radeon/cik.c

4293

WREG32(CP_MEC_ME1_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

4295

WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

4296

WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

4307

WREG32(CP_MEC_ME2_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

4309

WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

4310

WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

4317

WREG32(CP_MEC_ME1_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

4319

WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

4320

WREG32(CP_MEC_ME1_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

4325

WREG32(CP_MEC_ME2_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

4327

WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

4328

WREG32(CP_MEC_ME2_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

4553

WREG32(CP_CPF_DEBUG, tmp);

sys/dev/drm/radeon/cik.c

4566

WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);

sys/dev/drm/radeon/cik.c

4567

WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);

sys/dev/drm/radeon/cik.c

4570

WREG32(CP_HPD_EOP_VMID, 0);

sys/dev/drm/radeon/cik.c

4576

WREG32(CP_HPD_EOP_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

4638

WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);

sys/dev/drm/radeon/cik.c

4647

WREG32(CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/drm/radeon/cik.c

4655

WREG32(CP_HQD_DEQUEUE_REQUEST, 1);

sys/dev/drm/radeon/cik.c

4661

WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);

sys/dev/drm/radeon/cik.c

4662

WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);

sys/dev/drm/radeon/cik.c

4663

WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);

sys/dev/drm/radeon/cik.c

4669

WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);

sys/dev/drm/radeon/cik.c

4670

WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);

sys/dev/drm/radeon/cik.c

4674

WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);

sys/dev/drm/radeon/cik.c

4680

WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);

sys/dev/drm/radeon/cik.c

4681

WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);

sys/dev/drm/radeon/cik.c

4699

WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);

sys/dev/drm/radeon/cik.c

4708

WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);

sys/dev/drm/radeon/cik.c

4709

WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,

sys/dev/drm/radeon/cik.c

4720

WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,

sys/dev/drm/radeon/cik.c

4722

WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,

sys/dev/drm/radeon/cik.c

4739

WREG32(CP_HQD_PQ_DOORBELL_CONTROL,

sys/dev/drm/radeon/cik.c

4745

WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);

sys/dev/drm/radeon/cik.c

4750

WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);

sys/dev/drm/radeon/cik.c

4754

WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);

sys/dev/drm/radeon/cik.c

4973

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/drm/radeon/cik.c

4976

WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);

sys/dev/drm/radeon/cik.c

4982

WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

4988

WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5038

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/cik.c

5044

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/cik.c

5052

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/cik.c

5058

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/cik.c

5084

WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);

sys/dev/drm/radeon/cik.c

5085

WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |

sys/dev/drm/radeon/cik.c

5094

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5095

WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);

sys/dev/drm/radeon/cik.c

5098

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5100

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5101

WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);

sys/dev/drm/radeon/cik.c

5104

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5106

WREG32(GMCON_PGFSM_WRITE, 0x210000);

sys/dev/drm/radeon/cik.c

5107

WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);

sys/dev/drm/radeon/cik.c

5110

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5112

WREG32(GMCON_PGFSM_WRITE, 0x21003);

sys/dev/drm/radeon/cik.c

5113

WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);

sys/dev/drm/radeon/cik.c

5116

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5118

WREG32(GMCON_PGFSM_WRITE, 0x2b00);

sys/dev/drm/radeon/cik.c

5119

WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);

sys/dev/drm/radeon/cik.c

5122

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5124

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5125

WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);

sys/dev/drm/radeon/cik.c

5128

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5130

WREG32(GMCON_PGFSM_WRITE, 0x420000);

sys/dev/drm/radeon/cik.c

5131

WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);

sys/dev/drm/radeon/cik.c

5134

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5136

WREG32(GMCON_PGFSM_WRITE, 0x120202);

sys/dev/drm/radeon/cik.c

5137

WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);

sys/dev/drm/radeon/cik.c

5140

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5142

WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);

sys/dev/drm/radeon/cik.c

5143

WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);

sys/dev/drm/radeon/cik.c

5146

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5148

WREG32(GMCON_PGFSM_WRITE, 0x373f3e);

sys/dev/drm/radeon/cik.c

5149

WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);

sys/dev/drm/radeon/cik.c

5152

WREG32(GMCON_PGFSM_WRITE, 0);

sys/dev/drm/radeon/cik.c

5154

WREG32(GMCON_PGFSM_WRITE, 0x3e1332);

sys/dev/drm/radeon/cik.c

5155

WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);

sys/dev/drm/radeon/cik.c

5157

WREG32(GMCON_MISC3, save->gmcon_misc3);

sys/dev/drm/radeon/cik.c

5158

WREG32(GMCON_MISC, save->gmcon_misc);

sys/dev/drm/radeon/cik.c

5159

WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);

sys/dev/drm/radeon/cik.c

5177

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/drm/radeon/cik.c

5180

WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);

sys/dev/drm/radeon/cik.c

5185

WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5189

WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

5305

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

5306

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

5307

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/cik.c

5308

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

5309

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/cik.c

5311

WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/radeon/cik.c

5318

WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);

sys/dev/drm/radeon/cik.c

5320

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/cik.c

5322

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/cik.c

5324

WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,

sys/dev/drm/radeon/cik.c

5328

WREG32(MC_VM_FB_LOCATION, tmp);

sys/dev/drm/radeon/cik.c

5330

WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

sys/dev/drm/radeon/cik.c

5331

WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));

sys/dev/drm/radeon/cik.c

5332

WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

sys/dev/drm/radeon/cik.c

5333

WREG32(MC_VM_AGP_BASE, 0);

sys/dev/drm/radeon/cik.c

5334

WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/radeon/cik.c

5335

WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/radeon/cik.c

5428

WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/radeon/cik.c

5431

WREG32(VM_INVALIDATE_REQUEST, 0x1);

sys/dev/drm/radeon/cik.c

5457

WREG32(MC_VM_MX_L1_TLB_CNTL,

sys/dev/drm/radeon/cik.c

5465

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |

sys/dev/drm/radeon/cik.c

5471

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/drm/radeon/cik.c

5472

WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

sys/dev/drm/radeon/cik.c

5476

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/cik.c

5477

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

sys/dev/drm/radeon/cik.c

5478

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

sys/dev/drm/radeon/cik.c

5479

WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/cik.c

5481

WREG32(VM_CONTEXT0_CNTL2, 0);

sys/dev/drm/radeon/cik.c

5482

WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

sys/dev/drm/radeon/cik.c

5485

WREG32(0x15D4, 0);

sys/dev/drm/radeon/cik.c

5486

WREG32(0x15D8, 0);

sys/dev/drm/radeon/cik.c

5487

WREG32(0x15DC, 0);

sys/dev/drm/radeon/cik.c

5491

WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);

sys/dev/drm/radeon/cik.c

5492

WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);

sys/dev/drm/radeon/cik.c

5495

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

sys/dev/drm/radeon/cik.c

5498

WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),

sys/dev/drm/radeon/cik.c

5503

WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/cik.c

5505

WREG32(VM_CONTEXT1_CNTL2, 4);

sys/dev/drm/radeon/cik.c

5506

WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

sys/dev/drm/radeon/cik.c

5524

WREG32(CHUB_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

5533

WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT);

sys/dev/drm/radeon/cik.c

5534

WREG32(SH_MEM_APE1_BASE, 1);

sys/dev/drm/radeon/cik.c

5535

WREG32(SH_MEM_APE1_LIMIT, 0);

sys/dev/drm/radeon/cik.c

5536

WREG32(SH_MEM_BASES, 0);

sys/dev/drm/radeon/cik.c

5538

WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

5539

WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

5540

WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

5541

WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

5576

WREG32(VM_CONTEXT0_CNTL, 0);

sys/dev/drm/radeon/cik.c

5577

WREG32(VM_CONTEXT1_CNTL, 0);

sys/dev/drm/radeon/cik.c

5579

WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |

sys/dev/drm/radeon/cik.c

5582

WREG32(VM_L2_CNTL,

sys/dev/drm/radeon/cik.c

5588

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/cik.c

5589

WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

sys/dev/drm/radeon/cik.c

5793

WREG32(CP_INT_CNTL_RING0, tmp);

sys/dev/drm/radeon/cik.c

5805

WREG32(RLC_LB_CNTL, tmp);

sys/dev/drm/radeon/cik.c

5839

WREG32(RLC_CNTL, rlc);

sys/dev/drm/radeon/cik.c

5852

WREG32(RLC_CNTL, data);

sys/dev/drm/radeon/cik.c

5871

WREG32(RLC_GPR_REG2, tmp);

sys/dev/drm/radeon/cik.c

5892

WREG32(RLC_GPR_REG2, tmp);

sys/dev/drm/radeon/cik.c

5904

WREG32(RLC_CNTL, 0);

sys/dev/drm/radeon/cik.c

5920

WREG32(RLC_CNTL, RLC_ENABLE);

sys/dev/drm/radeon/cik.c

5947

WREG32(RLC_CGCG_CGLS_CTRL, tmp);

sys/dev/drm/radeon/cik.c

5955

WREG32(RLC_LB_CNTR_INIT, 0);

sys/dev/drm/radeon/cik.c

5956

WREG32(RLC_LB_CNTR_MAX, 0x00008000);

sys/dev/drm/radeon/cik.c

5959

WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

5960

WREG32(RLC_LB_PARAMS, 0x00600408);

sys/dev/drm/radeon/cik.c

5961

WREG32(RLC_LB_CNTL, 0x80000004);

sys/dev/drm/radeon/cik.c

5963

WREG32(RLC_MC_CNTL, 0);

sys/dev/drm/radeon/cik.c

5964

WREG32(RLC_UCODE_CNTL, 0);

sys/dev/drm/radeon/cik.c

5975

WREG32(RLC_GPM_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

5977

WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

5978

WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version));

sys/dev/drm/radeon/cik.c

6000

WREG32(RLC_GPM_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

6002

WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik.c

6003

WREG32(RLC_GPM_UCODE_ADDR, 0);

sys/dev/drm/radeon/cik.c

6010

WREG32(RLC_DRIVER_DMA_STATUS, 0);

sys/dev/drm/radeon/cik.c

6029

WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

6030

WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

6032

WREG32(RLC_SERDES_WR_CTRL, tmp2);

sys/dev/drm/radeon/cik.c

6049

WREG32(RLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/radeon/cik.c

6063

WREG32(CP_MEM_SLP_CNTL, data);

sys/dev/drm/radeon/cik.c

6071

WREG32(RLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/radeon/cik.c

6076

WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

6077

WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

6079

WREG32(RLC_SERDES_WR_CTRL, data);

sys/dev/drm/radeon/cik.c

6096

WREG32(CGTS_SM_CTRL_REG, data);

sys/dev/drm/radeon/cik.c

6102

WREG32(RLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/radeon/cik.c

6107

WREG32(RLC_MEM_SLP_CNTL, data);

sys/dev/drm/radeon/cik.c

6113

WREG32(CP_MEM_SLP_CNTL, data);

sys/dev/drm/radeon/cik.c

6119

WREG32(CGTS_SM_CTRL_REG, data);

sys/dev/drm/radeon/cik.c

6124

WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

6125

WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);

sys/dev/drm/radeon/cik.c

6127

WREG32(RLC_SERDES_WR_CTRL, data);

sys/dev/drm/radeon/cik.c

6159

WREG32(mc_cg_registers[i], data);

sys/dev/drm/radeon/cik.c

6176

WREG32(mc_cg_registers[i], data);

sys/dev/drm/radeon/cik.c

6186

WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/radeon/cik.c

6187

WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);

sys/dev/drm/radeon/cik.c

6192

WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6197

WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6210

WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6215

WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6220

WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6225

WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);

sys/dev/drm/radeon/cik.c

6242

WREG32(UVD_CGC_CTRL, data);

sys/dev/drm/radeon/cik.c

6251

WREG32(UVD_CGC_CTRL, data);

sys/dev/drm/radeon/cik.c

6286

WREG32(HDP_HOST_PATH_CNTL, data);

sys/dev/drm/radeon/cik.c

6302

WREG32(HDP_MEM_POWER_LS, data);

sys/dev/drm/radeon/cik.c

6390

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6404

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6417

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6430

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6530

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6535

WREG32(RLC_AUTO_PG_CTRL, data);

sys/dev/drm/radeon/cik.c

6540

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6545

WREG32(RLC_AUTO_PG_CTRL, data);

sys/dev/drm/radeon/cik.c

6599

WREG32(RLC_PG_AO_CU_MASK, tmp);

sys/dev/drm/radeon/cik.c

6604

WREG32(RLC_MAX_PG_CU, tmp);

sys/dev/drm/radeon/cik.c

6618

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6632

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6644

WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);

sys/dev/drm/radeon/cik.c

6645

WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));

sys/dev/drm/radeon/cik.c

6646

WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));

sys/dev/drm/radeon/cik.c

6647

WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);

sys/dev/drm/radeon/cik.c

6649

WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);

sys/dev/drm/radeon/cik.c

6651

WREG32(RLC_GPM_SCRATCH_DATA, 0);

sys/dev/drm/radeon/cik.c

6654

WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);

sys/dev/drm/radeon/cik.c

6656

WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);

sys/dev/drm/radeon/cik.c

6662

WREG32(RLC_PG_CNTL, data);

sys/dev/drm/radeon/cik.c

6664

WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);

sys/dev/drm/radeon/cik.c

6665

WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);

sys/dev/drm/radeon/cik.c

6670

WREG32(CP_RB_WPTR_POLL_CNTL, data);

sys/dev/drm/radeon/cik.c

6673

WREG32(RLC_PG_DELAY, data);

sys/dev/drm/radeon/cik.c

6678

WREG32(RLC_PG_DELAY_2, data);

sys/dev/drm/radeon/cik.c

6683

WREG32(RLC_AUTO_PG_CTRL, data);

sys/dev/drm/radeon/cik.c

6846

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/cik.c

6847

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/cik.c

6865

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/cik.c

6866

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/cik.c

6868

WREG32(IH_RB_RPTR, 0);

sys/dev/drm/radeon/cik.c

6869

WREG32(IH_RB_WPTR, 0);

sys/dev/drm/radeon/cik.c

6888

WREG32(CP_INT_CNTL_RING0, tmp);

sys/dev/drm/radeon/cik.c

6891

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

6893

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/cik.c

6895

WREG32(CP_ME1_PIPE0_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6896

WREG32(CP_ME1_PIPE1_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6897

WREG32(CP_ME1_PIPE2_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6898

WREG32(CP_ME1_PIPE3_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6899

WREG32(CP_ME2_PIPE0_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6900

WREG32(CP_ME2_PIPE1_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6901

WREG32(CP_ME2_PIPE2_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6902

WREG32(CP_ME2_PIPE3_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6904

WREG32(GRBM_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6906

WREG32(SRBM_INT_CNTL, 0);

sys/dev/drm/radeon/cik.c

6908

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6909

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6911

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6912

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6915

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6916

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6920

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6921

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6924

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6925

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6928

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6929

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik.c

6933

WREG32(DAC_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/cik.c

6937

WREG32(DC_HPD1_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

6939

WREG32(DC_HPD2_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

6941

WREG32(DC_HPD3_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

6943

WREG32(DC_HPD4_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

6945

WREG32(DC_HPD5_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

6947

WREG32(DC_HPD6_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

6985

WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);

sys/dev/drm/radeon/cik.c

6993

WREG32(INTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/radeon/cik.c

6995

WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);

sys/dev/drm/radeon/cik.c

7006

WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/cik.c

7007

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/cik.c

7009

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/cik.c

7012

WREG32(IH_RB_RPTR, 0);

sys/dev/drm/radeon/cik.c

7013

WREG32(IH_RB_WPTR, 0);

sys/dev/drm/radeon/cik.c

7020

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/cik.c

7244

WREG32(CP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/radeon/cik.c

7246

WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);

sys/dev/drm/radeon/cik.c

7247

WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);

sys/dev/drm/radeon/cik.c

7249

WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);

sys/dev/drm/radeon/cik.c

7250

WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);

sys/dev/drm/radeon/cik.c

7251

WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);

sys/dev/drm/radeon/cik.c

7252

WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);

sys/dev/drm/radeon/cik.c

7253

WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);

sys/dev/drm/radeon/cik.c

7254

WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);

sys/dev/drm/radeon/cik.c

7255

WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);

sys/dev/drm/radeon/cik.c

7256

WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);

sys/dev/drm/radeon/cik.c

7258

WREG32(GRBM_INT_CNTL, grbm_int_cntl);

sys/dev/drm/radeon/cik.c

7260

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);

sys/dev/drm/radeon/cik.c

7261

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);

sys/dev/drm/radeon/cik.c

7263

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);

sys/dev/drm/radeon/cik.c

7264

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);

sys/dev/drm/radeon/cik.c

7267

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);

sys/dev/drm/radeon/cik.c

7268

WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);

sys/dev/drm/radeon/cik.c

7272

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7274

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7278

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7280

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7284

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7286

WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7290

WREG32(DC_HPD1_INT_CONTROL, hpd1);

sys/dev/drm/radeon/cik.c

7291

WREG32(DC_HPD2_INT_CONTROL, hpd2);

sys/dev/drm/radeon/cik.c

7292

WREG32(DC_HPD3_INT_CONTROL, hpd3);

sys/dev/drm/radeon/cik.c

7293

WREG32(DC_HPD4_INT_CONTROL, hpd4);

sys/dev/drm/radeon/cik.c

7294

WREG32(DC_HPD5_INT_CONTROL, hpd5);

sys/dev/drm/radeon/cik.c

7295

WREG32(DC_HPD6_INT_CONTROL, hpd6);

sys/dev/drm/radeon/cik.c

7342

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7345

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7348

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7350

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/cik.c

7352

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7354

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/cik.c

7358

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7361

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7364

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7366

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/cik.c

7368

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7370

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/cik.c

7375

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7378

WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET,

sys/dev/drm/radeon/cik.c

7381

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7383

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/cik.c

7385

WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);

sys/dev/drm/radeon/cik.c

7387

WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);

sys/dev/drm/radeon/cik.c

7393

WREG32(DC_HPD1_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7398

WREG32(DC_HPD2_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7403

WREG32(DC_HPD3_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7408

WREG32(DC_HPD4_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7413

WREG32(DC_HPD5_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7418

WREG32(DC_HPD6_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7423

WREG32(DC_HPD1_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7428

WREG32(DC_HPD2_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7433

WREG32(DC_HPD3_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7438

WREG32(DC_HPD4_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7443

WREG32(DC_HPD5_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7448

WREG32(DC_HPD6_INT_CONTROL, tmp);

sys/dev/drm/radeon/cik.c

7528

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/cik.c

7915

WREG32(SRBM_INT_ACK, 0x1);

sys/dev/drm/radeon/cik.c

8114

WREG32(IH_RB_RPTR, rptr);

sys/dev/drm/radeon/cik.c

8818

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

8868

WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/cik.c

8871

WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

sys/dev/drm/radeon/cik.c

9370

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

9371

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/cik.c

9378

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/cik.c

9379

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/cik.c

9383

WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);

sys/dev/drm/radeon/cik.c

9434

WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/drm/radeon/cik_sdma.c

119

WREG32(reg, (ring->wptr << 2) & 0x3fffc);

sys/dev/drm/radeon/cik_sdma.c

264

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

sys/dev/drm/radeon/cik_sdma.c

265

WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);

sys/dev/drm/radeon/cik_sdma.c

275

WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);

sys/dev/drm/radeon/cik_sdma.c

278

WREG32(SRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/cik_sdma.c

317

WREG32(SDMA0_CNTL + reg_offset, value);

sys/dev/drm/radeon/cik_sdma.c

349

WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);

sys/dev/drm/radeon/cik_sdma.c

382

WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);

sys/dev/drm/radeon/cik_sdma.c

383

WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);

sys/dev/drm/radeon/cik_sdma.c

391

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);

sys/dev/drm/radeon/cik_sdma.c

394

WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);

sys/dev/drm/radeon/cik_sdma.c

395

WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);

sys/dev/drm/radeon/cik_sdma.c

398

WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,

sys/dev/drm/radeon/cik_sdma.c

400

WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,

sys/dev/drm/radeon/cik_sdma.c

406

WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);

sys/dev/drm/radeon/cik_sdma.c

407

WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);

sys/dev/drm/radeon/cik_sdma.c

410

WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);

sys/dev/drm/radeon/cik_sdma.c

413

WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);

sys/dev/drm/radeon/cik_sdma.c

420

WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);

sys/dev/drm/radeon/cik_sdma.c

482

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

484

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

485

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

491

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

493

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

494

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

500

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

502

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

503

WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

507

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

509

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/cik_sdma.c

510

WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);

sys/dev/drm/radeon/cik_sdma.c

513

WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cik_sdma.c

514

WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);

sys/dev/drm/radeon/cypress_dpm.c

1136

WREG32(MC_CONFIG_MCD, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1137

WREG32(MC_CG_CONFIG_MCD, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1139

WREG32(MC_CONFIG, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1140

WREG32(MC_CG_CONFIG, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1146

WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);

sys/dev/drm/radeon/cypress_dpm.c

1154

WREG32(MC_SEQ_CG, mc_seq_cg);

sys/dev/drm/radeon/cypress_dpm.c

1164

WREG32(MC_SEQ_CG, mc_seq_cg);

sys/dev/drm/radeon/cypress_dpm.c

1177

WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);

sys/dev/drm/radeon/cypress_dpm.c

1194

WREG32(MC_CONFIG_MCD, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1195

WREG32(MC_CG_CONFIG_MCD, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1197

WREG32(MC_CONFIG, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1198

WREG32(MC_CG_CONFIG, 0xf);

sys/dev/drm/radeon/cypress_dpm.c

1204

WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);

sys/dev/drm/radeon/cypress_dpm.c

1212

WREG32(MC_SEQ_CG, mc_seq_cg);

sys/dev/drm/radeon/cypress_dpm.c

1222

WREG32(MC_SEQ_CG, mc_seq_cg);

sys/dev/drm/radeon/cypress_dpm.c

126

WREG32(GRBM_GFX_INDEX, 0xC0000000);

sys/dev/drm/radeon/cypress_dpm.c

153

WREG32(GRBM_GFX_INDEX, 0xC0000000);

sys/dev/drm/radeon/cypress_dpm.c

1743

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/cypress_dpm.c

1762

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/cypress_dpm.c

1781

WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);

sys/dev/drm/radeon/cypress_dpm.c

187

WREG32(GRBM_GFX_INDEX, 0xC0000000);

sys/dev/drm/radeon/cypress_dpm.c

195

WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);

sys/dev/drm/radeon/cypress_dpm.c

208

WREG32(GRBM_GFX_INDEX, 0xC0000000);

sys/dev/drm/radeon/cypress_dpm.c

216

WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);

sys/dev/drm/radeon/cypress_dpm.c

62

WREG32(CG_BIF_REQ_AND_RSP, bif);

sys/dev/drm/radeon/cypress_dpm.c

948

WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);

sys/dev/drm/radeon/dce3_1_afmt.c

164

WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);

sys/dev/drm/radeon/dce3_1_afmt.c

165

WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);

sys/dev/drm/radeon/dce3_1_afmt.c

166

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/drm/radeon/dce3_1_afmt.c

167

WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

sys/dev/drm/radeon/dce3_1_afmt.c

171

WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);

sys/dev/drm/radeon/dce3_1_afmt.c

172

WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);

sys/dev/drm/radeon/dce3_1_afmt.c

173

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/dce3_1_afmt.c

174

WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */

sys/dev/drm/radeon/dce3_1_afmt.c

186

WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,

sys/dev/drm/radeon/dce3_1_afmt.c

218

WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

sys/dev/drm/radeon/dce3_1_afmt.c

222

WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

sys/dev/drm/radeon/dce6_afmt.c

128

WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,

sys/dev/drm/radeon/dce6_afmt.c

292

WREG32(DCCG_AUDIO_DTO_SOURCE, value);

sys/dev/drm/radeon/dce6_afmt.c

298

WREG32(DCCG_AUDIO_DTO0_PHASE, 24000);

sys/dev/drm/radeon/dce6_afmt.c

299

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/drm/radeon/dce6_afmt.c

314

WREG32(DCCG_AUDIO_DTO_SOURCE, value);

sys/dev/drm/radeon/dce6_afmt.c

329

WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);

sys/dev/drm/radeon/dce6_afmt.c

330

WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/dce6_afmt.c

332

WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);

sys/dev/drm/radeon/dce6_afmt.c

333

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/dce6_afmt.c

50

WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/radeon/dce6_afmt.c

62

WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);

sys/dev/drm/radeon/dce6_afmt.c

64

WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,

sys/dev/drm/radeon/dce6_afmt.c

66

WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);

sys/dev/drm/radeon/evergreen.c

106

WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

107

WREG32(EVERGREEN_PIF_PHY1_DATA, (v));

sys/dev/drm/radeon/evergreen.c

1169

WREG32(CG_SCRATCH1, cg_scratch);

sys/dev/drm/radeon/evergreen.c

1330

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1406

WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/evergreen.c

1408

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/evergreen.c

1410

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/evergreen.c

1666

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1691

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1768

WREG32(DC_HPDx_CONTROL(hpd), tmp);

sys/dev/drm/radeon/evergreen.c

1797

WREG32(DC_HPDx_CONTROL(hpd), 0);

sys/dev/drm/radeon/evergreen.c

1849

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/evergreen.c

1852

WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

sys/dev/drm/radeon/evergreen.c

2270

WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);

sys/dev/drm/radeon/evergreen.c

2271

WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,

sys/dev/drm/radeon/evergreen.c

2278

WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);

sys/dev/drm/radeon/evergreen.c

2279

WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,

sys/dev/drm/radeon/evergreen.c

2283

WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);

sys/dev/drm/radeon/evergreen.c

2286

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

sys/dev/drm/radeon/evergreen.c

2287

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

sys/dev/drm/radeon/evergreen.c

2361

WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);

sys/dev/drm/radeon/evergreen.c

2363

WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));

sys/dev/drm/radeon/evergreen.c

2392

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/evergreen.c

2395

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/evergreen.c

2396

WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

sys/dev/drm/radeon/evergreen.c

2403

WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2404

WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2405

WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2407

WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2408

WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2409

WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2414

WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2416

WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2417

WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2418

WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2419

WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2420

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/evergreen.c

2421

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

sys/dev/drm/radeon/evergreen.c

2422

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

sys/dev/drm/radeon/evergreen.c

2423

WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

sys/dev/drm/radeon/evergreen.c

2425

WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/evergreen.c

2427

WREG32(VM_CONTEXT1_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

2442

WREG32(VM_CONTEXT0_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

2443

WREG32(VM_CONTEXT1_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

2446

WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/evergreen.c

2448

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/evergreen.c

2449

WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

sys/dev/drm/radeon/evergreen.c

2452

WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2453

WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2454

WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2455

WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2456

WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2457

WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2458

WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2475

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/evergreen.c

2478

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/evergreen.c

2479

WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

sys/dev/drm/radeon/evergreen.c

2485

WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2486

WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2487

WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2488

WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2489

WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2490

WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2491

WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2492

WREG32(VM_CONTEXT0_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

2493

WREG32(VM_CONTEXT1_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

2626

WREG32(EVERGREEN_DP_VID_STREAM_CNTL +

sys/dev/drm/radeon/evergreen.c

2642

WREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe], fifo_ctrl);

sys/dev/drm/radeon/evergreen.c

2657

WREG32(VGA_RENDER_CONTROL, 0);

sys/dev/drm/radeon/evergreen.c

2668

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/evergreen.c

2670

WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2671

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

2677

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/evergreen.c

2679

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2680

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

2702

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/evergreen.c

2705

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2706

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

2719

WREG32(BIF_FB_EN, 0);

sys/dev/drm/radeon/evergreen.c

2722

WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);

sys/dev/drm/radeon/evergreen.c

2733

WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2738

WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2751

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

sys/dev/drm/radeon/evergreen.c

2753

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],

sys/dev/drm/radeon/evergreen.c

2755

WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],

sys/dev/drm/radeon/evergreen.c

2757

WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],

sys/dev/drm/radeon/evergreen.c

2762

WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));

sys/dev/drm/radeon/evergreen.c

2763

WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

sys/dev/drm/radeon/evergreen.c

2772

WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2777

WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2782

WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2796

WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

2798

WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);

sys/dev/drm/radeon/evergreen.c

2805

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/evergreen.c

2806

WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2807

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

2811

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/evergreen.c

2812

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/evergreen.c

2813

WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

2826

WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);

sys/dev/drm/radeon/evergreen.c

2828

WREG32(VGA_RENDER_CONTROL, save->vga_render_control);

sys/dev/drm/radeon/evergreen.c

2840

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

2841

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

2842

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

2843

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

2844

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

2846

WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

2853

WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);

sys/dev/drm/radeon/evergreen.c

2858

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/evergreen.c

2860

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/evergreen.c

2864

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/evergreen.c

2866

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/evergreen.c

2870

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/evergreen.c

2872

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/evergreen.c

2875

WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);

sys/dev/drm/radeon/evergreen.c

2883

WREG32(MC_FUS_VM_FB_OFFSET, tmp);

sys/dev/drm/radeon/evergreen.c

2887

WREG32(MC_VM_FB_LOCATION, tmp);

sys/dev/drm/radeon/evergreen.c

2888

WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

sys/dev/drm/radeon/evergreen.c

2889

WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));

sys/dev/drm/radeon/evergreen.c

2890

WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

sys/dev/drm/radeon/evergreen.c

2892

WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);

sys/dev/drm/radeon/evergreen.c

2893

WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);

sys/dev/drm/radeon/evergreen.c

2894

WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);

sys/dev/drm/radeon/evergreen.c

2896

WREG32(MC_VM_AGP_BASE, 0);

sys/dev/drm/radeon/evergreen.c

2897

WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/radeon/evergreen.c

2898

WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/radeon/evergreen.c

2956

WREG32(CP_RB_CNTL,

sys/dev/drm/radeon/evergreen.c

2963

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

2965

WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/evergreen.c

2966

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

2969

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/evergreen.c

2971

WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/evergreen.c

2973

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

2974

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/evergreen.c

2975

WREG32(CP_ME_RAM_RADDR, 0);

sys/dev/drm/radeon/evergreen.c

3000

WREG32(CP_ME_CNTL, cp_me);

sys/dev/drm/radeon/evergreen.c

3053

WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |

sys/dev/drm/radeon/evergreen.c

3061

WREG32(GRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/evergreen.c

3070

WREG32(CP_RB_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

3071

WREG32(CP_SEM_WAIT_TIMER, 0x0);

sys/dev/drm/radeon/evergreen.c

3072

WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);

sys/dev/drm/radeon/evergreen.c

3075

WREG32(CP_RB_WPTR_DELAY, 0);

sys/dev/drm/radeon/evergreen.c

3078

WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

sys/dev/drm/radeon/evergreen.c

3079

WREG32(CP_RB_RPTR_WR, 0);

sys/dev/drm/radeon/evergreen.c

3081

WREG32(CP_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/evergreen.c

3084

WREG32(CP_RB_RPTR_ADDR,

sys/dev/drm/radeon/evergreen.c

3086

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/evergreen.c

3087

WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);

sys/dev/drm/radeon/evergreen.c

3090

WREG32(SCRATCH_UMSK, 0xff);

sys/dev/drm/radeon/evergreen.c

3093

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/evergreen.c

3097

WREG32(CP_RB_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

3099

WREG32(CP_RB_BASE, ring->gpu_addr >> 8);

sys/dev/drm/radeon/evergreen.c

3100

WREG32(CP_DEBUG, (1 << 27) | (1 << 28));

sys/dev/drm/radeon/evergreen.c

3369

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

3370

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

3371

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

3372

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

3373

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/evergreen.c

3376

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

sys/dev/drm/radeon/evergreen.c

3377

WREG32(SRBM_INT_CNTL, 0x1);

sys/dev/drm/radeon/evergreen.c

3378

WREG32(SRBM_INT_ACK, 0x1);

sys/dev/drm/radeon/evergreen.c

3447

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/evergreen.c

3448

WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/evergreen.c

3468

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/evergreen.c

3469

WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/evergreen.c

3477

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

sys/dev/drm/radeon/evergreen.c

3478

WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

sys/dev/drm/radeon/evergreen.c

3480

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3481

WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3482

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3483

WREG32(DMA_TILING_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3484

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3485

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3486

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/evergreen.c

3503

WREG32(GB_BACKEND_MAP, tmp);

sys/dev/drm/radeon/evergreen.c

3505

WREG32(CGTS_SYS_TCC_DISABLE, 0);

sys/dev/drm/radeon/evergreen.c

3506

WREG32(CGTS_TCC_DISABLE, 0);

sys/dev/drm/radeon/evergreen.c

3507

WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);

sys/dev/drm/radeon/evergreen.c

3508

WREG32(CGTS_USER_TCC_DISABLE, 0);

sys/dev/drm/radeon/evergreen.c

3511

WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |

sys/dev/drm/radeon/evergreen.c

3514

WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));

sys/dev/drm/radeon/evergreen.c

3516

WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |

sys/dev/drm/radeon/evergreen.c

3523

WREG32(SX_DEBUG_1, sx_debug_1);

sys/dev/drm/radeon/evergreen.c

3529

WREG32(SMX_DC_CTL0, smx_dc_ctl0);

sys/dev/drm/radeon/evergreen.c

3532

WREG32(SMX_SAR_CTL0, 0x00010000);

sys/dev/drm/radeon/evergreen.c

3534

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |

sys/dev/drm/radeon/evergreen.c

3538

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |

sys/dev/drm/radeon/evergreen.c

3542

WREG32(VGT_NUM_INSTANCES, 1);

sys/dev/drm/radeon/evergreen.c

3543

WREG32(SPI_CONFIG_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

3544

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));

sys/dev/drm/radeon/evergreen.c

3545

WREG32(CP_PERFMON_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

3547

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |

sys/dev/drm/radeon/evergreen.c

3613

WREG32(SQ_CONFIG, sq_config);

sys/dev/drm/radeon/evergreen.c

3614

WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);

sys/dev/drm/radeon/evergreen.c

3615

WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);

sys/dev/drm/radeon/evergreen.c

3616

WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);

sys/dev/drm/radeon/evergreen.c

3617

WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);

sys/dev/drm/radeon/evergreen.c

3618

WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);

sys/dev/drm/radeon/evergreen.c

3619

WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);

sys/dev/drm/radeon/evergreen.c

3620

WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);

sys/dev/drm/radeon/evergreen.c

3621

WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);

sys/dev/drm/radeon/evergreen.c

3622

WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);

sys/dev/drm/radeon/evergreen.c

3623

WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);

sys/dev/drm/radeon/evergreen.c

3625

WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |

sys/dev/drm/radeon/evergreen.c

3641

WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);

sys/dev/drm/radeon/evergreen.c

3643

WREG32(VGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/radeon/evergreen.c

3644

WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);

sys/dev/drm/radeon/evergreen.c

3645

WREG32(PA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/radeon/evergreen.c

3647

WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);

sys/dev/drm/radeon/evergreen.c

3648

WREG32(VGT_OUT_DEALLOC_CNTL, 16);

sys/dev/drm/radeon/evergreen.c

3650

WREG32(CB_PERF_CTR0_SEL_0, 0);

sys/dev/drm/radeon/evergreen.c

3651

WREG32(CB_PERF_CTR0_SEL_1, 0);

sys/dev/drm/radeon/evergreen.c

3652

WREG32(CB_PERF_CTR1_SEL_0, 0);

sys/dev/drm/radeon/evergreen.c

3653

WREG32(CB_PERF_CTR1_SEL_1, 0);

sys/dev/drm/radeon/evergreen.c

3654

WREG32(CB_PERF_CTR2_SEL_0, 0);

sys/dev/drm/radeon/evergreen.c

3655

WREG32(CB_PERF_CTR2_SEL_1, 0);

sys/dev/drm/radeon/evergreen.c

3656

WREG32(CB_PERF_CTR3_SEL_0, 0);

sys/dev/drm/radeon/evergreen.c

3657

WREG32(CB_PERF_CTR3_SEL_1, 0);

sys/dev/drm/radeon/evergreen.c

3660

WREG32(CB_COLOR0_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3661

WREG32(CB_COLOR1_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3662

WREG32(CB_COLOR2_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3663

WREG32(CB_COLOR3_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3664

WREG32(CB_COLOR4_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3665

WREG32(CB_COLOR5_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3666

WREG32(CB_COLOR6_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3667

WREG32(CB_COLOR7_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3668

WREG32(CB_COLOR8_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3669

WREG32(CB_COLOR9_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3670

WREG32(CB_COLOR10_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3671

WREG32(CB_COLOR11_BASE, 0);

sys/dev/drm/radeon/evergreen.c

3675

WREG32(i, 0);

sys/dev/drm/radeon/evergreen.c

3677

WREG32(i, 0);

sys/dev/drm/radeon/evergreen.c

3681

WREG32(HDP_MISC_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

3684

WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);

sys/dev/drm/radeon/evergreen.c

3686

WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));

sys/dev/drm/radeon/evergreen.c

3891

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

sys/dev/drm/radeon/evergreen.c

3897

WREG32(DMA_RB_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

3958

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/evergreen.c

3964

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/evergreen.c

3972

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/evergreen.c

3978

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/evergreen.c

4001

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

sys/dev/drm/radeon/evergreen.c

4006

WREG32(DMA_RB_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

4360

WREG32(RLC_CNTL, mask);

sys/dev/drm/radeon/evergreen.c

4373

WREG32(RLC_HB_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

4384

WREG32(TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK, always_on_bitmap);

sys/dev/drm/radeon/evergreen.c

4385

WREG32(TN_RLC_LB_PARAMS, 0x00601004);

sys/dev/drm/radeon/evergreen.c

4386

WREG32(TN_RLC_LB_INIT_SIMD_MASK, 0xffffffff);

sys/dev/drm/radeon/evergreen.c

4387

WREG32(TN_RLC_LB_CNTR_INIT, 0x00000000);

sys/dev/drm/radeon/evergreen.c

4388

WREG32(TN_RLC_LB_CNTR_MAX, 0x00002000);

sys/dev/drm/radeon/evergreen.c

4391

WREG32(RLC_HB_WPTR_LSB_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

4392

WREG32(RLC_HB_WPTR_MSB_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

4394

WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);

sys/dev/drm/radeon/evergreen.c

4395

WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);

sys/dev/drm/radeon/evergreen.c

4397

WREG32(RLC_HB_BASE, 0);

sys/dev/drm/radeon/evergreen.c

4398

WREG32(RLC_HB_RPTR, 0);

sys/dev/drm/radeon/evergreen.c

4399

WREG32(RLC_HB_WPTR, 0);

sys/dev/drm/radeon/evergreen.c

4400

WREG32(RLC_HB_WPTR_LSB_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

4401

WREG32(RLC_HB_WPTR_MSB_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

4403

WREG32(RLC_MC_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

4404

WREG32(RLC_UCODE_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

4409

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/evergreen.c

4410

WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/evergreen.c

4414

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/evergreen.c

4415

WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/evergreen.c

4419

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/evergreen.c

4420

WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/evergreen.c

4423

WREG32(RLC_UCODE_ADDR, 0);

sys/dev/drm/radeon/evergreen.c

4451

WREG32(CAYMAN_DMA1_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

4453

WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

sys/dev/drm/radeon/evergreen.c

4455

WREG32(DMA_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

4456

WREG32(GRBM_INT_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

4457

WREG32(SRBM_INT_CNTL, 0);

sys/dev/drm/radeon/evergreen.c

4459

WREG32(INT_MASK + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

4461

WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);

sys/dev/drm/radeon/evergreen.c

4465

WREG32(DACA_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/evergreen.c

4466

WREG32(DACB_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/evergreen.c

4548

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/drm/radeon/evergreen.c

4550

WREG32(DMA_CNTL, dma_cntl);

sys/dev/drm/radeon/evergreen.c

4553

WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);

sys/dev/drm/radeon/evergreen.c

4555

WREG32(GRBM_INT_CNTL, grbm_int_cntl);

sys/dev/drm/radeon/evergreen.c

4566

WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);

sys/dev/drm/radeon/evergreen.c

4576

WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int);

sys/dev/drm/radeon/evergreen.c

4578

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/radeon/evergreen.c

4612

WREG32(GRPH_INT_STATUS + crtc_offsets[j],

sys/dev/drm/radeon/evergreen.c

4618

WREG32(VBLANK_STATUS + crtc_offsets[j],

sys/dev/drm/radeon/evergreen.c

4621

WREG32(VLINE_STATUS + crtc_offsets[j],

sys/dev/drm/radeon/evergreen.c

4678

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/evergreen.c

4818

WREG32(SRBM_INT_ACK, 0x1);

sys/dev/drm/radeon/evergreen.c

4893

WREG32(IH_RB_RPTR, rptr);

sys/dev/drm/radeon/evergreen.c

51

WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

62

WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

63

WREG32(EVERGREEN_CG_IND_DATA, (v));

sys/dev/drm/radeon/evergreen.c

73

WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

84

WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen.c

85

WREG32(EVERGREEN_PIF_PHY0_DATA, (v));

sys/dev/drm/radeon/evergreen.c

95

WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff));

sys/dev/drm/radeon/evergreen_hdmi.c

228

WREG32(AFMT_AVI_INFO0 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

230

WREG32(AFMT_AVI_INFO1 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

232

WREG32(AFMT_AVI_INFO2 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

234

WREG32(AFMT_AVI_INFO3 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

269

WREG32(DCCG_AUDIO_DTO0_CNTL, value);

sys/dev/drm/radeon/evergreen_hdmi.c

277

WREG32(DCCG_AUDIO_DTO_SOURCE, value);

sys/dev/drm/radeon/evergreen_hdmi.c

283

WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);

sys/dev/drm/radeon/evergreen_hdmi.c

284

WREG32(DCCG_AUDIO_DTO0_MODULE, clock);

sys/dev/drm/radeon/evergreen_hdmi.c

296

WREG32(DCCG_AUDIO_DTO1_CNTL, value);

sys/dev/drm/radeon/evergreen_hdmi.c

305

WREG32(DCCG_AUDIO_DTO_SOURCE, value);

sys/dev/drm/radeon/evergreen_hdmi.c

321

WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);

sys/dev/drm/radeon/evergreen_hdmi.c

322

WREG32(DCCG_AUDIO_DTO1_MODULE, clock);

sys/dev/drm/radeon/evergreen_hdmi.c

331

WREG32(HDMI_VBI_PACKET_CONTROL + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

372

WREG32(HDMI_CONTROL + offset, val);

sys/dev/drm/radeon/evergreen_hdmi.c

381

WREG32(AFMT_INFOFRAME_CONTROL0 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

384

WREG32(AFMT_60958_0 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

387

WREG32(AFMT_60958_1 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

390

WREG32(AFMT_60958_2 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

398

WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

401

WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

438

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,

sys/dev/drm/radeon/evergreen_hdmi.c

446

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,

sys/dev/drm/radeon/evergreen_hdmi.c

455

WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);

sys/dev/drm/radeon/evergreen_hdmi.c

486

WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,

sys/dev/drm/radeon/evergreen_hdmi.c

499

WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);

sys/dev/drm/radeon/evergreen_hdmi.c

502

WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,

sys/dev/drm/radeon/evergreen_hdmi.c

508

WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);

sys/dev/drm/radeon/evergreen_hdmi.c

67

WREG32(AZ_HOT_PLUG_CONTROL, tmp);

sys/dev/drm/radeon/evergreen_hdmi.c

85

WREG32(HDMI_ACR_PACKET_CONTROL + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

88

WREG32(HDMI_ACR_PACKET_CONTROL + offset,

sys/dev/drm/radeon/evergreen_hdmi.c

92

WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));

sys/dev/drm/radeon/evergreen_hdmi.c

93

WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);

sys/dev/drm/radeon/evergreen_hdmi.c

95

WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));

sys/dev/drm/radeon/evergreen_hdmi.c

96

WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);

sys/dev/drm/radeon/evergreen_hdmi.c

98

WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));

sys/dev/drm/radeon/evergreen_hdmi.c

99

WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);

sys/dev/drm/radeon/kv_dpm.c

318

WREG32(config_regs->offset << 2, data);

sys/dev/drm/radeon/kv_smc.c

165

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/kv_smc.c

178

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/kv_smc.c

211

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/kv_smc.c

35

WREG32(SMC_MESSAGE_0, id & SMC_MSG_MASK);

sys/dev/drm/radeon/kv_smc.c

70

WREG32(SMC_MSG_ARG_0, parameter);

sys/dev/drm/radeon/kv_smc.c

83

WREG32(SMC_IND_INDEX_0, smc_address);

sys/dev/drm/radeon/ni.c

1016

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/ni.c

1017

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/ni.c

1018

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/ni.c

1019

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/ni.c

1020

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/ni.c

1023

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

sys/dev/drm/radeon/ni.c

1024

WREG32(SRBM_INT_CNTL, 0x1);

sys/dev/drm/radeon/ni.c

1025

WREG32(SRBM_INT_ACK, 0x1);

sys/dev/drm/radeon/ni.c

1105

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/ni.c

1106

WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/ni.c

1125

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/ni.c

1126

WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));

sys/dev/drm/radeon/ni.c

1134

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

sys/dev/drm/radeon/ni.c

1135

WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);

sys/dev/drm/radeon/ni.c

1137

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1138

WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1140

WREG32(DMIF_ADDR_CALC, gb_addr_config);

sys/dev/drm/radeon/ni.c

1141

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1142

WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/ni.c

1143

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/ni.c

1144

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1145

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1146

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/ni.c

1165

WREG32(GB_BACKEND_MAP, tmp);

sys/dev/drm/radeon/ni.c

1170

WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);

sys/dev/drm/radeon/ni.c

1171

WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);

sys/dev/drm/radeon/ni.c

1172

WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);

sys/dev/drm/radeon/ni.c

1173

WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);

sys/dev/drm/radeon/ni.c

1178

WREG32(CGTS_SM_CTRL_REG, OVERRIDE);

sys/dev/drm/radeon/ni.c

1179

WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);

sys/dev/drm/radeon/ni.c

1182

WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));

sys/dev/drm/radeon/ni.c

1186

WREG32(SX_DEBUG_1, sx_debug_1);

sys/dev/drm/radeon/ni.c

1191

WREG32(SMX_DC_CTL0, smx_dc_ctl0);

sys/dev/drm/radeon/ni.c

1193

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);

sys/dev/drm/radeon/ni.c

1196

WREG32(VGT_OFFCHIP_LDS_BASE, 0);

sys/dev/drm/radeon/ni.c

1197

WREG32(SQ_LSTMP_RING_BASE, 0);

sys/dev/drm/radeon/ni.c

1198

WREG32(SQ_HSTMP_RING_BASE, 0);

sys/dev/drm/radeon/ni.c

1199

WREG32(SQ_ESTMP_RING_BASE, 0);

sys/dev/drm/radeon/ni.c

1200

WREG32(SQ_GSTMP_RING_BASE, 0);

sys/dev/drm/radeon/ni.c

1201

WREG32(SQ_VSTMP_RING_BASE, 0);

sys/dev/drm/radeon/ni.c

1202

WREG32(SQ_PSTMP_RING_BASE, 0);

sys/dev/drm/radeon/ni.c

1204

WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);

sys/dev/drm/radeon/ni.c

1206

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |

sys/dev/drm/radeon/ni.c

1210

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |

sys/dev/drm/radeon/ni.c

1215

WREG32(VGT_NUM_INSTANCES, 1);

sys/dev/drm/radeon/ni.c

1217

WREG32(CP_PERFMON_CNTL, 0);

sys/dev/drm/radeon/ni.c

1219

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |

sys/dev/drm/radeon/ni.c

1224

WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));

sys/dev/drm/radeon/ni.c

1225

WREG32(SQ_CONFIG, (VC_ENABLE |

sys/dev/drm/radeon/ni.c

1230

WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);

sys/dev/drm/radeon/ni.c

1232

WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |

sys/dev/drm/radeon/ni.c

1235

WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |

sys/dev/drm/radeon/ni.c

1238

WREG32(VGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/radeon/ni.c

1239

WREG32(PA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/radeon/ni.c

1241

WREG32(CB_PERF_CTR0_SEL_0, 0);

sys/dev/drm/radeon/ni.c

1242

WREG32(CB_PERF_CTR0_SEL_1, 0);

sys/dev/drm/radeon/ni.c

1243

WREG32(CB_PERF_CTR1_SEL_0, 0);

sys/dev/drm/radeon/ni.c

1244

WREG32(CB_PERF_CTR1_SEL_1, 0);

sys/dev/drm/radeon/ni.c

1245

WREG32(CB_PERF_CTR2_SEL_0, 0);

sys/dev/drm/radeon/ni.c

1246

WREG32(CB_PERF_CTR2_SEL_1, 0);

sys/dev/drm/radeon/ni.c

1247

WREG32(CB_PERF_CTR3_SEL_0, 0);

sys/dev/drm/radeon/ni.c

1248

WREG32(CB_PERF_CTR3_SEL_1, 0);

sys/dev/drm/radeon/ni.c

1252

WREG32(HDP_MISC_CNTL, tmp);

sys/dev/drm/radeon/ni.c

1255

WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);

sys/dev/drm/radeon/ni.c

1257

WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));

sys/dev/drm/radeon/ni.c

1278

WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);

sys/dev/drm/radeon/ni.c

1281

WREG32(VM_INVALIDATE_REQUEST, 1);

sys/dev/drm/radeon/ni.c

1296

WREG32(MC_VM_MX_L1_TLB_CNTL,

sys/dev/drm/radeon/ni.c

1304

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |

sys/dev/drm/radeon/ni.c

1310

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/drm/radeon/ni.c

1311

WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

sys/dev/drm/radeon/ni.c

1315

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/ni.c

1316

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

sys/dev/drm/radeon/ni.c

1317

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

sys/dev/drm/radeon/ni.c

1318

WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/ni.c

1320

WREG32(VM_CONTEXT0_CNTL2, 0);

sys/dev/drm/radeon/ni.c

1321

WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

sys/dev/drm/radeon/ni.c

1324

WREG32(0x15D4, 0);

sys/dev/drm/radeon/ni.c

1325

WREG32(0x15D8, 0);

sys/dev/drm/radeon/ni.c

1326

WREG32(0x15DC, 0);

sys/dev/drm/radeon/ni.c

1334

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);

sys/dev/drm/radeon/ni.c

1335

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),

sys/dev/drm/radeon/ni.c

1337

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

sys/dev/drm/radeon/ni.c

1342

WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/ni.c

1344

WREG32(VM_CONTEXT1_CNTL2, 4);

sys/dev/drm/radeon/ni.c

1345

WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

sys/dev/drm/radeon/ni.c

1378

WREG32(VM_CONTEXT0_CNTL, 0);

sys/dev/drm/radeon/ni.c

1379

WREG32(VM_CONTEXT1_CNTL, 0);

sys/dev/drm/radeon/ni.c

1381

WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/ni.c

1385

WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |

sys/dev/drm/radeon/ni.c

1389

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/ni.c

1390

WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

sys/dev/drm/radeon/ni.c

1405

WREG32(SRBM_GFX_CNTL, RINGID(ring));

sys/dev/drm/radeon/ni.c

1406

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/drm/radeon/ni.c

1474

WREG32(CP_ME_CNTL, 0);

sys/dev/drm/radeon/ni.c

1478

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

sys/dev/drm/radeon/ni.c

1479

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/ni.c

1522

WREG32(CP_RB0_WPTR, ring->wptr);

sys/dev/drm/radeon/ni.c

1525

WREG32(CP_RB1_WPTR, ring->wptr);

sys/dev/drm/radeon/ni.c

1528

WREG32(CP_RB2_WPTR, ring->wptr);

sys/dev/drm/radeon/ni.c

1544

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/ni.c

1546

WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/ni.c

1547

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/ni.c

1550

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/ni.c

1552

WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/ni.c

1554

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/ni.c

1555

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/ni.c

1556

WREG32(CP_ME_RAM_RADDR, 0);

sys/dev/drm/radeon/ni.c

1675

WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |

sys/dev/drm/radeon/ni.c

1683

WREG32(GRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/ni.c

1686

WREG32(CP_SEM_WAIT_TIMER, 0x0);

sys/dev/drm/radeon/ni.c

1687

WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);

sys/dev/drm/radeon/ni.c

1690

WREG32(CP_RB_WPTR_DELAY, 0);

sys/dev/drm/radeon/ni.c

1692

WREG32(CP_DEBUG, (1 << 27));

sys/dev/drm/radeon/ni.c

1695

WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);

sys/dev/drm/radeon/ni.c

1696

WREG32(SCRATCH_UMSK, 0xff);

sys/dev/drm/radeon/ni.c

1709

WREG32(cp_rb_cntl[i], rb_cntl);

sys/dev/drm/radeon/ni.c

1713

WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);

sys/dev/drm/radeon/ni.c

1714

WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);

sys/dev/drm/radeon/ni.c

1720

WREG32(cp_rb_base[i], ring->gpu_addr >> 8);

sys/dev/drm/radeon/ni.c

1729

WREG32(cp_rb_rptr[i], 0);

sys/dev/drm/radeon/ni.c

1730

WREG32(cp_rb_wptr[i], ring->wptr);

sys/dev/drm/radeon/ni.c

1856

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

sys/dev/drm/radeon/ni.c

1862

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/ni.c

1869

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/ni.c

1933

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/ni.c

1939

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/ni.c

1947

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/ni.c

1953

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/ni.c

46

WREG32(TN_SMC_IND_INDEX_0, (reg));

sys/dev/drm/radeon/ni.c

55

WREG32(TN_SMC_IND_INDEX_0, (reg));

sys/dev/drm/radeon/ni.c

56

WREG32(TN_SMC_IND_DATA_0, (v));

sys/dev/drm/radeon/ni.c

655

WREG32(MC_SHARED_BLACKOUT_CNTL, 1);

sys/dev/drm/radeon/ni.c

659

WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/radeon/ni.c

660

WREG32(MC_SEQ_SUP_CNTL, 0x00000010);

sys/dev/drm/radeon/ni.c

664

WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);

sys/dev/drm/radeon/ni.c

665

WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);

sys/dev/drm/radeon/ni.c

670

WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/ni.c

673

WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/radeon/ni.c

674

WREG32(MC_SEQ_SUP_CNTL, 0x00000004);

sys/dev/drm/radeon/ni.c

675

WREG32(MC_SEQ_SUP_CNTL, 0x00000001);

sys/dev/drm/radeon/ni.c

685

WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);

sys/dev/drm/radeon/ni_dma.c

109

WREG32(reg, (ring->wptr << 2) & 0x3fffc);

sys/dev/drm/radeon/ni_dma.c

166

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);

sys/dev/drm/radeon/ni_dma.c

171

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl);

sys/dev/drm/radeon/ni_dma.c

204

WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);

sys/dev/drm/radeon/ni_dma.c

205

WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);

sys/dev/drm/radeon/ni_dma.c

213

WREG32(DMA_RB_CNTL + reg_offset, rb_cntl);

sys/dev/drm/radeon/ni_dma.c

216

WREG32(DMA_RB_RPTR + reg_offset, 0);

sys/dev/drm/radeon/ni_dma.c

217

WREG32(DMA_RB_WPTR + reg_offset, 0);

sys/dev/drm/radeon/ni_dma.c

220

WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset,

sys/dev/drm/radeon/ni_dma.c

222

WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset,

sys/dev/drm/radeon/ni_dma.c

228

WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);

sys/dev/drm/radeon/ni_dma.c

235

WREG32(DMA_IB_CNTL + reg_offset, ib_cntl);

sys/dev/drm/radeon/ni_dma.c

239

WREG32(DMA_CNTL + reg_offset, dma_cntl);

sys/dev/drm/radeon/ni_dma.c

242

WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2);

sys/dev/drm/radeon/ni_dma.c

244

WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE);

sys/dev/drm/radeon/ni_dpm.c

1039

WREG32(SMC_SCRATCH0, parameter);

sys/dev/drm/radeon/ni_dpm.c

1539

WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);

sys/dev/drm/radeon/ni_dpm.c

1540

WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);

sys/dev/drm/radeon/ni_dpm.c

1544

WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);

sys/dev/drm/radeon/ni_dpm.c

1545

WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);

sys/dev/drm/radeon/ni_dpm.c

1549

WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);

sys/dev/drm/radeon/ni_dpm.c

1550

WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);

sys/dev/drm/radeon/ni_dpm.c

1554

WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);

sys/dev/drm/radeon/ni_dpm.c

1555

WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);

sys/dev/drm/radeon/ni_dpm.c

1563

WREG32(MC_CG_CONFIG, mc_cg_config);

sys/dev/drm/radeon/ni_dpm.c

2883

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

sys/dev/drm/radeon/ni_dpm.c

2884

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

sys/dev/drm/radeon/ni_dpm.c

2885

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

sys/dev/drm/radeon/ni_dpm.c

2886

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

sys/dev/drm/radeon/ni_dpm.c

2887

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

sys/dev/drm/radeon/ni_dpm.c

2888

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

sys/dev/drm/radeon/ni_dpm.c

2889

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

sys/dev/drm/radeon/ni_dpm.c

2890

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

sys/dev/drm/radeon/ni_dpm.c

2891

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

sys/dev/drm/radeon/ni_dpm.c

2892

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

sys/dev/drm/radeon/ni_dpm.c

2893

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

sys/dev/drm/radeon/ni_dpm.c

2894

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

sys/dev/drm/radeon/ni_dpm.c

2895

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

sys/dev/drm/radeon/ni_dpm.c

3157

WREG32(CG_CAC_CTRL, reg);

sys/dev/drm/radeon/ni_dpm.c

3360

WREG32(SQ_CAC_THRESHOLD, reg);

sys/dev/drm/radeon/ni_dpm.c

3367

WREG32(MC_CG_CONFIG, reg);

sys/dev/drm/radeon/ni_dpm.c

3372

WREG32(MC_CG_DATAPORT, reg);

sys/dev/drm/radeon/ni_dpm.c

3472

WREG32(CG_BIF_REQ_AND_RSP, bif);

sys/dev/drm/radeon/ni_dpm.c

3487

WREG32(CG_BIF_REQ_AND_RSP, bif);

sys/dev/drm/radeon/r100.c

1080

WREG32(RADEON_CP_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/r100.c

1110

WREG32(RADEON_CP_ME_RAM_ADDR, 0);

sys/dev/drm/radeon/r100.c

1112

WREG32(RADEON_CP_ME_RAM_DATAH,

sys/dev/drm/radeon/r100.c

1114

WREG32(RADEON_CP_ME_RAM_DATAL,

sys/dev/drm/radeon/r100.c

1178

WREG32(0x718, pre_write_timer | (pre_write_limit << 28));

sys/dev/drm/radeon/r100.c

1185

WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);

sys/dev/drm/radeon/r100.c

1189

WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);

sys/dev/drm/radeon/r100.c

1191

WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);

sys/dev/drm/radeon/r100.c

1192

WREG32(RADEON_CP_RB_RPTR_WR, 0);

sys/dev/drm/radeon/r100.c

1194

WREG32(RADEON_CP_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/r100.c

1197

WREG32(R_00070C_CP_RB_RPTR_ADDR,

sys/dev/drm/radeon/r100.c

1199

WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);

sys/dev/drm/radeon/r100.c

1202

WREG32(R_000770_SCRATCH_UMSK, 0xff);

sys/dev/drm/radeon/r100.c

1205

WREG32(R_000770_SCRATCH_UMSK, 0);

sys/dev/drm/radeon/r100.c

1208

WREG32(RADEON_CP_RB_CNTL, tmp);

sys/dev/drm/radeon/r100.c

1211

WREG32(RADEON_CP_CSQ_MODE,

sys/dev/drm/radeon/r100.c

1214

WREG32(RADEON_CP_RB_WPTR_DELAY, 0);

sys/dev/drm/radeon/r100.c

1215

WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);

sys/dev/drm/radeon/r100.c

1216

WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);

sys/dev/drm/radeon/r100.c

1258

WREG32(RADEON_CP_CSQ_MODE, 0);

sys/dev/drm/radeon/r100.c

1259

WREG32(RADEON_CP_CSQ_CNTL, 0);

sys/dev/drm/radeon/r100.c

1260

WREG32(R_000770_SCRATCH_UMSK, 0);

sys/dev/drm/radeon/r100.c

164

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r100.c

176

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r100.c

2546

WREG32(RADEON_BUS_CNTL, tmp);

sys/dev/drm/radeon/r100.c

2555

WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);

sys/dev/drm/radeon/r100.c

2557

WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);

sys/dev/drm/radeon/r100.c

2559

WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);

sys/dev/drm/radeon/r100.c

2580

WREG32(RADEON_CP_CSQ_CNTL, 0);

sys/dev/drm/radeon/r100.c

2582

WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);

sys/dev/drm/radeon/r100.c

2583

WREG32(RADEON_CP_RB_RPTR_WR, 0);

sys/dev/drm/radeon/r100.c

2584

WREG32(RADEON_CP_RB_WPTR, 0);

sys/dev/drm/radeon/r100.c

2585

WREG32(RADEON_CP_RB_CNTL, tmp);

sys/dev/drm/radeon/r100.c

2590

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |

sys/dev/drm/radeon/r100.c

2596

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r100.c

2601

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));

sys/dev/drm/radeon/r100.c

2604

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r100.c

2629

WREG32(RADEON_OV0_SCALE_CNTL, 0);

sys/dev/drm/radeon/r100.c

2630

WREG32(RADEON_SUBPIC_CNTL, 0);

sys/dev/drm/radeon/r100.c

2631

WREG32(RADEON_VIPH_CONTROL, 0);

sys/dev/drm/radeon/r100.c

2632

WREG32(RADEON_I2C_CNTL_1, 0);

sys/dev/drm/radeon/r100.c

2633

WREG32(RADEON_DVI_I2C_CNTL_1, 0);

sys/dev/drm/radeon/r100.c

2634

WREG32(RADEON_CAP0_TRIG_CNTL, 0);

sys/dev/drm/radeon/r100.c

2635

WREG32(RADEON_CAP1_TRIG_CNTL, 0);

sys/dev/drm/radeon/r100.c

2694

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/r100.c

2695

WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);

sys/dev/drm/radeon/r100.c

2696

WREG32(RADEON_DAC_CNTL2, dac2_cntl);

sys/dev/drm/radeon/r100.c

2799

WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);

sys/dev/drm/radeon/r100.c

2808

WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);

sys/dev/drm/radeon/r100.c

2834

WREG32(RADEON_CONFIG_CNTL, temp);

sys/dev/drm/radeon/r100.c

2884

WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);

sys/dev/drm/radeon/r100.c

2886

WREG32(RADEON_CLOCK_CNTL_INDEX, save);

sys/dev/drm/radeon/r100.c

2911

WREG32(RADEON_CLOCK_CNTL_DATA, v);

sys/dev/drm/radeon/r100.c

2945

WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);

sys/dev/drm/radeon/r100.c

2947

WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);

sys/dev/drm/radeon/r100.c

3013

WREG32(RADEON_CP_CSQ_ADDR, i << 2);

sys/dev/drm/radeon/r100.c

3019

WREG32(RADEON_CP_CSQ_ADDR, i << 2);

sys/dev/drm/radeon/r100.c

3025

WREG32(RADEON_CP_CSQ_ADDR, i << 2);

sys/dev/drm/radeon/r100.c

3145

WREG32(RADEON_SURFACE0_INFO + surf_index, flags);

sys/dev/drm/radeon/r100.c

3146

WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);

sys/dev/drm/radeon/r100.c

3147

WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);

sys/dev/drm/radeon/r100.c

3154

WREG32(RADEON_SURFACE0_INFO + surf_index, 0);

sys/dev/drm/radeon/r100.c

3265

WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);

sys/dev/drm/radeon/r100.c

3371

WREG32(R300_MC_IND_INDEX, temp);

sys/dev/drm/radeon/r100.c

3531

WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |

sys/dev/drm/radeon/r100.c

3541

WREG32(RS400_DISP1_REQ_CNTL1, (temp |

sys/dev/drm/radeon/r100.c

3547

WREG32(RS400_DMIF_MEM_CNTL1, (temp |

sys/dev/drm/radeon/r100.c

359

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/r100.c

3623

WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |

sys/dev/drm/radeon/r100.c

3633

WREG32(RS400_DISP2_REQ_CNTL1, (temp |

sys/dev/drm/radeon/r100.c

3639

WREG32(RS400_DISP2_REQ_CNTL2, (temp |

sys/dev/drm/radeon/r100.c

3643

WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);

sys/dev/drm/radeon/r100.c

3644

WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);

sys/dev/drm/radeon/r100.c

3645

WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);

sys/dev/drm/radeon/r100.c

3646

WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);

sys/dev/drm/radeon/r100.c

3673

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/radeon/r100.c

368

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/r100.c

3729

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/radeon/r100.c

3787

WREG32(R_000740_CP_CSQ_CNTL, 0);

sys/dev/drm/radeon/r100.c

3802

WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));

sys/dev/drm/radeon/r100.c

3803

WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |

sys/dev/drm/radeon/r100.c

3805

WREG32(R_000050_CRTC_GEN_CNTL,

sys/dev/drm/radeon/r100.c

3808

WREG32(R_000420_OV0_SCALE_CNTL,

sys/dev/drm/radeon/r100.c

3810

WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);

sys/dev/drm/radeon/r100.c

3812

WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |

sys/dev/drm/radeon/r100.c

3814

WREG32(R_0003F8_CRTC2_GEN_CNTL,

sys/dev/drm/radeon/r100.c

3818

WREG32(R_000360_CUR2_OFFSET,

sys/dev/drm/radeon/r100.c

3826

WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);

sys/dev/drm/radeon/r100.c

3828

WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);

sys/dev/drm/radeon/r100.c

3832

WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);

sys/dev/drm/radeon/r100.c

3833

WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);

sys/dev/drm/radeon/r100.c

3835

WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);

sys/dev/drm/radeon/r100.c

3863

WREG32(R_00014C_MC_AGP_LOCATION,

sys/dev/drm/radeon/r100.c

3866

WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));

sys/dev/drm/radeon/r100.c

3868

WREG32(R_00015C_AGP_BASE_2,

sys/dev/drm/radeon/r100.c

3871

WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);

sys/dev/drm/radeon/r100.c

3872

WREG32(R_000170_AGP_BASE, 0);

sys/dev/drm/radeon/r100.c

3874

WREG32(R_00015C_AGP_BASE_2, 0);

sys/dev/drm/radeon/r100.c

3880

WREG32(R_000148_MC_FB_LOCATION,

sys/dev/drm/radeon/r100.c

4028

WREG32(RADEON_CP_CSQ_CNTL, 0);

sys/dev/drm/radeon/r100.c

4032

WREG32(RADEON_CP_RB_CNTL, 0);

sys/dev/drm/radeon/r100.c

4036

WREG32(RADEON_SCRATCH_UMSK, 0);

sys/dev/drm/radeon/r100.c

457

WREG32(RADEON_CRTC2_GEN_CNTL, tmp);

sys/dev/drm/radeon/r100.c

461

WREG32(RADEON_CRTC_GEN_CNTL, tmp);

sys/dev/drm/radeon/r100.c

488

WREG32(RADEON_CRTC2_GEN_CNTL, tmp);

sys/dev/drm/radeon/r100.c

492

WREG32(RADEON_CRTC_GEN_CNTL, tmp);

sys/dev/drm/radeon/r100.c

564

WREG32(RADEON_FP_GEN_CNTL, tmp);

sys/dev/drm/radeon/r100.c

572

WREG32(RADEON_FP2_GEN_CNTL, tmp);

sys/dev/drm/radeon/r100.c

660

WREG32(RADEON_AIC_CNTL, tmp);

sys/dev/drm/radeon/r100.c

662

WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);

sys/dev/drm/radeon/r100.c

663

WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);

sys/dev/drm/radeon/r100.c

665

WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);

sys/dev/drm/radeon/r100.c

667

WREG32(RADEON_AIC_CNTL, tmp);

sys/dev/drm/radeon/r100.c

682

WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);

sys/dev/drm/radeon/r100.c

683

WREG32(RADEON_AIC_LO_ADDR, 0);

sys/dev/drm/radeon/r100.c

684

WREG32(RADEON_AIC_HI_ADDR, 0);

sys/dev/drm/radeon/r100.c

712

WREG32(R_000040_GEN_INT_CNTL, 0);

sys/dev/drm/radeon/r100.c

732

WREG32(RADEON_GEN_INT_CNTL, tmp);

sys/dev/drm/radeon/r100.c

744

WREG32(R_000040_GEN_INT_CNTL, 0);

sys/dev/drm/radeon/r100.c

748

WREG32(R_000044_GEN_INT_STATUS, tmp);

sys/dev/drm/radeon/r100.c

759

WREG32(RADEON_GEN_INT_STATUS, irqs);

sys/dev/drm/radeon/r100.c

817

WREG32(RADEON_AIC_CNTL, msi_rearm);

sys/dev/drm/radeon/r100.c

818

WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);

sys/dev/drm/radeon/r100.c

821

WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);

sys/dev/drm/radeon/r300.c

1333

WREG32(R_00014C_MC_AGP_LOCATION,

sys/dev/drm/radeon/r300.c

1336

WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));

sys/dev/drm/radeon/r300.c

1337

WREG32(R_00015C_AGP_BASE_2,

sys/dev/drm/radeon/r300.c

1340

WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);

sys/dev/drm/radeon/r300.c

1341

WREG32(R_000170_AGP_BASE, 0);

sys/dev/drm/radeon/r300.c

1342

WREG32(R_00015C_AGP_BASE_2, 0);

sys/dev/drm/radeon/r300.c

1348

WREG32(R_000148_MC_FB_LOCATION,

sys/dev/drm/radeon/r300.c

383

WREG32(R300_GB_TILE_CONFIG, gb_tile_config);

sys/dev/drm/radeon/r300.c

390

WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);

sys/dev/drm/radeon/r300.c

392

WREG32(R300_RB2D_DSTCACHE_MODE,

sys/dev/drm/radeon/r300.c

420

WREG32(RADEON_CP_CSQ_CNTL, 0);

sys/dev/drm/radeon/r300.c

422

WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);

sys/dev/drm/radeon/r300.c

423

WREG32(RADEON_CP_RB_RPTR_WR, 0);

sys/dev/drm/radeon/r300.c

424

WREG32(RADEON_CP_RB_WPTR, 0);

sys/dev/drm/radeon/r300.c

425

WREG32(RADEON_CP_RB_CNTL, tmp);

sys/dev/drm/radeon/r300.c

430

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |

sys/dev/drm/radeon/r300.c

434

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r300.c

443

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));

sys/dev/drm/radeon/r300.c

446

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r300.c

59

WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));

sys/dev/drm/radeon/r300.c

68

WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));

sys/dev/drm/radeon/r300.c

69

WREG32(RADEON_PCIE_DATA, (v));

sys/dev/drm/radeon/r420.c

125

WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1);

sys/dev/drm/radeon/r420.c

128

WREG32(R300_GB_TILE_CONFIG, tmp);

sys/dev/drm/radeon/r420.c

134

WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);

sys/dev/drm/radeon/r420.c

136

WREG32(R300_RB2D_DSTCACHE_MODE,

sys/dev/drm/radeon/r420.c

164

WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg));

sys/dev/drm/radeon/r420.c

175

WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/r420.c

177

WREG32(R_0001FC_MC_IND_DATA, v);

sys/dev/drm/radeon/r420.c

91

WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |

sys/dev/drm/radeon/r520.c

144

WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);

sys/dev/drm/radeon/r520.c

149

WREG32(R_000134_HDP_FB_LOCATION,

sys/dev/drm/radeon/r520.c

79

WREG32(0x4128, 0xFF);

sys/dev/drm/radeon/r600.c

1019

WREG32(DC_HPD1_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1022

WREG32(DC_HPD2_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1025

WREG32(DC_HPD3_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1028

WREG32(DC_HPD4_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1032

WREG32(DC_HPD5_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1035

WREG32(DC_HPD6_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1043

WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1046

WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1049

WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);

sys/dev/drm/radeon/r600.c

1080

WREG32(HDP_DEBUG1, 0);

sys/dev/drm/radeon/r600.c

1083

WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);

sys/dev/drm/radeon/r600.c

1085

WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/r600.c

1086

WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);

sys/dev/drm/radeon/r600.c

1087

WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));

sys/dev/drm/radeon/r600.c

1133

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/r600.c

1136

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/r600.c

1137

WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));

sys/dev/drm/radeon/r600.c

1143

WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1144

WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1145

WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);

sys/dev/drm/radeon/r600.c

1146

WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1147

WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1148

WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1149

WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1150

WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1151

WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1152

WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1153

WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1154

WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1155

WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1156

WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1157

WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

sys/dev/drm/radeon/r600.c

1158

WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

sys/dev/drm/radeon/r600.c

1159

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/r600.c

116

WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));

sys/dev/drm/radeon/r600.c

1160

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

sys/dev/drm/radeon/r600.c

1161

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

sys/dev/drm/radeon/r600.c

1162

WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

sys/dev/drm/radeon/r600.c

1164

WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/r600.c

1167

WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

sys/dev/drm/radeon/r600.c

1184

WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

sys/dev/drm/radeon/r600.c

1187

WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/r600.c

1189

WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));

sys/dev/drm/radeon/r600.c

1193

WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1194

WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1195

WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1196

WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1197

WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1198

WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1199

WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1200

WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1201

WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1202

WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1203

WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1204

WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1205

WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1206

WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1207

WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1208

WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1225

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/r600.c

1228

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/r600.c

1229

WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));

sys/dev/drm/radeon/r600.c

1235

WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1236

WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1237

WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);

sys/dev/drm/radeon/r600.c

1238

WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1239

WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1240

WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1241

WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1242

WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1243

WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1244

WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1245

WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1246

WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1247

WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

sys/dev/drm/radeon/r600.c

1248

WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);

sys/dev/drm/radeon/r600.c

1250

WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

sys/dev/drm/radeon/r600.c

127

WREG32(R600_RCU_INDEX, ((reg) & 0x1fff));

sys/dev/drm/radeon/r600.c

1274

WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));

sys/dev/drm/radeon/r600.c

1276

WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);

sys/dev/drm/radeon/r600.c

128

WREG32(R600_RCU_DATA, (v));

sys/dev/drm/radeon/r600.c

1286

WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/r600.c

1288

WREG32(R_0028FC_MC_DATA, v);

sys/dev/drm/radeon/r600.c

1289

WREG32(R_0028F8_MC_INDEX, 0x7F);

sys/dev/drm/radeon/r600.c

1301

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

1302

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

1303

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/r600.c

1304

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

1305

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

1307

WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/radeon/r600.c

1314

WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);

sys/dev/drm/radeon/r600.c

1319

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/r600.c

1321

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/r600.c

1325

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/r600.c

1327

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/r600.c

1331

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);

sys/dev/drm/radeon/r600.c

1332

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);

sys/dev/drm/radeon/r600.c

1334

WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);

sys/dev/drm/radeon/r600.c

1337

WREG32(MC_VM_FB_LOCATION, tmp);

sys/dev/drm/radeon/r600.c

1338

WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

sys/dev/drm/radeon/r600.c

1339

WREG32(HDP_NONSURFACE_INFO, (2 << 7));

sys/dev/drm/radeon/r600.c

1340

WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

sys/dev/drm/radeon/r600.c

1342

WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);

sys/dev/drm/radeon/r600.c

1343

WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);

sys/dev/drm/radeon/r600.c

1344

WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);

sys/dev/drm/radeon/r600.c

1346

WREG32(MC_VM_AGP_BASE, 0);

sys/dev/drm/radeon/r600.c

1347

WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/radeon/r600.c

1348

WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/radeon/r600.c

138

WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/radeon/r600.c

149

WREG32(R600_UVD_CTX_INDEX, ((reg) & 0x1ff));

sys/dev/drm/radeon/r600.c

150

WREG32(R600_UVD_CTX_DATA, (v));

sys/dev/drm/radeon/r600.c

1554

WREG32(R600_BIOS_3_SCRATCH, tmp);

sys/dev/drm/radeon/r600.c

1690

WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));

sys/dev/drm/radeon/r600.c

1692

WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));

sys/dev/drm/radeon/r600.c

1695

WREG32(RLC_CNTL, 0);

sys/dev/drm/radeon/r600.c

1701

WREG32(DMA_RB_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1778

WREG32(R_008020_GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/r600.c

1784

WREG32(R_008020_GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/r600.c

1792

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/r600.c

1798

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/r600.c

1822

WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));

sys/dev/drm/radeon/r600.c

1824

WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));

sys/dev/drm/radeon/r600.c

1827

WREG32(RLC_CNTL, 0);

sys/dev/drm/radeon/r600.c

1832

WREG32(DMA_RB_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1850

WREG32(BUS_CNTL, tmp);

sys/dev/drm/radeon/r600.c

1860

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/r600.c

1862

WREG32(SRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r600.c

2067

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

2068

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

2069

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/r600.c

2070

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

2071

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/r600.c

2074

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

sys/dev/drm/radeon/r600.c

2131

WREG32(GB_TILING_CONFIG, tiling_config);

sys/dev/drm/radeon/r600.c

2132

WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);

sys/dev/drm/radeon/r600.c

2133

WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);

sys/dev/drm/radeon/r600.c

2134

WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);

sys/dev/drm/radeon/r600.c

2137

WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);

sys/dev/drm/radeon/r600.c

2138

WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);

sys/dev/drm/radeon/r600.c

2141

WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));

sys/dev/drm/radeon/r600.c

2142

WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));

sys/dev/drm/radeon/r600.c

2144

WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |

sys/dev/drm/radeon/r600.c

2148

WREG32(ARB_GDEC_RD_CNTL, 0x00000021);

sys/dev/drm/radeon/r600.c

2154

WREG32(SX_DEBUG_1, tmp);

sys/dev/drm/radeon/r600.c

2162

WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);

sys/dev/drm/radeon/r600.c

2164

WREG32(DB_DEBUG, 0);

sys/dev/drm/radeon/r600.c

2166

WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |

sys/dev/drm/radeon/r600.c

2169

WREG32(PA_SC_MULTI_CHIP_CNTL, 0);

sys/dev/drm/radeon/r600.c

2170

WREG32(VGT_NUM_INSTANCES, 0);

sys/dev/drm/radeon/r600.c

2172

WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));

sys/dev/drm/radeon/r600.c

2173

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));

sys/dev/drm/radeon/r600.c

2189

WREG32(SQ_MS_FIFO_SIZES, tmp);

sys/dev/drm/radeon/r600.c

2271

WREG32(SQ_CONFIG, sq_config);

sys/dev/drm/radeon/r600.c

2272

WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);

sys/dev/drm/radeon/r600.c

2273

WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);

sys/dev/drm/radeon/r600.c

2274

WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);

sys/dev/drm/radeon/r600.c

2275

WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);

sys/dev/drm/radeon/r600.c

2276

WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);

sys/dev/drm/radeon/r600.c

2282

WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));

sys/dev/drm/radeon/r600.c

2284

WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));

sys/dev/drm/radeon/r600.c

2288

WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |

sys/dev/drm/radeon/r600.c

2290

WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |

sys/dev/drm/radeon/r600.c

2294

WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |

sys/dev/drm/radeon/r600.c

2298

WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |

sys/dev/drm/radeon/r600.c

2303

WREG32(VGT_STRMOUT_EN, 0);

sys/dev/drm/radeon/r600.c

2321

WREG32(VGT_ES_PER_GS, 128);

sys/dev/drm/radeon/r600.c

2322

WREG32(VGT_GS_PER_ES, tmp);

sys/dev/drm/radeon/r600.c

2323

WREG32(VGT_GS_PER_VS, 2);

sys/dev/drm/radeon/r600.c

2324

WREG32(VGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/radeon/r600.c

2327

WREG32(PA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/radeon/r600.c

2328

WREG32(VGT_STRMOUT_EN, 0);

sys/dev/drm/radeon/r600.c

2329

WREG32(SX_MISC, 0);

sys/dev/drm/radeon/r600.c

2330

WREG32(PA_SC_MODE_CNTL, 0);

sys/dev/drm/radeon/r600.c

2331

WREG32(PA_SC_AA_CONFIG, 0);

sys/dev/drm/radeon/r600.c

2332

WREG32(PA_SC_LINE_STIPPLE, 0);

sys/dev/drm/radeon/r600.c

2333

WREG32(SPI_INPUT_Z, 0);

sys/dev/drm/radeon/r600.c

2334

WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));

sys/dev/drm/radeon/r600.c

2335

WREG32(CB_COLOR7_FRAG, 0);

sys/dev/drm/radeon/r600.c

2338

WREG32(CB_COLOR0_BASE, 0);

sys/dev/drm/radeon/r600.c

2339

WREG32(CB_COLOR1_BASE, 0);

sys/dev/drm/radeon/r600.c

2340

WREG32(CB_COLOR2_BASE, 0);

sys/dev/drm/radeon/r600.c

2341

WREG32(CB_COLOR3_BASE, 0);

sys/dev/drm/radeon/r600.c

2342

WREG32(CB_COLOR4_BASE, 0);

sys/dev/drm/radeon/r600.c

2343

WREG32(CB_COLOR5_BASE, 0);

sys/dev/drm/radeon/r600.c

2344

WREG32(CB_COLOR6_BASE, 0);

sys/dev/drm/radeon/r600.c

2345

WREG32(CB_COLOR7_BASE, 0);

sys/dev/drm/radeon/r600.c

2346

WREG32(CB_COLOR7_FRAG, 0);

sys/dev/drm/radeon/r600.c

2366

WREG32(TC_CNTL, tmp);

sys/dev/drm/radeon/r600.c

2369

WREG32(HDP_HOST_PATH_CNTL, tmp);

sys/dev/drm/radeon/r600.c

2373

WREG32(ARB_POP, tmp);

sys/dev/drm/radeon/r600.c

2375

WREG32(PA_SC_MULTI_CHIP_CNTL, 0);

sys/dev/drm/radeon/r600.c

2376

WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |

sys/dev/drm/radeon/r600.c

2378

WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));

sys/dev/drm/radeon/r600.c

2379

WREG32(VC_ENHANCE, 0);

sys/dev/drm/radeon/r600.c

2392

WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));

sys/dev/drm/radeon/r600.c

2404

WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));

sys/dev/drm/radeon/r600.c

2406

WREG32(PCIE_PORT_DATA, (v));

sys/dev/drm/radeon/r600.c

2418

WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));

sys/dev/drm/radeon/r600.c

2419

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/r600.c

2629

WREG32(R600_CP_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/r600.c

2663

WREG32(CP_RB_CNTL,

sys/dev/drm/radeon/r600.c

2670

WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);

sys/dev/drm/radeon/r600.c

2673

WREG32(GRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r600.c

2675

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/r600.c

2678

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/r600.c

2680

WREG32(CP_ME_RAM_DATA,

sys/dev/drm/radeon/r600.c

2684

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/r600.c

2686

WREG32(CP_PFP_UCODE_DATA,

sys/dev/drm/radeon/r600.c

2689

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/r600.c

2690

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/r600.c

2691

WREG32(CP_ME_RAM_RADDR, 0);

sys/dev/drm/radeon/r600.c

2721

WREG32(R_0086D8_CP_ME_CNTL, cp_me);

sys/dev/drm/radeon/r600.c

2733

WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);

sys/dev/drm/radeon/r600.c

2736

WREG32(GRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r600.c

2744

WREG32(CP_RB_CNTL, tmp);

sys/dev/drm/radeon/r600.c

2745

WREG32(CP_SEM_WAIT_TIMER, 0x0);

sys/dev/drm/radeon/r600.c

2748

WREG32(CP_RB_WPTR_DELAY, 0);

sys/dev/drm/radeon/r600.c

2751

WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);

sys/dev/drm/radeon/r600.c

2752

WREG32(CP_RB_RPTR_WR, 0);

sys/dev/drm/radeon/r600.c

2754

WREG32(CP_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/r600.c

2757

WREG32(CP_RB_RPTR_ADDR,

sys/dev/drm/radeon/r600.c

2759

WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/r600.c

2760

WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);

sys/dev/drm/radeon/r600.c

2763

WREG32(SCRATCH_UMSK, 0xff);

sys/dev/drm/radeon/r600.c

2766

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/r600.c

2770

WREG32(CP_RB_CNTL, tmp);

sys/dev/drm/radeon/r600.c

2772

WREG32(CP_RB_BASE, ring->gpu_addr >> 8);

sys/dev/drm/radeon/r600.c

2773

WREG32(CP_DEBUG, (1 << 27) | (1 << 28));

sys/dev/drm/radeon/r600.c

2844

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/radeon/r600.c

3210

WREG32(CONFIG_CNTL, temp);

sys/dev/drm/radeon/r600.c

336

WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/r600.c

3423

WREG32(scratch, 0xCAFEDEAD);

sys/dev/drm/radeon/r600.c

3550

WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);

sys/dev/drm/radeon/r600.c

3553

WREG32(SRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/r600.c

3557

WREG32(RLC_CNTL, 0);

sys/dev/drm/radeon/r600.c

3562

WREG32(RLC_CNTL, RLC_ENABLE);

sys/dev/drm/radeon/r600.c

3575

WREG32(RLC_HB_CNTL, 0);

sys/dev/drm/radeon/r600.c

3577

WREG32(RLC_HB_BASE, 0);

sys/dev/drm/radeon/r600.c

3578

WREG32(RLC_HB_RPTR, 0);

sys/dev/drm/radeon/r600.c

3579

WREG32(RLC_HB_WPTR, 0);

sys/dev/drm/radeon/r600.c

3580

WREG32(RLC_HB_WPTR_LSB_ADDR, 0);

sys/dev/drm/radeon/r600.c

3581

WREG32(RLC_HB_WPTR_MSB_ADDR, 0);

sys/dev/drm/radeon/r600.c

3582

WREG32(RLC_MC_CNTL, 0);

sys/dev/drm/radeon/r600.c

3583

WREG32(RLC_UCODE_CNTL, 0);

sys/dev/drm/radeon/r600.c

3588

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/r600.c

3589

WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/r600.c

3593

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/r600.c

3594

WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/r600.c

3597

WREG32(RLC_UCODE_ADDR, 0);

sys/dev/drm/radeon/r600.c

3611

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/r600.c

3612

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/r600.c

3623

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/r600.c

3624

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/r600.c

3626

WREG32(IH_RB_RPTR, 0);

sys/dev/drm/radeon/r600.c

3627

WREG32(IH_RB_WPTR, 0);

sys/dev/drm/radeon/r600.c

3636

WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);

sys/dev/drm/radeon/r600.c

3638

WREG32(DMA_CNTL, tmp);

sys/dev/drm/radeon/r600.c

3639

WREG32(GRBM_INT_CNTL, 0);

sys/dev/drm/radeon/r600.c

3640

WREG32(DxMODE_INT_MASK, 0);

sys/dev/drm/radeon/r600.c

3641

WREG32(D1GRPH_INTERRUPT_CONTROL, 0);

sys/dev/drm/radeon/r600.c

3642

WREG32(D2GRPH_INTERRUPT_CONTROL, 0);

sys/dev/drm/radeon/r600.c

3644

WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/r600.c

3645

WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/r600.c

3647

WREG32(DC_HPD1_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3649

WREG32(DC_HPD2_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3651

WREG32(DC_HPD3_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3653

WREG32(DC_HPD4_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3656

WREG32(DC_HPD5_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3658

WREG32(DC_HPD6_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3660

WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);

sys/dev/drm/radeon/r600.c

3662

WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);

sys/dev/drm/radeon/r600.c

3665

WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3667

WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3670

WREG32(DACA_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/r600.c

3671

WREG32(DACB_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/r600.c

3673

WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3675

WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3677

WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3679

WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3681

WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3711

WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);

sys/dev/drm/radeon/r600.c

3719

WREG32(INTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/radeon/r600.c

3721

WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);

sys/dev/drm/radeon/r600.c

3732

WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/r600.c

3733

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/r600.c

3735

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/r600.c

3738

WREG32(IH_RB_RPTR, 0);

sys/dev/drm/radeon/r600.c

3739

WREG32(IH_RB_WPTR, 0);

sys/dev/drm/radeon/r600.c

3746

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/r600.c

3887

WREG32(CP_INT_CNTL, cp_int_cntl);

sys/dev/drm/radeon/r600.c

3888

WREG32(DMA_CNTL, dma_cntl);

sys/dev/drm/radeon/r600.c

3889

WREG32(DxMODE_INT_MASK, mode_int);

sys/dev/drm/radeon/r600.c

3890

WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);

sys/dev/drm/radeon/r600.c

3891

WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);

sys/dev/drm/radeon/r600.c

3892

WREG32(GRBM_INT_CNTL, grbm_int_cntl);

sys/dev/drm/radeon/r600.c

3894

WREG32(DC_HPD1_INT_CONTROL, hpd1);

sys/dev/drm/radeon/r600.c

3895

WREG32(DC_HPD2_INT_CONTROL, hpd2);

sys/dev/drm/radeon/r600.c

3896

WREG32(DC_HPD3_INT_CONTROL, hpd3);

sys/dev/drm/radeon/r600.c

3897

WREG32(DC_HPD4_INT_CONTROL, hpd4);

sys/dev/drm/radeon/r600.c

3899

WREG32(DC_HPD5_INT_CONTROL, hpd5);

sys/dev/drm/radeon/r600.c

3900

WREG32(DC_HPD6_INT_CONTROL, hpd6);

sys/dev/drm/radeon/r600.c

3901

WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);

sys/dev/drm/radeon/r600.c

3902

WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);

sys/dev/drm/radeon/r600.c

3904

WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);

sys/dev/drm/radeon/r600.c

3905

WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);

sys/dev/drm/radeon/r600.c

3908

WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);

sys/dev/drm/radeon/r600.c

3909

WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);

sys/dev/drm/radeon/r600.c

3910

WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);

sys/dev/drm/radeon/r600.c

3911

WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);

sys/dev/drm/radeon/r600.c

3912

WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);

sys/dev/drm/radeon/r600.c

3915

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/radeon/r600.c

3917

WREG32(RV770_CG_THERMAL_INT, thermal_int);

sys/dev/drm/radeon/r600.c

3952

WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);

sys/dev/drm/radeon/r600.c

3954

WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);

sys/dev/drm/radeon/r600.c

3956

WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);

sys/dev/drm/radeon/r600.c

3958

WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);

sys/dev/drm/radeon/r600.c

3960

WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);

sys/dev/drm/radeon/r600.c

3962

WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);

sys/dev/drm/radeon/r600.c

3967

WREG32(DC_HPD1_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3971

WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3978

WREG32(DC_HPD2_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3982

WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3989

WREG32(DC_HPD3_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3993

WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

3999

WREG32(DC_HPD4_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

4005

WREG32(DC_HPD5_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

4010

WREG32(DC_HPD6_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

4015

WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);

sys/dev/drm/radeon/r600.c

4020

WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);

sys/dev/drm/radeon/r600.c

4026

WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

4032

WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

4036

WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

4071

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/r600.c

4336

WREG32(IH_RB_RPTR, rptr);

sys/dev/drm/radeon/r600.c

4406

WREG32(HDP_DEBUG1, 0);

sys/dev/drm/radeon/r600.c

4409

WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);

sys/dev/drm/radeon/r600.c

4565

WREG32(MM_CFGREGS_CNTL, 0x8);

sys/dev/drm/radeon/r600.c

4567

WREG32(MM_CFGREGS_CNTL, 0);

sys/dev/drm/radeon/r600.c

4581

WREG32(0x541c, tmp | 0x8);

sys/dev/drm/radeon/r600.c

4582

WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);

sys/dev/drm/radeon/r600.c

4587

WREG32(MM_CFGREGS_CNTL, 0);

sys/dev/drm/radeon/r600.c

4629

WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/drm/radeon/r600.c

863

WREG32(DC_HPD1_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

871

WREG32(DC_HPD2_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

879

WREG32(DC_HPD3_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

887

WREG32(DC_HPD4_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

895

WREG32(DC_HPD5_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

904

WREG32(DC_HPD6_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

917

WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

925

WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

933

WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

965

WREG32(DC_HPD1_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

968

WREG32(DC_HPD2_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

971

WREG32(DC_HPD3_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

974

WREG32(DC_HPD4_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

978

WREG32(DC_HPD5_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

981

WREG32(DC_HPD6_CONTROL, tmp);

sys/dev/drm/radeon/r600.c

989

WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);

sys/dev/drm/radeon/r600.c

992

WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);

sys/dev/drm/radeon/r600.c

995

WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);

sys/dev/drm/radeon/r600_dma.c

105

WREG32(DMA_RB_CNTL, rb_cntl);

sys/dev/drm/radeon/r600_dma.c

125

WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);

sys/dev/drm/radeon/r600_dma.c

126

WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);

sys/dev/drm/radeon/r600_dma.c

134

WREG32(DMA_RB_CNTL, rb_cntl);

sys/dev/drm/radeon/r600_dma.c

137

WREG32(DMA_RB_RPTR, 0);

sys/dev/drm/radeon/r600_dma.c

138

WREG32(DMA_RB_WPTR, 0);

sys/dev/drm/radeon/r600_dma.c

141

WREG32(DMA_RB_RPTR_ADDR_HI,

sys/dev/drm/radeon/r600_dma.c

143

WREG32(DMA_RB_RPTR_ADDR_LO,

sys/dev/drm/radeon/r600_dma.c

149

WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);

sys/dev/drm/radeon/r600_dma.c

156

WREG32(DMA_IB_CNTL, ib_cntl);

sys/dev/drm/radeon/r600_dma.c

160

WREG32(DMA_CNTL, dma_cntl);

sys/dev/drm/radeon/r600_dma.c

163

WREG32(DMA_MODE, 1);

sys/dev/drm/radeon/r600_dma.c

166

WREG32(DMA_RB_WPTR, ring->wptr << 2);

sys/dev/drm/radeon/r600_dma.c

168

WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);

sys/dev/drm/radeon/r600_dma.c

87

WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc);

sys/dev/drm/radeon/r600_dpm.c

252

WREG32(CG_RLC_REQ_AND_RSP, 0x2);

sys/dev/drm/radeon/r600_dpm.c

260

WREG32(CG_RLC_REQ_AND_RSP, 0x0);

sys/dev/drm/radeon/r600_dpm.c

262

WREG32(GRBM_PWR_CNTL, 0x1);

sys/dev/drm/radeon/r600_dpm.c

341

WREG32(CG_BSP, BSP(p) | BSU(u));

sys/dev/drm/radeon/r600_dpm.c

348

WREG32(CG_RT, FLS(l_to_m) | FMS(m_to_h));

sys/dev/drm/radeon/r600_dpm.c

349

WREG32(CG_LT, FHS(h_to_m) | FMS(m_to_l));

sys/dev/drm/radeon/r600_dpm.c

355

WREG32(CG_FFCT_0 + (index * 4), UTC_0(u_t) | DTC_0(d_t));

sys/dev/drm/radeon/r600_dpm.c

373

WREG32(CG_FTV, vrv);

sys/dev/drm/radeon/r600_dpm.c

525

WREG32(LOWER_GPIO_ENABLE, mask & 0xffffffff);

sys/dev/drm/radeon/r600_dpm.c

526

WREG32(UPPER_GPIO_ENABLE, upper_32_bits(mask));

sys/dev/drm/radeon/r600_dpm.c

536

WREG32(CTXSW_VID_LOWER_GPIO_CNTL + (ix * 4), pins & 0xffffffff);

sys/dev/drm/radeon/r600_dpm.c

541

WREG32(VID_UPPER_GPIO_CNTL, tmp);

sys/dev/drm/radeon/r600_dpm.c

551

WREG32(GPIOPAD_MASK, gpio);

sys/dev/drm/radeon/r600_dpm.c

555

WREG32(GPIOPAD_EN, gpio);

sys/dev/drm/radeon/r600_dpm.c

559

WREG32(GPIOPAD_A, gpio);

sys/dev/drm/radeon/r600_hdmi.c

168

WREG32(AZ_HOT_PLUG_CONTROL, tmp);

sys/dev/drm/radeon/r600_hdmi.c

226

WREG32(HDMI0_AVI_INFO0 + offset,

sys/dev/drm/radeon/r600_hdmi.c

228

WREG32(HDMI0_AVI_INFO1 + offset,

sys/dev/drm/radeon/r600_hdmi.c

230

WREG32(HDMI0_AVI_INFO2 + offset,

sys/dev/drm/radeon/r600_hdmi.c

232

WREG32(HDMI0_AVI_INFO3 + offset,

sys/dev/drm/radeon/r600_hdmi.c

257

WREG32(HDMI0_AUDIO_INFO0 + offset,

sys/dev/drm/radeon/r600_hdmi.c

259

WREG32(HDMI0_AUDIO_INFO1 + offset,

sys/dev/drm/radeon/r600_hdmi.c

336

WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100);

sys/dev/drm/radeon/r600_hdmi.c

337

WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);

sys/dev/drm/radeon/r600_hdmi.c

338

WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */

sys/dev/drm/radeon/r600_hdmi.c

340

WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100);

sys/dev/drm/radeon/r600_hdmi.c

341

WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100);

sys/dev/drm/radeon/r600_hdmi.c

342

WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */

sys/dev/drm/radeon/r600_hdmi.c

459

WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

sys/dev/drm/radeon/r600_hdmi.c

528

WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);

sys/dev/drm/radeon/radeon.h

2570

WREG32(reg, tmp_); \

sys/dev/drm/radeon/radeon_agp.c

253

WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);

sys/dev/drm/radeon/radeon_atombios.c

4090

WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4091

WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4093

WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4094

WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4124

WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);

sys/dev/drm/radeon/radeon_atombios.c

4147

WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4149

WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4329

WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4330

WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4331

WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4333

WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4334

WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4335

WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4389

WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4391

WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4472

WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);

sys/dev/drm/radeon/radeon_atombios.c

4474

WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);

sys/dev/drm/radeon/radeon_audio.c

131

WREG32(reg, v);

sys/dev/drm/radeon/radeon_bios.c

322

WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

sys/dev/drm/radeon/radeon_bios.c

325

WREG32(AVIVO_D1VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

328

WREG32(AVIVO_D2VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

331

WREG32(AVIVO_VGA_RENDER_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

334

WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);

sys/dev/drm/radeon/radeon_bios.c

339

WREG32(R600_BUS_CNTL, bus_cntl);

sys/dev/drm/radeon/radeon_bios.c

341

WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);

sys/dev/drm/radeon/radeon_bios.c

342

WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);

sys/dev/drm/radeon/radeon_bios.c

343

WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);

sys/dev/drm/radeon/radeon_bios.c

345

WREG32(R600_ROM_CNTL, rom_cntl);

sys/dev/drm/radeon/radeon_bios.c

371

WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));

sys/dev/drm/radeon/radeon_bios.c

373

WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

sys/dev/drm/radeon/radeon_bios.c

375

WREG32(AVIVO_D1VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

378

WREG32(AVIVO_D2VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

381

WREG32(AVIVO_VGA_RENDER_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

388

WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |

sys/dev/drm/radeon/radeon_bios.c

396

WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));

sys/dev/drm/radeon/radeon_bios.c

398

WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));

sys/dev/drm/radeon/radeon_bios.c

404

WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);

sys/dev/drm/radeon/radeon_bios.c

411

WREG32(RADEON_VIPH_CONTROL, viph_control);

sys/dev/drm/radeon/radeon_bios.c

412

WREG32(R600_BUS_CNTL, bus_cntl);

sys/dev/drm/radeon/radeon_bios.c

413

WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);

sys/dev/drm/radeon/radeon_bios.c

414

WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);

sys/dev/drm/radeon/radeon_bios.c

415

WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);

sys/dev/drm/radeon/radeon_bios.c

416

WREG32(R600_ROM_CNTL, rom_cntl);

sys/dev/drm/radeon/radeon_bios.c

452

WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));

sys/dev/drm/radeon/radeon_bios.c

454

WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));

sys/dev/drm/radeon/radeon_bios.c

456

WREG32(AVIVO_D1VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

459

WREG32(AVIVO_D2VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

462

WREG32(AVIVO_VGA_RENDER_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

465

WREG32(R600_ROM_CNTL,

sys/dev/drm/radeon/radeon_bios.c

470

WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));

sys/dev/drm/radeon/radeon_bios.c

471

WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,

sys/dev/drm/radeon/radeon_bios.c

473

WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,

sys/dev/drm/radeon/radeon_bios.c

475

WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,

sys/dev/drm/radeon/radeon_bios.c

477

WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,

sys/dev/drm/radeon/radeon_bios.c

479

WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));

sys/dev/drm/radeon/radeon_bios.c

484

WREG32(RADEON_VIPH_CONTROL, viph_control);

sys/dev/drm/radeon/radeon_bios.c

485

WREG32(R600_BUS_CNTL, bus_cntl);

sys/dev/drm/radeon/radeon_bios.c

486

WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);

sys/dev/drm/radeon/radeon_bios.c

487

WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);

sys/dev/drm/radeon/radeon_bios.c

488

WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);

sys/dev/drm/radeon/radeon_bios.c

489

WREG32(R600_ROM_CNTL, rom_cntl);

sys/dev/drm/radeon/radeon_bios.c

490

WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);

sys/dev/drm/radeon/radeon_bios.c

491

WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);

sys/dev/drm/radeon/radeon_bios.c

492

WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);

sys/dev/drm/radeon/radeon_bios.c

493

WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);

sys/dev/drm/radeon/radeon_bios.c

494

WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);

sys/dev/drm/radeon/radeon_bios.c

495

WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);

sys/dev/drm/radeon/radeon_bios.c

524

WREG32(RADEON_SEPROM_CNTL1,

sys/dev/drm/radeon/radeon_bios.c

527

WREG32(RADEON_GPIOPAD_A, 0);

sys/dev/drm/radeon/radeon_bios.c

528

WREG32(RADEON_GPIOPAD_EN, 0);

sys/dev/drm/radeon/radeon_bios.c

529

WREG32(RADEON_GPIOPAD_MASK, 0);

sys/dev/drm/radeon/radeon_bios.c

532

WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));

sys/dev/drm/radeon/radeon_bios.c

535

WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));

sys/dev/drm/radeon/radeon_bios.c

538

WREG32(AVIVO_D1VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

541

WREG32(AVIVO_D2VGA_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

544

WREG32(AVIVO_VGA_RENDER_CONTROL,

sys/dev/drm/radeon/radeon_bios.c

550

WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);

sys/dev/drm/radeon/radeon_bios.c

551

WREG32(RADEON_VIPH_CONTROL, viph_control);

sys/dev/drm/radeon/radeon_bios.c

552

WREG32(RV370_BUS_CNTL, bus_cntl);

sys/dev/drm/radeon/radeon_bios.c

553

WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);

sys/dev/drm/radeon/radeon_bios.c

554

WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);

sys/dev/drm/radeon/radeon_bios.c

555

WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);

sys/dev/drm/radeon/radeon_bios.c

556

WREG32(RADEON_GPIOPAD_A, gpiopad_a);

sys/dev/drm/radeon/radeon_bios.c

557

WREG32(RADEON_GPIOPAD_EN, gpiopad_en);

sys/dev/drm/radeon/radeon_bios.c

558

WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);

sys/dev/drm/radeon/radeon_bios.c

596

WREG32(RADEON_SEPROM_CNTL1,

sys/dev/drm/radeon/radeon_bios.c

601

WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));

sys/dev/drm/radeon/radeon_bios.c

605

WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));

sys/dev/drm/radeon/radeon_bios.c

607

WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));

sys/dev/drm/radeon/radeon_bios.c

610

WREG32(RADEON_CRTC_GEN_CNTL,

sys/dev/drm/radeon/radeon_bios.c

615

WREG32(RADEON_CRTC2_GEN_CNTL,

sys/dev/drm/radeon/radeon_bios.c

620

WREG32(RADEON_CRTC_EXT_CNTL,

sys/dev/drm/radeon/radeon_bios.c

626

WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));

sys/dev/drm/radeon/radeon_bios.c

632

WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);

sys/dev/drm/radeon/radeon_bios.c

633

WREG32(RADEON_VIPH_CONTROL, viph_control);

sys/dev/drm/radeon/radeon_bios.c

635

WREG32(RV370_BUS_CNTL, bus_cntl);

sys/dev/drm/radeon/radeon_bios.c

637

WREG32(RADEON_BUS_CNTL, bus_cntl);

sys/dev/drm/radeon/radeon_bios.c

638

WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);

sys/dev/drm/radeon/radeon_bios.c

640

WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);

sys/dev/drm/radeon/radeon_bios.c

642

WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);

sys/dev/drm/radeon/radeon_bios.c

644

WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);

sys/dev/drm/radeon/radeon_combios.c

2904

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2914

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2958

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

2968

WREG32(reg, val);

sys/dev/drm/radeon/radeon_combios.c

3021

WREG32(addr, val);

sys/dev/drm/radeon/radeon_combios.c

3026

WREG32(addr, val);

sys/dev/drm/radeon/radeon_combios.c

3036

WREG32(addr, tmp);

sys/dev/drm/radeon/radeon_combios.c

3046

WREG32(addr, tmp);

sys/dev/drm/radeon/radeon_combios.c

3208

WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);

sys/dev/drm/radeon/radeon_combios.c

3214

WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);

sys/dev/drm/radeon/radeon_combios.c

3235

WREG32(RADEON_MEM_CNTL, mem_cntl);

sys/dev/drm/radeon/radeon_combios.c

3274

WREG32(RADEON_MEM_CNTL, mem_cntl);

sys/dev/drm/radeon/radeon_combios.c

3312

WREG32(RADEON_CONFIG_MEMSIZE, mem_size);

sys/dev/drm/radeon/radeon_combios.c

3433

WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);

sys/dev/drm/radeon/radeon_combios.c

3434

WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_combios.c

3435

WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);

sys/dev/drm/radeon/radeon_combios.c

3451

WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_combios.c

3553

WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);

sys/dev/drm/radeon/radeon_combios.c

3554

WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);

sys/dev/drm/radeon/radeon_combios.c

3589

WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);

sys/dev/drm/radeon/radeon_combios.c

3624

WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);

sys/dev/drm/radeon/radeon_cursor.c

101

WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

102

WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |

sys/dev/drm/radeon/radeon_cursor.c

108

WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,

sys/dev/drm/radeon/radeon_cursor.c

111

WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,

sys/dev/drm/radeon/radeon_cursor.c

115

WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

117

WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);

sys/dev/drm/radeon/radeon_cursor.c

118

WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |

sys/dev/drm/radeon/radeon_cursor.c

122

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

127

WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);

sys/dev/drm/radeon/radeon_cursor.c

130

WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);

sys/dev/drm/radeon/radeon_cursor.c

216

WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/radeon/radeon_cursor.c

217

WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/radeon/radeon_cursor.c

218

WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

221

WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);

sys/dev/drm/radeon/radeon_cursor.c

222

WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);

sys/dev/drm/radeon/radeon_cursor.c

223

WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

232

WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

236

WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

241

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

42

WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

sys/dev/drm/radeon/radeon_cursor.c

49

WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);

sys/dev/drm/radeon/radeon_cursor.c

56

WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);

sys/dev/drm/radeon/radeon_cursor.c

97

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_cursor.c

99

WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_device.c

216

WREG32(reg, tmp);

sys/dev/drm/radeon/radeon_device.c

245

WREG32(RADEON_SURFACE_CNTL, 0);

sys/dev/drm/radeon/radeon_device.c

896

WREG32(reg*4, val);

sys/dev/drm/radeon/radeon_display.c

100

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

sys/dev/drm/radeon/radeon_display.c

102

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

107

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

126

WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

129

WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

131

WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

133

WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

137

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

139

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

140

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

141

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

143

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

144

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

145

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

147

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

148

WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);

sys/dev/drm/radeon/radeon_display.c

150

WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

155

WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

161

WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

166

WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

169

WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

172

WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

176

WREG32(0x6940 + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

181

WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/radeon_display.c

200

WREG32(RADEON_DAC_CNTL2, dac2_cntl);

sys/dev/drm/radeon/radeon_display.c

207

WREG32(RADEON_PALETTE_30_DATA,

sys/dev/drm/radeon/radeon_display.c

51

WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

53

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

54

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

55

WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

57

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

58

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

59

WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

61

WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);

sys/dev/drm/radeon/radeon_display.c

62

WREG32(AVIVO_DC_LUT_RW_MODE, 0);

sys/dev/drm/radeon/radeon_display.c

63

WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);

sys/dev/drm/radeon/radeon_display.c

70

WREG32(AVIVO_DC_LUT_30_COLOR,

sys/dev/drm/radeon/radeon_display.c

89

WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

91

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

92

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

93

WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_display.c

95

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

96

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

97

WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);

sys/dev/drm/radeon/radeon_display.c

99

WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_dp_auxch.c

101

WREG32(chan->rec.mask_clk_reg, tmp);

sys/dev/drm/radeon/radeon_dp_auxch.c

110

WREG32(AUX_CONTROL + aux_offset[instance], tmp);

sys/dev/drm/radeon/radeon_dp_auxch.c

113

WREG32(AUX_SW_CONTROL + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

115

WREG32(AUX_SW_CONTROL + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

121

WREG32(AUX_SW_DATA + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

125

WREG32(AUX_SW_DATA + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

129

WREG32(AUX_SW_DATA + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

133

WREG32(AUX_SW_DATA + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

139

WREG32(AUX_SW_DATA + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

145

WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK);

sys/dev/drm/radeon/radeon_dp_auxch.c

148

WREG32(AUX_SW_CONTROL + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

179

WREG32(AUX_SW_DATA + aux_offset[instance],

sys/dev/drm/radeon/radeon_dp_auxch.c

194

WREG32(AUX_SW_INTERRUPT_CONTROL + aux_offset[instance], AUX_SW_DONE_ACK);

sys/dev/drm/radeon/radeon_dp_mst.c

174

WREG32(NI_DP_MSE_RATE_CNTL + offset, val);

sys/dev/drm/radeon/radeon_dp_mst.c

48

WREG32(NI_DIG_BE_CNTL + primary->offset, reg);

sys/dev/drm/radeon/radeon_dp_mst.c

87

WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);

sys/dev/drm/radeon/radeon_dp_mst.c

89

WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);

sys/dev/drm/radeon/radeon_fence.c

69

WREG32(drv->scratch_reg, seq);

sys/dev/drm/radeon/radeon_i2c.c

117

WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |

sys/dev/drm/radeon/radeon_i2c.c

120

WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |

sys/dev/drm/radeon/radeon_i2c.c

131

WREG32(rec->mask_clk_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

136

WREG32(rec->a_clk_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

139

WREG32(rec->a_data_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

143

WREG32(rec->en_clk_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

146

WREG32(rec->en_data_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

150

WREG32(rec->mask_clk_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

154

WREG32(rec->mask_data_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

169

WREG32(rec->mask_clk_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

173

WREG32(rec->mask_data_reg, temp);

sys/dev/drm/radeon/radeon_i2c.c

218

WREG32(rec->en_clk_reg, val);

sys/dev/drm/radeon/radeon_i2c.c

231

WREG32(rec->en_data_reg, val);

sys/dev/drm/radeon/radeon_i2c.c

352

WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);

sys/dev/drm/radeon/radeon_i2c.c

466

WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

470

WREG32(i2c_data, (p->addr << 1) & 0xff);

sys/dev/drm/radeon/radeon_i2c.c

471

WREG32(i2c_data, 0);

sys/dev/drm/radeon/radeon_i2c.c

472

WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |

sys/dev/drm/radeon/radeon_i2c.c

476

WREG32(i2c_cntl_0, reg);

sys/dev/drm/radeon/radeon_i2c.c

487

WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);

sys/dev/drm/radeon/radeon_i2c.c

499

WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

503

WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1);

sys/dev/drm/radeon/radeon_i2c.c

504

WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |

sys/dev/drm/radeon/radeon_i2c.c

508

WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);

sys/dev/drm/radeon/radeon_i2c.c

519

WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);

sys/dev/drm/radeon/radeon_i2c.c

526

WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

530

WREG32(i2c_data, (p->addr << 1) & 0xff);

sys/dev/drm/radeon/radeon_i2c.c

531

WREG32(i2c_data, p->buf[j]);

sys/dev/drm/radeon/radeon_i2c.c

532

WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |

sys/dev/drm/radeon/radeon_i2c.c

536

WREG32(i2c_cntl_0, reg);

sys/dev/drm/radeon/radeon_i2c.c

547

WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);

sys/dev/drm/radeon/radeon_i2c.c

557

WREG32(i2c_cntl_0, 0);

sys/dev/drm/radeon/radeon_i2c.c

558

WREG32(i2c_cntl_1, 0);

sys/dev/drm/radeon/radeon_i2c.c

559

WREG32(i2c_cntl_0, (RADEON_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

567

WREG32(RADEON_BIOS_6_SCRATCH, tmp);

sys/dev/drm/radeon/radeon_i2c.c

600

WREG32(rec->mask_clk_reg, tmp);

sys/dev/drm/radeon/radeon_i2c.c

605

WREG32(rec->mask_data_reg, tmp);

sys/dev/drm/radeon/radeon_i2c.c

611

WREG32(rec->a_clk_reg, tmp);

sys/dev/drm/radeon/radeon_i2c.c

616

WREG32(rec->a_data_reg, tmp);

sys/dev/drm/radeon/radeon_i2c.c

622

WREG32(rec->en_clk_reg, tmp);

sys/dev/drm/radeon/radeon_i2c.c

627

WREG32(rec->en_data_reg, tmp);

sys/dev/drm/radeon/radeon_i2c.c

632

WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);

sys/dev/drm/radeon/radeon_i2c.c

635

WREG32(0x494, saved2 | 0x1);

sys/dev/drm/radeon/radeon_i2c.c

637

WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);

sys/dev/drm/radeon/radeon_i2c.c

669

WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

672

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

sys/dev/drm/radeon/radeon_i2c.c

674

WREG32(AVIVO_DC_I2C_RESET, 0);

sys/dev/drm/radeon/radeon_i2c.c

676

WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);

sys/dev/drm/radeon/radeon_i2c.c

677

WREG32(AVIVO_DC_I2C_DATA, 0);

sys/dev/drm/radeon/radeon_i2c.c

679

WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));

sys/dev/drm/radeon/radeon_i2c.c

680

WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |

sys/dev/drm/radeon/radeon_i2c.c

683

WREG32(AVIVO_DC_I2C_CONTROL1, reg);

sys/dev/drm/radeon/radeon_i2c.c

684

WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);

sys/dev/drm/radeon/radeon_i2c.c

695

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);

sys/dev/drm/radeon/radeon_i2c.c

713

WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

716

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

sys/dev/drm/radeon/radeon_i2c.c

718

WREG32(AVIVO_DC_I2C_RESET, 0);

sys/dev/drm/radeon/radeon_i2c.c

720

WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1);

sys/dev/drm/radeon/radeon_i2c.c

721

WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));

sys/dev/drm/radeon/radeon_i2c.c

722

WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |

sys/dev/drm/radeon/radeon_i2c.c

725

WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);

sys/dev/drm/radeon/radeon_i2c.c

726

WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);

sys/dev/drm/radeon/radeon_i2c.c

737

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);

sys/dev/drm/radeon/radeon_i2c.c

753

WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

756

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

sys/dev/drm/radeon/radeon_i2c.c

758

WREG32(AVIVO_DC_I2C_RESET, 0);

sys/dev/drm/radeon/radeon_i2c.c

760

WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff);

sys/dev/drm/radeon/radeon_i2c.c

762

WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);

sys/dev/drm/radeon/radeon_i2c.c

764

WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));

sys/dev/drm/radeon/radeon_i2c.c

765

WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |

sys/dev/drm/radeon/radeon_i2c.c

768

WREG32(AVIVO_DC_I2C_CONTROL1, reg);

sys/dev/drm/radeon/radeon_i2c.c

769

WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);

sys/dev/drm/radeon/radeon_i2c.c

780

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);

sys/dev/drm/radeon/radeon_i2c.c

792

WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |

sys/dev/drm/radeon/radeon_i2c.c

795

WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);

sys/dev/drm/radeon/radeon_i2c.c

797

WREG32(AVIVO_DC_I2C_RESET, 0);

sys/dev/drm/radeon/radeon_i2c.c

799

WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);

sys/dev/drm/radeon/radeon_i2c.c

800

WREG32(AVIVO_DC_I2C_CONTROL1, saved1);

sys/dev/drm/radeon/radeon_i2c.c

801

WREG32(0x494, saved2);

sys/dev/drm/radeon/radeon_i2c.c

804

WREG32(RADEON_BIOS_6_SCRATCH, tmp);

sys/dev/drm/radeon/radeon_irq_kms.c

582

WREG32(reg, tmp |= mask);

sys/dev/drm/radeon/radeon_irq_kms.c

585

WREG32(reg, tmp & ~mask);

sys/dev/drm/radeon/radeon_legacy_crtc.c

200

WREG32(RADEON_FP_HORZ_STRETCH, fp_horz_stretch);

sys/dev/drm/radeon/radeon_legacy_crtc.c

201

WREG32(RADEON_FP_VERT_STRETCH, fp_vert_stretch);

sys/dev/drm/radeon/radeon_legacy_crtc.c

202

WREG32(RADEON_CRTC_MORE_CNTL, crtc_more_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

203

WREG32(RADEON_FP_HORZ_VERT_ACTIVE, fp_horz_vert_active);

sys/dev/drm/radeon/radeon_legacy_crtc.c

204

WREG32(RADEON_FP_H_SYNC_STRT_WID, fp_h_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

205

WREG32(RADEON_FP_V_SYNC_STRT_WID, fp_v_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

206

WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);

sys/dev/drm/radeon/radeon_legacy_crtc.c

207

WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);

sys/dev/drm/radeon/radeon_legacy_crtc.c

41

WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

42

WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

43

WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

539

WREG32(gen_cntl_reg, gen_cntl_val);

sys/dev/drm/radeon/radeon_legacy_crtc.c

543

WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);

sys/dev/drm/radeon/radeon_legacy_crtc.c

547

WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

549

WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);

sys/dev/drm/radeon/radeon_legacy_crtc.c

551

WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

552

WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);

sys/dev/drm/radeon/radeon_legacy_crtc.c

553

WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);

sys/dev/drm/radeon/radeon_legacy_crtc.c

675

WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

676

WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

678

WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

679

WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

712

WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

713

WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

714

WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_crtc.c

722

WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);

sys/dev/drm/radeon/radeon_legacy_crtc.c

723

WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_crtc.c

724

WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);

sys/dev/drm/radeon/radeon_legacy_crtc.c

725

WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1006

WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

103

WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1111

WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1114

WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1117

WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1118

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

113

WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

116

WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

120

WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1209

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1228

WREG32(RADEON_DAC_CNTL, dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1256

WREG32(RADEON_DAC_CNTL2, dac2_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1281

WREG32(RADEON_DAC_CNTL2, dac2_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1286

WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1288

WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1290

WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1293

WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1324

WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1326

WREG32(RADEON_CRTC2_GEN_CNTL,

sys/dev/drm/radeon/radeon_legacy_encoders.c

1331

WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1333

WREG32(RADEON_DAC_EXT_CNTL,

sys/dev/drm/radeon/radeon_legacy_encoders.c

1339

WREG32(RADEON_TV_DAC_CNTL,

sys/dev/drm/radeon/radeon_legacy_encoders.c

1347

WREG32(RADEON_TV_DAC_CNTL,

sys/dev/drm/radeon/radeon_legacy_encoders.c

1367

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1368

WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1369

WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1370

WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1371

WREG32(RADEON_DAC_CNTL2, dac_cntl2);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1395

WREG32(RADEON_DAC_CNTL2, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1404

WREG32(RADEON_TV_MASTER_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1414

WREG32(RADEON_TV_DAC_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1421

WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1433

WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1434

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1435

WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1436

WREG32(RADEON_DAC_CNTL2, dac_cntl2);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1471

WREG32(RADEON_GPIO_MONID, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1473

WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON |

sys/dev/drm/radeon/radeon_legacy_encoders.c

1479

WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX |

sys/dev/drm/radeon/radeon_legacy_encoders.c

1482

WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN |

sys/dev/drm/radeon/radeon_legacy_encoders.c

1485

WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1486

WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1487

WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1488

WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1489

WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1490

WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1492

WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1493

WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1494

WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1495

WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1513

WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1514

WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1515

WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1516

WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1517

WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1518

WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1519

WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1520

WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1521

WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1522

WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1523

WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1524

WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1525

WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1526

WREG32(RADEON_GPIO_MONID, gpio_monid);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1606

WREG32(RADEON_CRTC_EXT_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1611

WREG32(RADEON_CRTC2_GEN_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1617

WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1620

WREG32(RADEON_DISP_HW_DEBUG, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1629

WREG32(RADEON_TV_DAC_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1644

WREG32(RADEON_DAC_EXT_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1647

WREG32(RADEON_DAC_CNTL2, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1660

WREG32(RADEON_DAC_CNTL2, dac_cntl2);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1661

WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1662

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1665

WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1667

WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1669

WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

1672

WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);

sys/dev/drm/radeon/radeon_legacy_encoders.c

231

WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

232

WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

233

WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

236

WREG32(RADEON_CLOCK_CNTL_INDEX, 0);

sys/dev/drm/radeon/radeon_legacy_encoders.c

549

WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

550

WREG32(RADEON_DAC_CNTL, dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

551

WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

599

WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

602

WREG32(RADEON_DAC_CNTL2, dac2_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

609

WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

612

WREG32(RADEON_DAC_CNTL2, dac2_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

632

WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

670

WREG32(RADEON_CRTC_EXT_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

687

WREG32(RADEON_DAC_EXT_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

691

WREG32(RADEON_DAC_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

698

WREG32(RADEON_DAC_MACRO_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_encoders.c

706

WREG32(RADEON_DAC_CNTL, dac_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

707

WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

708

WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

709

WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

748

WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

85

WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);

sys/dev/drm/radeon/radeon_legacy_encoders.c

870

WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

871

WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

872

WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

88

WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

914

WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);

sys/dev/drm/radeon/radeon_legacy_encoders.c

93

WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

282

WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100);

sys/dev/drm/radeon/radeon_legacy_tv.c

294

WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff);

sys/dev/drm/radeon/radeon_legacy_tv.c

306

WREG32(RADEON_TV_HOST_WRITE_DATA, value);

sys/dev/drm/radeon/radeon_legacy_tv.c

308

WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);

sys/dev/drm/radeon/radeon_legacy_tv.c

309

WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT);

sys/dev/drm/radeon/radeon_legacy_tv.c

317

WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);

sys/dev/drm/radeon/radeon_legacy_tv.c

328

WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr);

sys/dev/drm/radeon/radeon_legacy_tv.c

329

WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD);

sys/dev/drm/radeon/radeon_legacy_tv.c

337

WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0);

sys/dev/drm/radeon/radeon_legacy_tv.c

393

WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr);

sys/dev/drm/radeon/radeon_legacy_tv.c

416

WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart);

sys/dev/drm/radeon/radeon_legacy_tv.c

417

WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart);

sys/dev/drm/radeon/radeon_legacy_tv.c

418

WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart);

sys/dev/drm/radeon/radeon_legacy_tv.c

758

WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |

sys/dev/drm/radeon/radeon_legacy_tv.c

767

WREG32(RADEON_TV_DAC_CNTL, tmp);

sys/dev/drm/radeon/radeon_legacy_tv.c

788

WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

789

WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1);

sys/dev/drm/radeon/radeon_legacy_tv.c

790

WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1);

sys/dev/drm/radeon/radeon_legacy_tv.c

791

WREG32(RADEON_TV_HSTART, const_ptr->hor_start);

sys/dev/drm/radeon/radeon_legacy_tv.c

793

WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1);

sys/dev/drm/radeon/radeon_legacy_tv.c

794

WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1);

sys/dev/drm/radeon/radeon_legacy_tv.c

795

WREG32(RADEON_TV_FTOTAL, tv_ftotal);

sys/dev/drm/radeon/radeon_legacy_tv.c

796

WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1);

sys/dev/drm/radeon/radeon_legacy_tv.c

797

WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2);

sys/dev/drm/radeon/radeon_legacy_tv.c

799

WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

800

WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

801

WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

803

WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST |

sys/dev/drm/radeon/radeon_legacy_tv.c

812

WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST));

sys/dev/drm/radeon/radeon_legacy_tv.c

815

WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE));

sys/dev/drm/radeon/radeon_legacy_tv.c

816

WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

817

WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1);

sys/dev/drm/radeon/radeon_legacy_tv.c

818

WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2);

sys/dev/drm/radeon/radeon_legacy_tv.c

819

WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN |

sys/dev/drm/radeon/radeon_legacy_tv.c

824

WREG32(RADEON_TV_CRC_CNTL, 0);

sys/dev/drm/radeon/radeon_legacy_tv.c

826

WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);

sys/dev/drm/radeon/radeon_legacy_tv.c

828

WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) |

sys/dev/drm/radeon/radeon_legacy_tv.c

830

WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) |

sys/dev/drm/radeon/radeon_legacy_tv.c

833

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);

sys/dev/drm/radeon/radeon_ttm.c

1099

WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);

sys/dev/drm/radeon/radeon_ttm.c

1101

WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);

sys/dev/drm/radeon/rs400.c

144

WREG32(RADEON_AGP_BASE, 0xFFFFFFFF);

sys/dev/drm/radeon/rs400.c

145

WREG32(RS480_AGP_BASE_2, 0);

sys/dev/drm/radeon/rs400.c

152

WREG32(RADEON_BUS_CNTL, tmp);

sys/dev/drm/radeon/rs400.c

154

WREG32(RADEON_MC_AGP_LOCATION, tmp);

sys/dev/drm/radeon/rs400.c

156

WREG32(RADEON_BUS_CNTL, tmp);

sys/dev/drm/radeon/rs400.c

283

WREG32(RS480_NB_MC_INDEX, reg & 0xff);

sys/dev/drm/radeon/rs400.c

285

WREG32(RS480_NB_MC_INDEX, 0xff);

sys/dev/drm/radeon/rs400.c

293

WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN);

sys/dev/drm/radeon/rs400.c

294

WREG32(RS480_NB_MC_DATA, (v));

sys/dev/drm/radeon/rs400.c

295

WREG32(RS480_NB_MC_INDEX, 0xff);

sys/dev/drm/radeon/rs400.c

393

WREG32(R_000148_MC_FB_LOCATION,

sys/dev/drm/radeon/rs600.c

120

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

123

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rs600.c

125

WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rs600.c

127

WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rs600.c

140

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

200

WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

203

WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

206

WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

209

WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

231

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/rs600.c

240

WREG32(voltage->gpio.reg, tmp);

sys/dev/drm/radeon/rs600.c

323

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

341

WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rs600.c

382

WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

390

WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

407

WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,

sys/dev/drm/radeon/rs600.c

411

WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,

sys/dev/drm/radeon/rs600.c

434

WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,

sys/dev/drm/radeon/rs600.c

438

WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,

sys/dev/drm/radeon/rs600.c

465

WREG32(RADEON_CP_CSQ_CNTL, 0);

sys/dev/drm/radeon/rs600.c

467

WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);

sys/dev/drm/radeon/rs600.c

468

WREG32(RADEON_CP_RB_RPTR_WR, 0);

sys/dev/drm/radeon/rs600.c

469

WREG32(RADEON_CP_RB_WPTR, 0);

sys/dev/drm/radeon/rs600.c

470

WREG32(RADEON_CP_RB_CNTL, tmp);

sys/dev/drm/radeon/rs600.c

476

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |

sys/dev/drm/radeon/rs600.c

480

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/rs600.c

485

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));

sys/dev/drm/radeon/rs600.c

488

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/rs600.c

493

WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));

sys/dev/drm/radeon/rs600.c

496

WREG32(R_0000F0_RBBM_SOFT_RESET, 0);

sys/dev/drm/radeon/rs600.c

564

WREG32(RADEON_BUS_CNTL, tmp);

sys/dev/drm/radeon/rs600.c

671

WREG32(R_000040_GEN_INT_CNTL, 0);

sys/dev/drm/radeon/rs600.c

694

WREG32(R_000040_GEN_INT_CNTL, tmp);

sys/dev/drm/radeon/rs600.c

695

WREG32(R_006540_DxMODE_INT_MASK, mode_int);

sys/dev/drm/radeon/rs600.c

696

WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);

sys/dev/drm/radeon/rs600.c

697

WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);

sys/dev/drm/radeon/rs600.c

699

WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);

sys/dev/drm/radeon/rs600.c

716

WREG32(R_006534_D1MODE_VBLANK_STATUS,

sys/dev/drm/radeon/rs600.c

720

WREG32(R_006D34_D2MODE_VBLANK_STATUS,

sys/dev/drm/radeon/rs600.c

726

WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

731

WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

743

WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);

sys/dev/drm/radeon/rs600.c

749

WREG32(R_000044_GEN_INT_STATUS, irqs);

sys/dev/drm/radeon/rs600.c

758

WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);

sys/dev/drm/radeon/rs600.c

759

WREG32(R_000040_GEN_INT_CNTL, 0);

sys/dev/drm/radeon/rs600.c

760

WREG32(R_006540_DxMODE_INT_MASK, 0);

sys/dev/drm/radeon/rs600.c

828

WREG32(RADEON_BUS_CNTL, msi_rearm);

sys/dev/drm/radeon/rs600.c

829

WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);

sys/dev/drm/radeon/rs600.c

832

WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);

sys/dev/drm/radeon/rs600.c

911

WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);

sys/dev/drm/radeon/rs600.c

912

WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);

sys/dev/drm/radeon/rs600.c

913

WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);

sys/dev/drm/radeon/rs600.c

914

WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);

sys/dev/drm/radeon/rs600.c

923

WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/rs600.c

933

WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/rs600.c

935

WREG32(R_000074_MC_IND_DATA, v);

sys/dev/drm/radeon/rs600.c

970

WREG32(R_000134_HDP_FB_LOCATION,

sys/dev/drm/radeon/rs690.c

247

WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);

sys/dev/drm/radeon/rs690.c

621

WREG32(R_006C9C_DCP_CONTROL, 0);

sys/dev/drm/radeon/rs690.c

623

WREG32(R_006C9C_DCP_CONTROL, 2);

sys/dev/drm/radeon/rs690.c

633

WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);

sys/dev/drm/radeon/rs690.c

644

WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);

sys/dev/drm/radeon/rs690.c

645

WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);

sys/dev/drm/radeon/rs690.c

646

WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);

sys/dev/drm/radeon/rs690.c

647

WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);

sys/dev/drm/radeon/rs690.c

655

WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));

sys/dev/drm/radeon/rs690.c

657

WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);

sys/dev/drm/radeon/rs690.c

665

WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |

sys/dev/drm/radeon/rs690.c

667

WREG32(R_00007C_MC_DATA, v);

sys/dev/drm/radeon/rs690.c

668

WREG32(R_000078_MC_INDEX, 0x7F);

sys/dev/drm/radeon/rs690.c

686

WREG32(R_000134_HDP_FB_LOCATION,

sys/dev/drm/radeon/rs780_dpm.c

278

WREG32(FVTHROT_PWM_CTRL_REG1,

sys/dev/drm/radeon/rs780_dpm.c

282

WREG32(FVTHROT_PWM_US_REG0, RS780_FVTHROTPWMUSREG0_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

283

WREG32(FVTHROT_PWM_US_REG1, RS780_FVTHROTPWMUSREG1_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

284

WREG32(FVTHROT_PWM_DS_REG0, RS780_FVTHROTPWMDSREG0_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

285

WREG32(FVTHROT_PWM_DS_REG1, RS780_FVTHROTPWMDSREG1_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

291

WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG2,

sys/dev/drm/radeon/rs780_dpm.c

295

WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG3,

sys/dev/drm/radeon/rs780_dpm.c

298

WREG32(FVTHROT_PWM_FEEDBACK_DIV_REG4,

sys/dev/drm/radeon/rs780_dpm.c

323

WREG32(FVTHROT_UTC0, RS780_FVTHROTUTC0_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

324

WREG32(FVTHROT_UTC1, RS780_FVTHROTUTC1_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

325

WREG32(FVTHROT_UTC2, RS780_FVTHROTUTC2_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

326

WREG32(FVTHROT_UTC3, RS780_FVTHROTUTC3_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

327

WREG32(FVTHROT_UTC4, RS780_FVTHROTUTC4_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

329

WREG32(FVTHROT_DTC0, RS780_FVTHROTDTC0_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

330

WREG32(FVTHROT_DTC1, RS780_FVTHROTDTC1_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

331

WREG32(FVTHROT_DTC2, RS780_FVTHROTDTC2_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

332

WREG32(FVTHROT_DTC3, RS780_FVTHROTDTC3_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

333

WREG32(FVTHROT_DTC4, RS780_FVTHROTDTC4_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

354

WREG32(FVTHROT_FB_US_REG0, RS780_FVTHROTFBUSREG0_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

355

WREG32(FVTHROT_FB_US_REG1, RS780_FVTHROTFBUSREG1_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

356

WREG32(FVTHROT_FB_DS_REG0, RS780_FVTHROTFBDSREG0_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

357

WREG32(FVTHROT_FB_DS_REG1, RS780_FVTHROTFBDSREG1_DFLT);

sys/dev/drm/radeon/rs780_dpm.c

366

WREG32(FVTHROT_TARGET_REG, 30000000 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

367

WREG32(FVTHROT_CB1, 1000000 * 5 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

368

WREG32(FVTHROT_CB2, 1000000 * 10 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

369

WREG32(FVTHROT_CB3, 1000000 * 30 / pi->refresh_rate);

sys/dev/drm/radeon/rs780_dpm.c

370

WREG32(FVTHROT_CB4, 1000000 * 50 / pi->refresh_rate);

sys/dev/drm/radeon/rv515.c

1253

WREG32(LB_MAX_REQ_OUTSTANDING, tmp);

sys/dev/drm/radeon/rv515.c

1264

WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);

sys/dev/drm/radeon/rv515.c

1265

WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);

sys/dev/drm/radeon/rv515.c

1266

WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);

sys/dev/drm/radeon/rv515.c

1267

WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);

sys/dev/drm/radeon/rv515.c

147

WREG32(R_000300_VGA_RENDER_CONTROL,

sys/dev/drm/radeon/rv515.c

212

WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));

sys/dev/drm/radeon/rv515.c

214

WREG32(MC_IND_INDEX, 0);

sys/dev/drm/radeon/rv515.c

225

WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));

sys/dev/drm/radeon/rv515.c

226

WREG32(MC_IND_DATA, (v));

sys/dev/drm/radeon/rv515.c

227

WREG32(MC_IND_INDEX, 0);

sys/dev/drm/radeon/rv515.c

301

WREG32(R_000300_VGA_RENDER_CONTROL, 0);

sys/dev/drm/radeon/rv515.c

310

WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/rv515.c

312

WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

313

WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/rv515.c

324

WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);

sys/dev/drm/radeon/rv515.c

327

WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

328

WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);

sys/dev/drm/radeon/rv515.c

345

WREG32(R600_BIF_FB_EN, 0);

sys/dev/drm/radeon/rv515.c

349

WREG32(R700_MC_CITF_CNTL, blackout);

sys/dev/drm/radeon/rv515.c

351

WREG32(R600_CITF_CNTL, blackout);

sys/dev/drm/radeon/rv515.c

363

WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

368

WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

383

WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,

sys/dev/drm/radeon/rv515.c

385

WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,

sys/dev/drm/radeon/rv515.c

388

WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,

sys/dev/drm/radeon/rv515.c

390

WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,

sys/dev/drm/radeon/rv515.c

394

WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],

sys/dev/drm/radeon/rv515.c

396

WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],

sys/dev/drm/radeon/rv515.c

399

WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);

sys/dev/drm/radeon/rv515.c

408

WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

413

WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

418

WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

437

WREG32(R700_MC_CITF_CNTL, tmp);

sys/dev/drm/radeon/rv515.c

439

WREG32(R600_CITF_CNTL, tmp);

sys/dev/drm/radeon/rv515.c

441

WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);

sys/dev/drm/radeon/rv515.c

448

WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);

sys/dev/drm/radeon/rv515.c

459

WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);

sys/dev/drm/radeon/rv515.c

461

WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);

sys/dev/drm/radeon/rv515.c

475

WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);

sys/dev/drm/radeon/rv515.c

480

WREG32(R_000134_HDP_FB_LOCATION,

sys/dev/drm/radeon/rv515.c

711

WREG32(0x659C + crtc->crtc_offset, 0x0);

sys/dev/drm/radeon/rv515.c

712

WREG32(0x6594 + crtc->crtc_offset, 0x705);

sys/dev/drm/radeon/rv515.c

713

WREG32(0x65A4 + crtc->crtc_offset, 0x10001);

sys/dev/drm/radeon/rv515.c

714

WREG32(0x65D8 + crtc->crtc_offset, 0x0);

sys/dev/drm/radeon/rv515.c

715

WREG32(0x65B0 + crtc->crtc_offset, 0x0);

sys/dev/drm/radeon/rv515.c

716

WREG32(0x65C0 + crtc->crtc_offset, 0x0);

sys/dev/drm/radeon/rv515.c

717

WREG32(0x65D4 + crtc->crtc_offset, 0x0);

sys/dev/drm/radeon/rv515.c

718

WREG32(index_reg, 0x0);

sys/dev/drm/radeon/rv515.c

719

WREG32(data_reg, 0x841880A8);

sys/dev/drm/radeon/rv515.c

720

WREG32(index_reg, 0x1);

sys/dev/drm/radeon/rv515.c

721

WREG32(data_reg, 0x84208680);

sys/dev/drm/radeon/rv515.c

722

WREG32(index_reg, 0x2);

sys/dev/drm/radeon/rv515.c

723

WREG32(data_reg, 0xBFF880B0);

sys/dev/drm/radeon/rv515.c

724

WREG32(index_reg, 0x100);

sys/dev/drm/radeon/rv515.c

725

WREG32(data_reg, 0x83D88088);

sys/dev/drm/radeon/rv515.c

726

WREG32(index_reg, 0x101);

sys/dev/drm/radeon/rv515.c

727

WREG32(data_reg, 0x84608680);

sys/dev/drm/radeon/rv515.c

728

WREG32(index_reg, 0x102);

sys/dev/drm/radeon/rv515.c

729

WREG32(data_reg, 0xBFF080D0);

sys/dev/drm/radeon/rv515.c

730

WREG32(index_reg, 0x200);

sys/dev/drm/radeon/rv515.c

731

WREG32(data_reg, 0x83988068);

sys/dev/drm/radeon/rv515.c

732

WREG32(index_reg, 0x201);

sys/dev/drm/radeon/rv515.c

733

WREG32(data_reg, 0x84A08680);

sys/dev/drm/radeon/rv515.c

734

WREG32(index_reg, 0x202);

sys/dev/drm/radeon/rv515.c

735

WREG32(data_reg, 0xBFF080F8);

sys/dev/drm/radeon/rv515.c

736

WREG32(index_reg, 0x300);

sys/dev/drm/radeon/rv515.c

737

WREG32(data_reg, 0x83588058);

sys/dev/drm/radeon/rv515.c

738

WREG32(index_reg, 0x301);

sys/dev/drm/radeon/rv515.c

739

WREG32(data_reg, 0x84E08660);

sys/dev/drm/radeon/rv515.c

740

WREG32(index_reg, 0x302);

sys/dev/drm/radeon/rv515.c

741

WREG32(data_reg, 0xBFF88120);

sys/dev/drm/radeon/rv515.c

742

WREG32(index_reg, 0x400);

sys/dev/drm/radeon/rv515.c

743

WREG32(data_reg, 0x83188040);

sys/dev/drm/radeon/rv515.c

744

WREG32(index_reg, 0x401);

sys/dev/drm/radeon/rv515.c

745

WREG32(data_reg, 0x85008660);

sys/dev/drm/radeon/rv515.c

746

WREG32(index_reg, 0x402);

sys/dev/drm/radeon/rv515.c

747

WREG32(data_reg, 0xBFF88150);

sys/dev/drm/radeon/rv515.c

748

WREG32(index_reg, 0x500);

sys/dev/drm/radeon/rv515.c

749

WREG32(data_reg, 0x82D88030);

sys/dev/drm/radeon/rv515.c

750

WREG32(index_reg, 0x501);

sys/dev/drm/radeon/rv515.c

751

WREG32(data_reg, 0x85408640);

sys/dev/drm/radeon/rv515.c

752

WREG32(index_reg, 0x502);

sys/dev/drm/radeon/rv515.c

753

WREG32(data_reg, 0xBFF88180);

sys/dev/drm/radeon/rv515.c

754

WREG32(index_reg, 0x600);

sys/dev/drm/radeon/rv515.c

755

WREG32(data_reg, 0x82A08018);

sys/dev/drm/radeon/rv515.c

756

WREG32(index_reg, 0x601);

sys/dev/drm/radeon/rv515.c

757

WREG32(data_reg, 0x85808620);

sys/dev/drm/radeon/rv515.c

758

WREG32(index_reg, 0x602);

sys/dev/drm/radeon/rv515.c

759

WREG32(data_reg, 0xBFF081B8);

sys/dev/drm/radeon/rv515.c

760

WREG32(index_reg, 0x700);

sys/dev/drm/radeon/rv515.c

761

WREG32(data_reg, 0x82608010);

sys/dev/drm/radeon/rv515.c

762

WREG32(index_reg, 0x701);

sys/dev/drm/radeon/rv515.c

763

WREG32(data_reg, 0x85A08600);

sys/dev/drm/radeon/rv515.c

764

WREG32(index_reg, 0x702);

sys/dev/drm/radeon/rv515.c

765

WREG32(data_reg, 0x800081F0);

sys/dev/drm/radeon/rv515.c

766

WREG32(index_reg, 0x800);

sys/dev/drm/radeon/rv515.c

767

WREG32(data_reg, 0x8228BFF8);

sys/dev/drm/radeon/rv515.c

768

WREG32(index_reg, 0x801);

sys/dev/drm/radeon/rv515.c

769

WREG32(data_reg, 0x85E085E0);

sys/dev/drm/radeon/rv515.c

770

WREG32(index_reg, 0x802);

sys/dev/drm/radeon/rv515.c

771

WREG32(data_reg, 0xBFF88228);

sys/dev/drm/radeon/rv515.c

772

WREG32(index_reg, 0x10000);

sys/dev/drm/radeon/rv515.c

773

WREG32(data_reg, 0x82A8BF00);

sys/dev/drm/radeon/rv515.c

774

WREG32(index_reg, 0x10001);

sys/dev/drm/radeon/rv515.c

775

WREG32(data_reg, 0x82A08CC0);

sys/dev/drm/radeon/rv515.c

776

WREG32(index_reg, 0x10002);

sys/dev/drm/radeon/rv515.c

777

WREG32(data_reg, 0x8008BEF8);

sys/dev/drm/radeon/rv515.c

778

WREG32(index_reg, 0x10100);

sys/dev/drm/radeon/rv515.c

779

WREG32(data_reg, 0x81F0BF28);

sys/dev/drm/radeon/rv515.c

780

WREG32(index_reg, 0x10101);

sys/dev/drm/radeon/rv515.c

781

WREG32(data_reg, 0x83608CA0);

sys/dev/drm/radeon/rv515.c

782

WREG32(index_reg, 0x10102);

sys/dev/drm/radeon/rv515.c

783

WREG32(data_reg, 0x8018BED0);

sys/dev/drm/radeon/rv515.c

784

WREG32(index_reg, 0x10200);

sys/dev/drm/radeon/rv515.c

785

WREG32(data_reg, 0x8148BF38);

sys/dev/drm/radeon/rv515.c

786

WREG32(index_reg, 0x10201);

sys/dev/drm/radeon/rv515.c

787

WREG32(data_reg, 0x84408C80);

sys/dev/drm/radeon/rv515.c

788

WREG32(index_reg, 0x10202);

sys/dev/drm/radeon/rv515.c

789

WREG32(data_reg, 0x8008BEB8);

sys/dev/drm/radeon/rv515.c

790

WREG32(index_reg, 0x10300);

sys/dev/drm/radeon/rv515.c

791

WREG32(data_reg, 0x80B0BF78);

sys/dev/drm/radeon/rv515.c

792

WREG32(index_reg, 0x10301);

sys/dev/drm/radeon/rv515.c

793

WREG32(data_reg, 0x85008C20);

sys/dev/drm/radeon/rv515.c

794

WREG32(index_reg, 0x10302);

sys/dev/drm/radeon/rv515.c

795

WREG32(data_reg, 0x8020BEA0);

sys/dev/drm/radeon/rv515.c

796

WREG32(index_reg, 0x10400);

sys/dev/drm/radeon/rv515.c

797

WREG32(data_reg, 0x8028BF90);

sys/dev/drm/radeon/rv515.c

798

WREG32(index_reg, 0x10401);

sys/dev/drm/radeon/rv515.c

799

WREG32(data_reg, 0x85E08BC0);

sys/dev/drm/radeon/rv515.c

800

WREG32(index_reg, 0x10402);

sys/dev/drm/radeon/rv515.c

801

WREG32(data_reg, 0x8018BE90);

sys/dev/drm/radeon/rv515.c

802

WREG32(index_reg, 0x10500);

sys/dev/drm/radeon/rv515.c

803

WREG32(data_reg, 0xBFB8BFB0);

sys/dev/drm/radeon/rv515.c

804

WREG32(index_reg, 0x10501);

sys/dev/drm/radeon/rv515.c

805

WREG32(data_reg, 0x86C08B40);

sys/dev/drm/radeon/rv515.c

806

WREG32(index_reg, 0x10502);

sys/dev/drm/radeon/rv515.c

807

WREG32(data_reg, 0x8010BE90);

sys/dev/drm/radeon/rv515.c

808

WREG32(index_reg, 0x10600);

sys/dev/drm/radeon/rv515.c

809

WREG32(data_reg, 0xBF58BFC8);

sys/dev/drm/radeon/rv515.c

810

WREG32(index_reg, 0x10601);

sys/dev/drm/radeon/rv515.c

811

WREG32(data_reg, 0x87A08AA0);

sys/dev/drm/radeon/rv515.c

812

WREG32(index_reg, 0x10602);

sys/dev/drm/radeon/rv515.c

813

WREG32(data_reg, 0x8010BE98);

sys/dev/drm/radeon/rv515.c

814

WREG32(index_reg, 0x10700);

sys/dev/drm/radeon/rv515.c

815

WREG32(data_reg, 0xBF10BFF0);

sys/dev/drm/radeon/rv515.c

816

WREG32(index_reg, 0x10701);

sys/dev/drm/radeon/rv515.c

817

WREG32(data_reg, 0x886089E0);

sys/dev/drm/radeon/rv515.c

818

WREG32(index_reg, 0x10702);

sys/dev/drm/radeon/rv515.c

819

WREG32(data_reg, 0x8018BEB0);

sys/dev/drm/radeon/rv515.c

820

WREG32(index_reg, 0x10800);

sys/dev/drm/radeon/rv515.c

821

WREG32(data_reg, 0xBED8BFE8);

sys/dev/drm/radeon/rv515.c

822

WREG32(index_reg, 0x10801);

sys/dev/drm/radeon/rv515.c

823

WREG32(data_reg, 0x89408940);

sys/dev/drm/radeon/rv515.c

824

WREG32(index_reg, 0x10802);

sys/dev/drm/radeon/rv515.c

825

WREG32(data_reg, 0xBFE8BED8);

sys/dev/drm/radeon/rv515.c

826

WREG32(index_reg, 0x20000);

sys/dev/drm/radeon/rv515.c

827

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

828

WREG32(index_reg, 0x20001);

sys/dev/drm/radeon/rv515.c

829

WREG32(data_reg, 0x90008000);

sys/dev/drm/radeon/rv515.c

830

WREG32(index_reg, 0x20002);

sys/dev/drm/radeon/rv515.c

831

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

832

WREG32(index_reg, 0x20003);

sys/dev/drm/radeon/rv515.c

833

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

834

WREG32(index_reg, 0x20100);

sys/dev/drm/radeon/rv515.c

835

WREG32(data_reg, 0x80108000);

sys/dev/drm/radeon/rv515.c

836

WREG32(index_reg, 0x20101);

sys/dev/drm/radeon/rv515.c

837

WREG32(data_reg, 0x8FE0BF70);

sys/dev/drm/radeon/rv515.c

838

WREG32(index_reg, 0x20102);

sys/dev/drm/radeon/rv515.c

839

WREG32(data_reg, 0xBFE880C0);

sys/dev/drm/radeon/rv515.c

840

WREG32(index_reg, 0x20103);

sys/dev/drm/radeon/rv515.c

841

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

842

WREG32(index_reg, 0x20200);

sys/dev/drm/radeon/rv515.c

843

WREG32(data_reg, 0x8018BFF8);

sys/dev/drm/radeon/rv515.c

844

WREG32(index_reg, 0x20201);

sys/dev/drm/radeon/rv515.c

845

WREG32(data_reg, 0x8F80BF08);

sys/dev/drm/radeon/rv515.c

846

WREG32(index_reg, 0x20202);

sys/dev/drm/radeon/rv515.c

847

WREG32(data_reg, 0xBFD081A0);

sys/dev/drm/radeon/rv515.c

848

WREG32(index_reg, 0x20203);

sys/dev/drm/radeon/rv515.c

849

WREG32(data_reg, 0xBFF88000);

sys/dev/drm/radeon/rv515.c

850

WREG32(index_reg, 0x20300);

sys/dev/drm/radeon/rv515.c

851

WREG32(data_reg, 0x80188000);

sys/dev/drm/radeon/rv515.c

852

WREG32(index_reg, 0x20301);

sys/dev/drm/radeon/rv515.c

853

WREG32(data_reg, 0x8EE0BEC0);

sys/dev/drm/radeon/rv515.c

854

WREG32(index_reg, 0x20302);

sys/dev/drm/radeon/rv515.c

855

WREG32(data_reg, 0xBFB082A0);

sys/dev/drm/radeon/rv515.c

856

WREG32(index_reg, 0x20303);

sys/dev/drm/radeon/rv515.c

857

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

858

WREG32(index_reg, 0x20400);

sys/dev/drm/radeon/rv515.c

859

WREG32(data_reg, 0x80188000);

sys/dev/drm/radeon/rv515.c

860

WREG32(index_reg, 0x20401);

sys/dev/drm/radeon/rv515.c

861

WREG32(data_reg, 0x8E00BEA0);

sys/dev/drm/radeon/rv515.c

862

WREG32(index_reg, 0x20402);

sys/dev/drm/radeon/rv515.c

863

WREG32(data_reg, 0xBF8883C0);

sys/dev/drm/radeon/rv515.c

864

WREG32(index_reg, 0x20403);

sys/dev/drm/radeon/rv515.c

865

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

866

WREG32(index_reg, 0x20500);

sys/dev/drm/radeon/rv515.c

867

WREG32(data_reg, 0x80188000);

sys/dev/drm/radeon/rv515.c

868

WREG32(index_reg, 0x20501);

sys/dev/drm/radeon/rv515.c

869

WREG32(data_reg, 0x8D00BE90);

sys/dev/drm/radeon/rv515.c

870

WREG32(index_reg, 0x20502);

sys/dev/drm/radeon/rv515.c

871

WREG32(data_reg, 0xBF588500);

sys/dev/drm/radeon/rv515.c

872

WREG32(index_reg, 0x20503);

sys/dev/drm/radeon/rv515.c

873

WREG32(data_reg, 0x80008008);

sys/dev/drm/radeon/rv515.c

874

WREG32(index_reg, 0x20600);

sys/dev/drm/radeon/rv515.c

875

WREG32(data_reg, 0x80188000);

sys/dev/drm/radeon/rv515.c

876

WREG32(index_reg, 0x20601);

sys/dev/drm/radeon/rv515.c

877

WREG32(data_reg, 0x8BC0BE98);

sys/dev/drm/radeon/rv515.c

878

WREG32(index_reg, 0x20602);

sys/dev/drm/radeon/rv515.c

879

WREG32(data_reg, 0xBF308660);

sys/dev/drm/radeon/rv515.c

880

WREG32(index_reg, 0x20603);

sys/dev/drm/radeon/rv515.c

881

WREG32(data_reg, 0x80008008);

sys/dev/drm/radeon/rv515.c

882

WREG32(index_reg, 0x20700);

sys/dev/drm/radeon/rv515.c

883

WREG32(data_reg, 0x80108000);

sys/dev/drm/radeon/rv515.c

884

WREG32(index_reg, 0x20701);

sys/dev/drm/radeon/rv515.c

885

WREG32(data_reg, 0x8A80BEB0);

sys/dev/drm/radeon/rv515.c

886

WREG32(index_reg, 0x20702);

sys/dev/drm/radeon/rv515.c

887

WREG32(data_reg, 0xBF0087C0);

sys/dev/drm/radeon/rv515.c

888

WREG32(index_reg, 0x20703);

sys/dev/drm/radeon/rv515.c

889

WREG32(data_reg, 0x80008008);

sys/dev/drm/radeon/rv515.c

890

WREG32(index_reg, 0x20800);

sys/dev/drm/radeon/rv515.c

891

WREG32(data_reg, 0x80108000);

sys/dev/drm/radeon/rv515.c

892

WREG32(index_reg, 0x20801);

sys/dev/drm/radeon/rv515.c

893

WREG32(data_reg, 0x8920BED0);

sys/dev/drm/radeon/rv515.c

894

WREG32(index_reg, 0x20802);

sys/dev/drm/radeon/rv515.c

895

WREG32(data_reg, 0xBED08920);

sys/dev/drm/radeon/rv515.c

896

WREG32(index_reg, 0x20803);

sys/dev/drm/radeon/rv515.c

897

WREG32(data_reg, 0x80008010);

sys/dev/drm/radeon/rv515.c

898

WREG32(index_reg, 0x30000);

sys/dev/drm/radeon/rv515.c

899

WREG32(data_reg, 0x90008000);

sys/dev/drm/radeon/rv515.c

900

WREG32(index_reg, 0x30001);

sys/dev/drm/radeon/rv515.c

901

WREG32(data_reg, 0x80008000);

sys/dev/drm/radeon/rv515.c

902

WREG32(index_reg, 0x30100);

sys/dev/drm/radeon/rv515.c

903

WREG32(data_reg, 0x8FE0BF90);

sys/dev/drm/radeon/rv515.c

904

WREG32(index_reg, 0x30101);

sys/dev/drm/radeon/rv515.c

905

WREG32(data_reg, 0xBFF880A0);

sys/dev/drm/radeon/rv515.c

906

WREG32(index_reg, 0x30200);

sys/dev/drm/radeon/rv515.c

907

WREG32(data_reg, 0x8F60BF40);

sys/dev/drm/radeon/rv515.c

908

WREG32(index_reg, 0x30201);

sys/dev/drm/radeon/rv515.c

909

WREG32(data_reg, 0xBFE88180);

sys/dev/drm/radeon/rv515.c

910

WREG32(index_reg, 0x30300);

sys/dev/drm/radeon/rv515.c

911

WREG32(data_reg, 0x8EC0BF00);

sys/dev/drm/radeon/rv515.c

912

WREG32(index_reg, 0x30301);

sys/dev/drm/radeon/rv515.c

913

WREG32(data_reg, 0xBFC88280);

sys/dev/drm/radeon/rv515.c

914

WREG32(index_reg, 0x30400);

sys/dev/drm/radeon/rv515.c

915

WREG32(data_reg, 0x8DE0BEE0);

sys/dev/drm/radeon/rv515.c

916

WREG32(index_reg, 0x30401);

sys/dev/drm/radeon/rv515.c

917

WREG32(data_reg, 0xBFA083A0);

sys/dev/drm/radeon/rv515.c

918

WREG32(index_reg, 0x30500);

sys/dev/drm/radeon/rv515.c

919

WREG32(data_reg, 0x8CE0BED0);

sys/dev/drm/radeon/rv515.c

920

WREG32(index_reg, 0x30501);

sys/dev/drm/radeon/rv515.c

921

WREG32(data_reg, 0xBF7884E0);

sys/dev/drm/radeon/rv515.c

922

WREG32(index_reg, 0x30600);

sys/dev/drm/radeon/rv515.c

923

WREG32(data_reg, 0x8BA0BED8);

sys/dev/drm/radeon/rv515.c

924

WREG32(index_reg, 0x30601);

sys/dev/drm/radeon/rv515.c

925

WREG32(data_reg, 0xBF508640);

sys/dev/drm/radeon/rv515.c

926

WREG32(index_reg, 0x30700);

sys/dev/drm/radeon/rv515.c

927

WREG32(data_reg, 0x8A60BEE8);

sys/dev/drm/radeon/rv515.c

928

WREG32(index_reg, 0x30701);

sys/dev/drm/radeon/rv515.c

929

WREG32(data_reg, 0xBF2087A0);

sys/dev/drm/radeon/rv515.c

930

WREG32(index_reg, 0x30800);

sys/dev/drm/radeon/rv515.c

931

WREG32(data_reg, 0x8900BF00);

sys/dev/drm/radeon/rv515.c

932

WREG32(index_reg, 0x30801);

sys/dev/drm/radeon/rv515.c

933

WREG32(data_reg, 0xBF008900);

sys/dev/drm/radeon/rv6xx_dpm.c

1196

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv6xx_dpm.c

815

WREG32(SQM_RATIO, sqm_ratio);

sys/dev/drm/radeon/rv6xx_dpm.c

826

WREG32(ARB_RFSH_RATE, arb_refresh_rate);

sys/dev/drm/radeon/rv6xx_dpm.c

990

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv730_dpm.c

409

WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);

sys/dev/drm/radeon/rv730_dpm.c

422

WREG32(MC_ARB_DRAM_TIMING_3, dram_timing);

sys/dev/drm/radeon/rv730_dpm.c

423

WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2);

sys/dev/drm/radeon/rv730_dpm.c

432

WREG32(MC_ARB_DRAM_TIMING_2, dram_timing);

sys/dev/drm/radeon/rv730_dpm.c

433

WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2);

sys/dev/drm/radeon/rv730_dpm.c

442

WREG32(MC_ARB_DRAM_TIMING_1, dram_timing);

sys/dev/drm/radeon/rv730_dpm.c

443

WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2);

sys/dev/drm/radeon/rv730_dpm.c

446

WREG32(MC_ARB_DRAM_TIMING, old_dram_timing);

sys/dev/drm/radeon/rv730_dpm.c

447

WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2);

sys/dev/drm/radeon/rv730_dpm.c

485

WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl);

sys/dev/drm/radeon/rv730_dpm.c

486

WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl);

sys/dev/drm/radeon/rv730_dpm.c

491

WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl);

sys/dev/drm/radeon/rv730_dpm.c

492

WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl);

sys/dev/drm/radeon/rv770.c

1009

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1010

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1011

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1012

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1013

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1025

WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);

sys/dev/drm/radeon/rv770.c

1030

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/rv770.c

1032

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/rv770.c

1036

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/rv770.c

1038

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/rv770.c

1042

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/rv770.c

1044

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/rv770.c

1047

WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);

sys/dev/drm/radeon/rv770.c

1050

WREG32(MC_VM_FB_LOCATION, tmp);

sys/dev/drm/radeon/rv770.c

1051

WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

sys/dev/drm/radeon/rv770.c

1052

WREG32(HDP_NONSURFACE_INFO, (2 << 7));

sys/dev/drm/radeon/rv770.c

1053

WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

sys/dev/drm/radeon/rv770.c

1055

WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);

sys/dev/drm/radeon/rv770.c

1056

WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);

sys/dev/drm/radeon/rv770.c

1057

WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);

sys/dev/drm/radeon/rv770.c

1059

WREG32(MC_VM_AGP_BASE, 0);

sys/dev/drm/radeon/rv770.c

1060

WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/radeon/rv770.c

1061

WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/radeon/rv770.c

1080

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));

sys/dev/drm/radeon/rv770.c

1081

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/rv770.c

1094

WREG32(CP_RB_CNTL,

sys/dev/drm/radeon/rv770.c

1101

WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);

sys/dev/drm/radeon/rv770.c

1104

WREG32(GRBM_SOFT_RESET, 0);

sys/dev/drm/radeon/rv770.c

1107

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/rv770.c

1109

WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/rv770.c

1110

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/rv770.c

1113

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/rv770.c

1115

WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/rv770.c

1117

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/rv770.c

1118

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/rv770.c

1119

WREG32(CP_ME_RAM_RADDR, 0);

sys/dev/drm/radeon/rv770.c

1141

WREG32(CG_SPLL_FUNC_CNTL_2, tmp);

sys/dev/drm/radeon/rv770.c

1150

WREG32(CG_SPLL_FUNC_CNTL_2, tmp);

sys/dev/drm/radeon/rv770.c

1157

WREG32(MPLL_CNTL_MODE, tmp);

sys/dev/drm/radeon/rv770.c

1285

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1286

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1287

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1288

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1289

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/rv770.c

1293

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

sys/dev/drm/radeon/rv770.c

1307

WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);

sys/dev/drm/radeon/rv770.c

1309

WREG32(SPI_CONFIG_CNTL, 0);

sys/dev/drm/radeon/rv770.c

1372

WREG32(GB_TILING_CONFIG, gb_tiling_config);

sys/dev/drm/radeon/rv770.c

1373

WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1374

WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1375

WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1376

WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1378

WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1379

WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1380

WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));

sys/dev/drm/radeon/rv770.c

1383

WREG32(CGTS_SYS_TCC_DISABLE, 0);

sys/dev/drm/radeon/rv770.c

1384

WREG32(CGTS_TCC_DISABLE, 0);

sys/dev/drm/radeon/rv770.c

1385

WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);

sys/dev/drm/radeon/rv770.c

1386

WREG32(CGTS_USER_TCC_DISABLE, 0);

sys/dev/drm/radeon/rv770.c

1390

WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);

sys/dev/drm/radeon/rv770.c

1391

WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);

sys/dev/drm/radeon/rv770.c

1394

WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |

sys/dev/drm/radeon/rv770.c

1397

WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));

sys/dev/drm/radeon/rv770.c

1400

WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);

sys/dev/drm/radeon/rv770.c

1404

WREG32(SX_DEBUG_1, sx_debug_1);

sys/dev/drm/radeon/rv770.c

1409

WREG32(SMX_DC_CTL0, smx_dc_ctl0);

sys/dev/drm/radeon/rv770.c

1412

WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |

sys/dev/drm/radeon/rv770.c

1418

WREG32(SMX_SAR_CTL0, 0x00003f3f);

sys/dev/drm/radeon/rv770.c

1433

WREG32(DB_DEBUG3, db_debug3);

sys/dev/drm/radeon/rv770.c

1438

WREG32(DB_DEBUG4, db_debug4);

sys/dev/drm/radeon/rv770.c

1441

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |

sys/dev/drm/radeon/rv770.c

1445

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |

sys/dev/drm/radeon/rv770.c

1449

WREG32(PA_SC_MULTI_CHIP_CNTL, 0);

sys/dev/drm/radeon/rv770.c

1451

WREG32(VGT_NUM_INSTANCES, 1);

sys/dev/drm/radeon/rv770.c

1453

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));

sys/dev/drm/radeon/rv770.c

1455

WREG32(CP_PERFMON_CNTL, 0);

sys/dev/drm/radeon/rv770.c

1471

WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);

sys/dev/drm/radeon/rv770.c

1492

WREG32(SQ_CONFIG, sq_config);

sys/dev/drm/radeon/rv770.c

1494

WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |

sys/dev/drm/radeon/rv770.c

1498

WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |

sys/dev/drm/radeon/rv770.c

1508

WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);

sys/dev/drm/radeon/rv770.c

1510

WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |

sys/dev/drm/radeon/rv770.c

1513

WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |

sys/dev/drm/radeon/rv770.c

1521

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1522

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1523

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1524

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1525

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1526

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1527

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1528

WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);

sys/dev/drm/radeon/rv770.c

1530

WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |

sys/dev/drm/radeon/rv770.c

1534

WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |

sys/dev/drm/radeon/rv770.c

1537

WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |

sys/dev/drm/radeon/rv770.c

1559

WREG32(VGT_ES_PER_GS, 128);

sys/dev/drm/radeon/rv770.c

1560

WREG32(VGT_GS_PER_ES, vgt_gs_per_es);

sys/dev/drm/radeon/rv770.c

1561

WREG32(VGT_GS_PER_VS, 2);

sys/dev/drm/radeon/rv770.c

1564

WREG32(VGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/radeon/rv770.c

1565

WREG32(PA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/radeon/rv770.c

1566

WREG32(VGT_STRMOUT_EN, 0);

sys/dev/drm/radeon/rv770.c

1567

WREG32(SX_MISC, 0);

sys/dev/drm/radeon/rv770.c

1568

WREG32(PA_SC_MODE_CNTL, 0);

sys/dev/drm/radeon/rv770.c

1569

WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);

sys/dev/drm/radeon/rv770.c

1570

WREG32(PA_SC_AA_CONFIG, 0);

sys/dev/drm/radeon/rv770.c

1571

WREG32(PA_SC_CLIPRECT_RULE, 0xffff);

sys/dev/drm/radeon/rv770.c

1572

WREG32(PA_SC_LINE_STIPPLE, 0);

sys/dev/drm/radeon/rv770.c

1573

WREG32(SPI_INPUT_Z, 0);

sys/dev/drm/radeon/rv770.c

1574

WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));

sys/dev/drm/radeon/rv770.c

1575

WREG32(CB_COLOR7_FRAG, 0);

sys/dev/drm/radeon/rv770.c

1578

WREG32(CB_COLOR0_BASE, 0);

sys/dev/drm/radeon/rv770.c

1579

WREG32(CB_COLOR1_BASE, 0);

sys/dev/drm/radeon/rv770.c

1580

WREG32(CB_COLOR2_BASE, 0);

sys/dev/drm/radeon/rv770.c

1581

WREG32(CB_COLOR3_BASE, 0);

sys/dev/drm/radeon/rv770.c

1582

WREG32(CB_COLOR4_BASE, 0);

sys/dev/drm/radeon/rv770.c

1583

WREG32(CB_COLOR5_BASE, 0);

sys/dev/drm/radeon/rv770.c

1584

WREG32(CB_COLOR6_BASE, 0);

sys/dev/drm/radeon/rv770.c

1585

WREG32(CB_COLOR7_BASE, 0);

sys/dev/drm/radeon/rv770.c

1587

WREG32(TCP_CNTL, 0);

sys/dev/drm/radeon/rv770.c

1590

WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);

sys/dev/drm/radeon/rv770.c

1592

WREG32(PA_SC_MULTI_CHIP_CNTL, 0);

sys/dev/drm/radeon/rv770.c

1594

WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |

sys/dev/drm/radeon/rv770.c

1596

WREG32(VC_ENHANCE, 0);

sys/dev/drm/radeon/rv770.c

2065

WREG32(0x541c, tmp | 0x8);

sys/dev/drm/radeon/rv770.c

2066

WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);

sys/dev/drm/radeon/rv770.c

2071

WREG32(MM_CFGREGS_CNTL, 0);

sys/dev/drm/radeon/rv770.c

809

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rv770.c

812

WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rv770.c

815

WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

816

WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

818

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

819

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));

sys/dev/drm/radeon/rv770.c

821

WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rv770.c

823

WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/rv770.c

836

WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/rv770.c

903

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/rv770.c

906

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/rv770.c

907

WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

sys/dev/drm/radeon/rv770.c

913

WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

914

WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

915

WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

917

WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

918

WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

919

WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

920

WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

921

WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

922

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/rv770.c

923

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

sys/dev/drm/radeon/rv770.c

924

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

sys/dev/drm/radeon/rv770.c

925

WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

sys/dev/drm/radeon/rv770.c

927

WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/rv770.c

930

WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

sys/dev/drm/radeon/rv770.c

947

WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

sys/dev/drm/radeon/rv770.c

950

WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/rv770.c

952

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/rv770.c

953

WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

sys/dev/drm/radeon/rv770.c

956

WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

957

WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

958

WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

959

WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

960

WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

961

WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

962

WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

980

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |

sys/dev/drm/radeon/rv770.c

983

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/rv770.c

984

WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));

sys/dev/drm/radeon/rv770.c

990

WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

991

WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

992

WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

993

WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

994

WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

995

WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

996

WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);

sys/dev/drm/radeon/rv770.c

998

WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);

sys/dev/drm/radeon/rv770_dpm.c

1361

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv770_dpm.c

1590

WREG32(S0_VID_LOWER_SMIO_CNTL, vid_smio_cntl);

sys/dev/drm/radeon/rv770_dpm.c

160

WREG32(CG_CGTT_LOCAL_0, mgcg_cgtt_local0);

sys/dev/drm/radeon/rv770_dpm.c

161

WREG32(CG_CGTT_LOCAL_1, (RV770_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF));

sys/dev/drm/radeon/rv770_dpm.c

164

WREG32(CGTS_SM_CTRL_REG, RV770_MGCGCGTSSMCTRL_DFLT);

sys/dev/drm/radeon/rv770_dpm.c

166

WREG32(CG_CGTT_LOCAL_0, 0xFFFFFFFF);

sys/dev/drm/radeon/rv770_dpm.c

167

WREG32(CG_CGTT_LOCAL_1, 0xFFFFCFFF);

sys/dev/drm/radeon/rv770_dpm.c

765

WREG32(MC_ARB_SQM_RATIO, sqm_ratio);

sys/dev/drm/radeon/rv770_dpm.c

772

WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate);

sys/dev/drm/radeon/rv770_dpm.c

814

WREG32(MPLL_TIME,

sys/dev/drm/radeon/rv770_dpm.c

840

WREG32(CG_BSP, pi->dsp);

sys/dev/drm/radeon/rv770_dpm.c

855

WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));

sys/dev/drm/radeon/rv770_dpm.c

869

WREG32(CG_TPC, R600_TPC_DFLT);

sys/dev/drm/radeon/rv770_dpm.c

874

WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));

sys/dev/drm/radeon/rv770_dpm.c

889

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/rv770_dpm.c

896

WREG32(CG_FTV, pi->vrc);

sys/dev/drm/radeon/rv770_dpm.c

901

WREG32(CG_FTV, 0);

sys/dev/drm/radeon/rv770_smc.c

290

WREG32(SMC_SRAM_ADDR, addr);

sys/dev/drm/radeon/rv770_smc.c

320

WREG32(SMC_SRAM_DATA, data);

sys/dev/drm/radeon/rv770_smc.c

353

WREG32(SMC_SRAM_DATA, data);

sys/dev/drm/radeon/rv770_smc.c

386

WREG32(SMC_ISR_FFD8_FFDB + i, tmp);

sys/dev/drm/radeon/rv770_smc.c

475

WREG32(SMC_SRAM_DATA, 0);

sys/dev/drm/radeon/rv770_smc.c

627

WREG32(SMC_SRAM_DATA, value);

sys/dev/drm/radeon/si.c

1618

WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/radeon/si.c

1619

WREG32(MC_SEQ_SUP_CNTL, 0x00000010);

sys/dev/drm/radeon/si.c

1624

WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));

sys/dev/drm/radeon/si.c

1625

WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));

sys/dev/drm/radeon/si.c

1627

WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);

sys/dev/drm/radeon/si.c

1628

WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);

sys/dev/drm/radeon/si.c

1634

WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));

sys/dev/drm/radeon/si.c

1636

WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

1640

WREG32(MC_SEQ_SUP_CNTL, 0x00000008);

sys/dev/drm/radeon/si.c

1641

WREG32(MC_SEQ_SUP_CNTL, 0x00000004);

sys/dev/drm/radeon/si.c

1642

WREG32(MC_SEQ_SUP_CNTL, 0x00000001);

sys/dev/drm/radeon/si.c

1990

WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/si.c

1993

WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,

sys/dev/drm/radeon/si.c

2425

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/si.c

2426

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/si.c

2433

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp);

sys/dev/drm/radeon/si.c

2434

WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,

sys/dev/drm/radeon/si.c

2438

WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3);

sys/dev/drm/radeon/si.c

2441

WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);

sys/dev/drm/radeon/si.c

2442

WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);

sys/dev/drm/radeon/si.c

2714

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

sys/dev/drm/radeon/si.c

2929

WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);

sys/dev/drm/radeon/si.c

2950

WREG32(GRBM_GFX_INDEX, data);

sys/dev/drm/radeon/si.c

3000

WREG32(SPI_STATIC_THREAD_MGMT_3, data);

sys/dev/drm/radeon/si.c

3074

WREG32(PA_SC_RASTER_CONFIG, data);

sys/dev/drm/radeon/si.c

3179

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/si.c

3180

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/si.c

3181

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/si.c

3182

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/si.c

3183

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/si.c

3186

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));

sys/dev/drm/radeon/si.c

3187

WREG32(SRBM_INT_CNTL, 1);

sys/dev/drm/radeon/si.c

3188

WREG32(SRBM_INT_ACK, 1);

sys/dev/drm/radeon/si.c

3192

WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);

sys/dev/drm/radeon/si.c

3264

WREG32(GB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3265

WREG32(DMIF_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3266

WREG32(DMIF_ADDR_CALC, gb_addr_config);

sys/dev/drm/radeon/si.c

3267

WREG32(HDP_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3268

WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/si.c

3269

WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);

sys/dev/drm/radeon/si.c

3271

WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3272

WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3273

WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);

sys/dev/drm/radeon/si.c

3295

WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |

sys/dev/drm/radeon/si.c

3297

WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));

sys/dev/drm/radeon/si.c

3300

WREG32(SX_DEBUG_1, sx_debug_1);

sys/dev/drm/radeon/si.c

3302

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));

sys/dev/drm/radeon/si.c

3304

WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) |

sys/dev/drm/radeon/si.c

3309

WREG32(VGT_NUM_INSTANCES, 1);

sys/dev/drm/radeon/si.c

3311

WREG32(CP_PERFMON_CNTL, 0);

sys/dev/drm/radeon/si.c

3313

WREG32(SQ_CONFIG, 0);

sys/dev/drm/radeon/si.c

3315

WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |

sys/dev/drm/radeon/si.c

3318

WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |

sys/dev/drm/radeon/si.c

3321

WREG32(VGT_GS_VERTEX_REUSE, 16);

sys/dev/drm/radeon/si.c

3322

WREG32(PA_SC_LINE_STIPPLE_STATE, 0);

sys/dev/drm/radeon/si.c

3324

WREG32(CB_PERFCOUNTER0_SELECT0, 0);

sys/dev/drm/radeon/si.c

3325

WREG32(CB_PERFCOUNTER0_SELECT1, 0);

sys/dev/drm/radeon/si.c

3326

WREG32(CB_PERFCOUNTER1_SELECT0, 0);

sys/dev/drm/radeon/si.c

3327

WREG32(CB_PERFCOUNTER1_SELECT1, 0);

sys/dev/drm/radeon/si.c

3328

WREG32(CB_PERFCOUNTER2_SELECT0, 0);

sys/dev/drm/radeon/si.c

3329

WREG32(CB_PERFCOUNTER2_SELECT1, 0);

sys/dev/drm/radeon/si.c

3330

WREG32(CB_PERFCOUNTER3_SELECT0, 0);

sys/dev/drm/radeon/si.c

3331

WREG32(CB_PERFCOUNTER3_SELECT1, 0);

sys/dev/drm/radeon/si.c

3335

WREG32(HDP_MISC_CNTL, tmp);

sys/dev/drm/radeon/si.c

3338

WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);

sys/dev/drm/radeon/si.c

3340

WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));

sys/dev/drm/radeon/si.c

3453

WREG32(CP_ME_CNTL, 0);

sys/dev/drm/radeon/si.c

3457

WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));

sys/dev/drm/radeon/si.c

3458

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/si.c

3493

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3495

WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

3496

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3502

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3504

WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

3505

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3511

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/si.c

3513

WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

3514

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/si.c

3520

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3522

WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

3523

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3527

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3529

WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

3530

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3534

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/si.c

3536

WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

3537

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/si.c

3540

WREG32(CP_PFP_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3541

WREG32(CP_CE_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

3542

WREG32(CP_ME_RAM_WADDR, 0);

sys/dev/drm/radeon/si.c

3543

WREG32(CP_ME_RAM_RADDR, 0);

sys/dev/drm/radeon/si.c

3643

WREG32(CP_SEM_WAIT_TIMER, 0x0);

sys/dev/drm/radeon/si.c

3644

WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);

sys/dev/drm/radeon/si.c

3647

WREG32(CP_RB_WPTR_DELAY, 0);

sys/dev/drm/radeon/si.c

3649

WREG32(CP_DEBUG, 0);

sys/dev/drm/radeon/si.c

3650

WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);

sys/dev/drm/radeon/si.c

3660

WREG32(CP_RB0_CNTL, tmp);

sys/dev/drm/radeon/si.c

3663

WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);

sys/dev/drm/radeon/si.c

3665

WREG32(CP_RB0_WPTR, ring->wptr);

sys/dev/drm/radeon/si.c

3668

WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/si.c

3669

WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

3672

WREG32(SCRATCH_UMSK, 0xff);

sys/dev/drm/radeon/si.c

3675

WREG32(SCRATCH_UMSK, 0);

sys/dev/drm/radeon/si.c

3679

WREG32(CP_RB0_CNTL, tmp);

sys/dev/drm/radeon/si.c

3681

WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);

sys/dev/drm/radeon/si.c

3691

WREG32(CP_RB1_CNTL, tmp);

sys/dev/drm/radeon/si.c

3694

WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);

sys/dev/drm/radeon/si.c

3696

WREG32(CP_RB1_WPTR, ring->wptr);

sys/dev/drm/radeon/si.c

3699

WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/si.c

3700

WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

3703

WREG32(CP_RB1_CNTL, tmp);

sys/dev/drm/radeon/si.c

3705

WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);

sys/dev/drm/radeon/si.c

3715

WREG32(CP_RB2_CNTL, tmp);

sys/dev/drm/radeon/si.c

3718

WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);

sys/dev/drm/radeon/si.c

3720

WREG32(CP_RB2_WPTR, ring->wptr);

sys/dev/drm/radeon/si.c

3723

WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/si.c

3724

WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

3727

WREG32(CP_RB2_CNTL, tmp);

sys/dev/drm/radeon/si.c

3729

WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);

sys/dev/drm/radeon/si.c

3866

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/drm/radeon/si.c

3872

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

3878

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

3940

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/si.c

3946

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/si.c

3954

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/si.c

3960

WREG32(SRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/si.c

3979

WREG32(CG_SPLL_FUNC_CNTL, tmp);

sys/dev/drm/radeon/si.c

3983

WREG32(CG_SPLL_FUNC_CNTL_2, tmp);

sys/dev/drm/radeon/si.c

3993

WREG32(CG_SPLL_FUNC_CNTL_2, tmp);

sys/dev/drm/radeon/si.c

3997

WREG32(MPLL_CNTL_MODE, tmp);

sys/dev/drm/radeon/si.c

4006

WREG32(SPLL_CNTL_MODE, tmp);

sys/dev/drm/radeon/si.c

4010

WREG32(CG_SPLL_FUNC_CNTL, tmp);

sys/dev/drm/radeon/si.c

4014

WREG32(CG_SPLL_FUNC_CNTL, tmp);

sys/dev/drm/radeon/si.c

4018

WREG32(SPLL_CNTL_MODE, tmp);

sys/dev/drm/radeon/si.c

4035

WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);

sys/dev/drm/radeon/si.c

4039

WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

4043

WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

4135

WREG32((0x2c14 + j), 0x00000000);

sys/dev/drm/radeon/si.c

4136

WREG32((0x2c18 + j), 0x00000000);

sys/dev/drm/radeon/si.c

4137

WREG32((0x2c1c + j), 0x00000000);

sys/dev/drm/radeon/si.c

4138

WREG32((0x2c20 + j), 0x00000000);

sys/dev/drm/radeon/si.c

4139

WREG32((0x2c24 + j), 0x00000000);

sys/dev/drm/radeon/si.c

4141

WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);

sys/dev/drm/radeon/si.c

4149

WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);

sys/dev/drm/radeon/si.c

4151

WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,

sys/dev/drm/radeon/si.c

4153

WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

sys/dev/drm/radeon/si.c

4155

WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,

sys/dev/drm/radeon/si.c

4159

WREG32(MC_VM_FB_LOCATION, tmp);

sys/dev/drm/radeon/si.c

4161

WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));

sys/dev/drm/radeon/si.c

4162

WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));

sys/dev/drm/radeon/si.c

4163

WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

sys/dev/drm/radeon/si.c

4164

WREG32(MC_VM_AGP_BASE, 0);

sys/dev/drm/radeon/si.c

4165

WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);

sys/dev/drm/radeon/si.c

4166

WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);

sys/dev/drm/radeon/si.c

4265

WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);

sys/dev/drm/radeon/si.c

4268

WREG32(VM_INVALIDATE_REQUEST, 1);

sys/dev/drm/radeon/si.c

4283

WREG32(MC_VM_MX_L1_TLB_CNTL,

sys/dev/drm/radeon/si.c

4291

WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |

sys/dev/drm/radeon/si.c

4297

WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);

sys/dev/drm/radeon/si.c

4298

WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

sys/dev/drm/radeon/si.c

4302

WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);

sys/dev/drm/radeon/si.c

4303

WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);

sys/dev/drm/radeon/si.c

4304

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);

sys/dev/drm/radeon/si.c

4305

WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/si.c

4307

WREG32(VM_CONTEXT0_CNTL2, 0);

sys/dev/drm/radeon/si.c

4308

WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |

sys/dev/drm/radeon/si.c

4311

WREG32(0x15D4, 0);

sys/dev/drm/radeon/si.c

4312

WREG32(0x15D8, 0);

sys/dev/drm/radeon/si.c

4313

WREG32(0x15DC, 0);

sys/dev/drm/radeon/si.c

4317

WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);

sys/dev/drm/radeon/si.c

4318

WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1);

sys/dev/drm/radeon/si.c

4325

WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),

sys/dev/drm/radeon/si.c

4328

WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),

sys/dev/drm/radeon/si.c

4333

WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,

sys/dev/drm/radeon/si.c

4335

WREG32(VM_CONTEXT1_CNTL2, 4);

sys/dev/drm/radeon/si.c

4336

WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |

sys/dev/drm/radeon/si.c

4373

WREG32(VM_CONTEXT0_CNTL, 0);

sys/dev/drm/radeon/si.c

4374

WREG32(VM_CONTEXT1_CNTL, 0);

sys/dev/drm/radeon/si.c

4376

WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |

sys/dev/drm/radeon/si.c

4379

WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |

sys/dev/drm/radeon/si.c

4383

WREG32(VM_L2_CNTL2, 0);

sys/dev/drm/radeon/si.c

4384

WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |

sys/dev/drm/radeon/si.c

5142

WREG32(CP_INT_CNTL_RING0, tmp);

sys/dev/drm/radeon/si.c

5174

WREG32(UVD_CGC_CTRL, tmp);

sys/dev/drm/radeon/si.c

5187

WREG32(UVD_CGC_CTRL, tmp);

sys/dev/drm/radeon/si.c

5199

WREG32(RLC_CNTL, data);

sys/dev/drm/radeon/si.c

5213

WREG32(RLC_CNTL, rlc);

sys/dev/drm/radeon/si.c

5226

WREG32(DMA_PG, data);

sys/dev/drm/radeon/si.c

5233

WREG32(DMA_PGFSM_WRITE, 0x00002000);

sys/dev/drm/radeon/si.c

5234

WREG32(DMA_PGFSM_CONFIG, 0x100010ff);

sys/dev/drm/radeon/si.c

5237

WREG32(DMA_PGFSM_WRITE, 0);

sys/dev/drm/radeon/si.c

5247

WREG32(RLC_TTOP_D, tmp);

sys/dev/drm/radeon/si.c

5251

WREG32(RLC_PG_CNTL, tmp);

sys/dev/drm/radeon/si.c

5255

WREG32(RLC_AUTO_PG_CTRL, tmp);

sys/dev/drm/radeon/si.c

5259

WREG32(RLC_AUTO_PG_CTRL, tmp);

sys/dev/drm/radeon/si.c

5269

WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);

sys/dev/drm/radeon/si.c

5273

WREG32(RLC_PG_CNTL, tmp);

sys/dev/drm/radeon/si.c

5275

WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);

sys/dev/drm/radeon/si.c

5282

WREG32(RLC_AUTO_PG_CTRL, tmp);

sys/dev/drm/radeon/si.c

5333

WREG32(RLC_PG_AO_CU_MASK, tmp);

sys/dev/drm/radeon/si.c

5338

WREG32(RLC_MAX_PG_CU, tmp);

sys/dev/drm/radeon/si.c

5351

WREG32(RLC_GCPM_GENERAL_3, 0x00000080);

sys/dev/drm/radeon/si.c

5355

WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);

sys/dev/drm/radeon/si.c

5356

WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);

sys/dev/drm/radeon/si.c

5357

WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff);

sys/dev/drm/radeon/si.c

5363

WREG32(RLC_SERDES_WR_CTRL, 0x007000ff);

sys/dev/drm/radeon/si.c

5378

WREG32(RLC_CGCG_CGLS_CTRL, data);

sys/dev/drm/radeon/si.c

5390

WREG32(CGTS_SM_CTRL_REG, data);

sys/dev/drm/radeon/si.c

5396

WREG32(CP_MEM_SLP_CNTL, data);

sys/dev/drm/radeon/si.c

5402

WREG32(RLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/radeon/si.c

5406

WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);

sys/dev/drm/radeon/si.c

5407

WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);

sys/dev/drm/radeon/si.c

5408

WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff);

sys/dev/drm/radeon/si.c

5415

WREG32(RLC_CGTT_MGCG_OVERRIDE, data);

sys/dev/drm/radeon/si.c

5420

WREG32(CP_MEM_SLP_CNTL, data);

sys/dev/drm/radeon/si.c

5425

WREG32(CGTS_SM_CTRL_REG, data);

sys/dev/drm/radeon/si.c

5429

WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);

sys/dev/drm/radeon/si.c

5430

WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);

sys/dev/drm/radeon/si.c

5431

WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff);

sys/dev/drm/radeon/si.c

5450

WREG32(UVD_CGC_CTRL, data);

sys/dev/drm/radeon/si.c

5462

WREG32(UVD_CGC_CTRL, data);

sys/dev/drm/radeon/si.c

5495

WREG32(mc_cg_registers[i], data);

sys/dev/drm/radeon/si.c

5512

WREG32(mc_cg_registers[i], data);

sys/dev/drm/radeon/si.c

5531

WREG32(DMA_POWER_CNTL + offset, data);

sys/dev/drm/radeon/si.c

5532

WREG32(DMA_CLK_CTRL + offset, 0x00000100);

sys/dev/drm/radeon/si.c

5543

WREG32(DMA_POWER_CNTL + offset, data);

sys/dev/drm/radeon/si.c

5548

WREG32(DMA_CLK_CTRL + offset, data);

sys/dev/drm/radeon/si.c

5584

WREG32(HDP_HOST_PATH_CNTL, data);

sys/dev/drm/radeon/si.c

5600

WREG32(HDP_MEM_POWER_LS, data);

sys/dev/drm/radeon/si.c

5771

WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);

sys/dev/drm/radeon/si.c

5772

WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);

sys/dev/drm/radeon/si.c

5777

WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);

sys/dev/drm/radeon/si.c

5778

WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);

sys/dev/drm/radeon/si.c

5798

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/si.c

5801

WREG32(GRBM_SOFT_RESET, tmp);

sys/dev/drm/radeon/si.c

5807

WREG32(RLC_CNTL, 0);

sys/dev/drm/radeon/si.c

5816

WREG32(RLC_CNTL, RLC_ENABLE);

sys/dev/drm/radeon/si.c

5843

WREG32(RLC_LB_CNTL, tmp);

sys/dev/drm/radeon/si.c

5847

WREG32(SPI_LB_CU_MASK, 0x00ff);

sys/dev/drm/radeon/si.c

5866

WREG32(RLC_RL_BASE, 0);

sys/dev/drm/radeon/si.c

5867

WREG32(RLC_RL_SIZE, 0);

sys/dev/drm/radeon/si.c

5868

WREG32(RLC_LB_CNTL, 0);

sys/dev/drm/radeon/si.c

5869

WREG32(RLC_LB_CNTR_MAX, 0xffffffff);

sys/dev/drm/radeon/si.c

5870

WREG32(RLC_LB_CNTR_INIT, 0);

sys/dev/drm/radeon/si.c

5871

WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);

sys/dev/drm/radeon/si.c

5873

WREG32(RLC_MC_CNTL, 0);

sys/dev/drm/radeon/si.c

5874

WREG32(RLC_UCODE_CNTL, 0);

sys/dev/drm/radeon/si.c

5886

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/si.c

5887

WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

5893

WREG32(RLC_UCODE_ADDR, i);

sys/dev/drm/radeon/si.c

5894

WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));

sys/dev/drm/radeon/si.c

5897

WREG32(RLC_UCODE_ADDR, 0);

sys/dev/drm/radeon/si.c

5913

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/si.c

5914

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/si.c

5925

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/si.c

5926

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/si.c

5928

WREG32(IH_RB_RPTR, 0);

sys/dev/drm/radeon/si.c

5929

WREG32(IH_RB_WPTR, 0);

sys/dev/drm/radeon/si.c

5941

WREG32(CP_INT_CNTL_RING0, tmp);

sys/dev/drm/radeon/si.c

5942

WREG32(CP_INT_CNTL_RING1, 0);

sys/dev/drm/radeon/si.c

5943

WREG32(CP_INT_CNTL_RING2, 0);

sys/dev/drm/radeon/si.c

5945

WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

5947

WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);

sys/dev/drm/radeon/si.c

5948

WREG32(GRBM_INT_CNTL, 0);

sys/dev/drm/radeon/si.c

5949

WREG32(SRBM_INT_CNTL, 0);

sys/dev/drm/radeon/si.c

5951

WREG32(INT_MASK + crtc_offsets[i], 0);

sys/dev/drm/radeon/si.c

5953

WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0);

sys/dev/drm/radeon/si.c

5956

WREG32(DAC_AUTODETECT_INT_CONTROL, 0);

sys/dev/drm/radeon/si.c

5987

WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8);

sys/dev/drm/radeon/si.c

5995

WREG32(INTERRUPT_CNTL, interrupt_cntl);

sys/dev/drm/radeon/si.c

5997

WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);

sys/dev/drm/radeon/si.c

6008

WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);

sys/dev/drm/radeon/si.c

6009

WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);

sys/dev/drm/radeon/si.c

6011

WREG32(IH_RB_CNTL, ih_rb_cntl);

sys/dev/drm/radeon/si.c

6014

WREG32(IH_RB_RPTR, 0);

sys/dev/drm/radeon/si.c

6015

WREG32(IH_RB_WPTR, 0);

sys/dev/drm/radeon/si.c

6022

WREG32(IH_CNTL, ih_cntl);

sys/dev/drm/radeon/si.c

6089

WREG32(CP_INT_CNTL_RING0, cp_int_cntl);

sys/dev/drm/radeon/si.c

6090

WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);

sys/dev/drm/radeon/si.c

6091

WREG32(CP_INT_CNTL_RING2, cp_int_cntl2);

sys/dev/drm/radeon/si.c

6093

WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl);

sys/dev/drm/radeon/si.c

6094

WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1);

sys/dev/drm/radeon/si.c

6096

WREG32(GRBM_INT_CNTL, grbm_int_cntl);

sys/dev/drm/radeon/si.c

6111

WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK);

sys/dev/drm/radeon/si.c

6122

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/radeon/si.c

6150

WREG32(GRPH_INT_STATUS + crtc_offsets[j],

sys/dev/drm/radeon/si.c

6156

WREG32(VBLANK_STATUS + crtc_offsets[j],

sys/dev/drm/radeon/si.c

6159

WREG32(VLINE_STATUS + crtc_offsets[j],

sys/dev/drm/radeon/si.c

6216

WREG32(IH_RB_CNTL, tmp);

sys/dev/drm/radeon/si.c

6350

WREG32(SRBM_INT_ACK, 0x1);

sys/dev/drm/radeon/si.c

6423

WREG32(IH_RB_RPTR, rptr);

sys/dev/drm/radeon/si.c

6985

WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);

sys/dev/drm/radeon/si.c

7402

WREG32(THM_CLK_CNTL, data);

sys/dev/drm/radeon/si.c

7408

WREG32(MISC_CLK_CNTL, data);

sys/dev/drm/radeon/si.c

7413

WREG32(CG_CLKPIN_CNTL, data);

sys/dev/drm/radeon/si.c

7418

WREG32(CG_CLKPIN_CNTL_2, data);

sys/dev/drm/radeon/si.c

7424

WREG32(MPLL_BYPASSCLK_SEL, data);

sys/dev/drm/radeon/si.c

7429

WREG32(SPLL_CNTL_MODE, data);

sys/dev/drm/radeon/si_dpm.c

2673

WREG32(CG_CAC_CTRL, reg);

sys/dev/drm/radeon/si_dpm.c

2768

WREG32(config_regs->offset << 2, data);

sys/dev/drm/radeon/si_dpm.c

3218

WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);

sys/dev/drm/radeon/si_dpm.c

3390

WREG32(SMC_SCRATCH0, parameter);

sys/dev/drm/radeon/si_dpm.c

3608

WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);

sys/dev/drm/radeon/si_dpm.c

3619

WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);

sys/dev/drm/radeon/si_dpm.c

3700

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/si_dpm.c

3719

WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);

sys/dev/drm/radeon/si_dpm.c

3763

WREG32(CG_BSP, pi->dsp);

sys/dev/drm/radeon/si_dpm.c

3777

WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));

sys/dev/drm/radeon/si_dpm.c

3793

WREG32(CG_TPC, R600_TPC_DFLT);

sys/dev/drm/radeon/si_dpm.c

3798

WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));

sys/dev/drm/radeon/si_dpm.c

3812

WREG32(CG_DISPLAY_GAP_CNTL, tmp);

sys/dev/drm/radeon/si_dpm.c

3819

WREG32(CG_FTV, pi->vrc);

sys/dev/drm/radeon/si_dpm.c

3824

WREG32(CG_FTV, 0);

sys/dev/drm/radeon/si_dpm.c

4770

WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);

sys/dev/drm/radeon/si_dpm.c

4771

WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);

sys/dev/drm/radeon/si_dpm.c

5547

WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));

sys/dev/drm/radeon/si_dpm.c

5548

WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));

sys/dev/drm/radeon/si_dpm.c

5549

WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));

sys/dev/drm/radeon/si_dpm.c

5550

WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));

sys/dev/drm/radeon/si_dpm.c

5551

WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));

sys/dev/drm/radeon/si_dpm.c

5552

WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));

sys/dev/drm/radeon/si_dpm.c

5553

WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));

sys/dev/drm/radeon/si_dpm.c

5554

WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));

sys/dev/drm/radeon/si_dpm.c

5555

WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));

sys/dev/drm/radeon/si_dpm.c

5556

WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));

sys/dev/drm/radeon/si_dpm.c

5557

WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));

sys/dev/drm/radeon/si_dpm.c

5558

WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));

sys/dev/drm/radeon/si_dpm.c

5559

WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));

sys/dev/drm/radeon/si_dpm.c

5560

WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));

sys/dev/drm/radeon/si_dpm.c

5967

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/radeon/si_dpm.c

5976

WREG32(CG_THERMAL_INT, thermal_int);

sys/dev/drm/radeon/si_dpm.c

6023

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/radeon/si_dpm.c

6027

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/radeon/si_dpm.c

6189

WREG32(CG_FDO_CTRL0, tmp);

sys/dev/drm/radeon/si_dpm.c

6266

WREG32(CG_TACH_CTRL, tmp);

sys/dev/drm/radeon/si_dpm.c

6282

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/radeon/si_dpm.c

6286

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/radeon/si_dpm.c

6306

WREG32(CG_TACH_CTRL, tmp);

sys/dev/drm/radeon/si_dpm.c

6311

WREG32(CG_FDO_CTRL2, tmp);

sys/dev/drm/radeon/si_smc.c

104

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/si_smc.c

180

WREG32(SMC_MESSAGE_0, msg);

sys/dev/drm/radeon/si_smc.c

265

WREG32(SMC_IND_INDEX_0, ucode_start_address);

sys/dev/drm/radeon/si_smc.c

271

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/si_smc.c

306

WREG32(SMC_IND_DATA_0, value);

sys/dev/drm/radeon/si_smc.c

41

WREG32(SMC_IND_INDEX_0, smc_address);

sys/dev/drm/radeon/si_smc.c

71

WREG32(SMC_IND_DATA_0, data);

sys/dev/drm/radeon/sumo_dpm.c

115

WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );

sys/dev/drm/radeon/sumo_dpm.c

116

WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );

sys/dev/drm/radeon/sumo_dpm.c

118

WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );

sys/dev/drm/radeon/sumo_dpm.c

119

WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );

sys/dev/drm/radeon/sumo_dpm.c

142

WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));

sys/dev/drm/radeon/sumo_dpm.c

173

WREG32(CG_SCRATCH2, 0x01B60A17);

sys/dev/drm/radeon/sumo_dpm.c

340

WREG32(CG_BSP_0, pi->psp);

sys/dev/drm/radeon/sumo_dpm.c

358

WREG32(CG_BSP_0 + (i * 4), pi->dsp);

sys/dev/drm/radeon/sumo_dpm.c

360

WREG32(CG_BSP_0 + (i * 4), pi->psp);

sys/dev/drm/radeon/sumo_dpm.c

363

WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);

sys/dev/drm/radeon/sumo_dpm.c

370

WREG32(CG_AT_0, value);

sys/dev/drm/radeon/sumo_dpm.c

372

WREG32(CG_AT_1, value);

sys/dev/drm/radeon/sumo_dpm.c

374

WREG32(CG_AT_2, value);

sys/dev/drm/radeon/sumo_dpm.c

376

WREG32(CG_AT_3, value);

sys/dev/drm/radeon/sumo_dpm.c

378

WREG32(CG_AT_4, value);

sys/dev/drm/radeon/sumo_dpm.c

380

WREG32(CG_AT_5, value);

sys/dev/drm/radeon/sumo_dpm.c

382

WREG32(CG_AT_6, value);

sys/dev/drm/radeon/sumo_dpm.c

384

WREG32(CG_AT_7, value);

sys/dev/drm/radeon/sumo_dpm.c

457

WREG32(CG_FTV, vrc);

sys/dev/drm/radeon/sumo_dpm.c

462

WREG32(CG_FTV, 0);

sys/dev/drm/radeon/sumo_dpm.c

473

WREG32(CG_SSP, SSTU(u) | SST(p));

sys/dev/drm/radeon/sumo_dpm.c

506

WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);

sys/dev/drm/radeon/sumo_dpm.c

520

WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);

sys/dev/drm/radeon/sumo_dpm.c

530

WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);

sys/dev/drm/radeon/sumo_dpm.c

546

WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);

sys/dev/drm/radeon/sumo_dpm.c

751

WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);

sys/dev/drm/radeon/sumo_dpm.c

811

WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);

sys/dev/drm/radeon/sumo_dpm.c

887

WREG32(DOUT_SCRATCH3, v);

sys/dev/drm/radeon/sumo_dpm.c

906

WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);

sys/dev/drm/radeon/sumo_dpm.c

907

WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);

sys/dev/drm/radeon/sumo_dpm.c

940

WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);

sys/dev/drm/radeon/sumo_dpm.c

951

WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);

sys/dev/drm/radeon/sumo_dpm.c

984

WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);

sys/dev/drm/radeon/sumo_smc.c

48

WREG32(GFX_INT_REQ, gfx_int_req);

sys/dev/drm/radeon/sumo_smc.c

69

WREG32(GFX_INT_REQ, gfx_int_req);

sys/dev/drm/radeon/trinity_dpm.c

392

WREG32(CG_PG_CTRL, SP(p) | SU(u));

sys/dev/drm/radeon/trinity_dpm.c

422

WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE);

sys/dev/drm/radeon/trinity_dpm.c

424

WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE);

sys/dev/drm/radeon/trinity_dpm.c

475

WREG32(seq[i], seq[i+1]);

sys/dev/drm/radeon/trinity_dpm.c

946

WREG32(CG_MISC_REG, tmp);

sys/dev/drm/radeon/trinity_smc.c

116

WREG32(SMC_INT_REQ, 1);

sys/dev/drm/radeon/trinity_smc.c

126

WREG32(SMC_INT_REQ, 0);

sys/dev/drm/radeon/trinity_smc.c

35

WREG32(SMC_MESSAGE_0, id);

sys/dev/drm/radeon/uvd_v1_0.c

123

WREG32(UVD_VCPU_CACHE_OFFSET0, addr);

sys/dev/drm/radeon/uvd_v1_0.c

124

WREG32(UVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/radeon/uvd_v1_0.c

128

WREG32(UVD_VCPU_CACHE_OFFSET1, addr);

sys/dev/drm/radeon/uvd_v1_0.c

129

WREG32(UVD_VCPU_CACHE_SIZE1, size);

sys/dev/drm/radeon/uvd_v1_0.c

134

WREG32(UVD_VCPU_CACHE_OFFSET2, addr);

sys/dev/drm/radeon/uvd_v1_0.c

135

WREG32(UVD_VCPU_CACHE_SIZE2, size);

sys/dev/drm/radeon/uvd_v1_0.c

139

WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));

sys/dev/drm/radeon/uvd_v1_0.c

143

WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));

sys/dev/drm/radeon/uvd_v1_0.c

145

WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr));

sys/dev/drm/radeon/uvd_v1_0.c

217

WREG32(MC_CONFIG, 0);

sys/dev/drm/radeon/uvd_v1_0.c

218

WREG32(MC_CONFIG, 1 << 4);

sys/dev/drm/radeon/uvd_v1_0.c

219

WREG32(RS_DQ_RD_RET_CONF, 0x3f);

sys/dev/drm/radeon/uvd_v1_0.c

220

WREG32(MC_CONFIG, 0x1f);

sys/dev/drm/radeon/uvd_v1_0.c

274

WREG32(UVD_CGC_GATE, 0);

sys/dev/drm/radeon/uvd_v1_0.c

285

WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |

sys/dev/drm/radeon/uvd_v1_0.c

295

WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |

sys/dev/drm/radeon/uvd_v1_0.c

303

WREG32(UVD_LMI_SWAP_CNTL, lmi_swap_cntl);

sys/dev/drm/radeon/uvd_v1_0.c

304

WREG32(UVD_MP_SWAP_CNTL, mp_swap_cntl);

sys/dev/drm/radeon/uvd_v1_0.c

306

WREG32(UVD_MPC_SET_MUXA0, 0x40c2040);

sys/dev/drm/radeon/uvd_v1_0.c

307

WREG32(UVD_MPC_SET_MUXA1, 0x0);

sys/dev/drm/radeon/uvd_v1_0.c

308

WREG32(UVD_MPC_SET_MUXB0, 0x40c2040);

sys/dev/drm/radeon/uvd_v1_0.c

309

WREG32(UVD_MPC_SET_MUXB1, 0x0);

sys/dev/drm/radeon/uvd_v1_0.c

310

WREG32(UVD_MPC_SET_ALU, 0);

sys/dev/drm/radeon/uvd_v1_0.c

311

WREG32(UVD_MPC_SET_MUX, 0x88);

sys/dev/drm/radeon/uvd_v1_0.c

314

WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);

sys/dev/drm/radeon/uvd_v1_0.c

318

WREG32(UVD_VCPU_CNTL, 1 << 9);

sys/dev/drm/radeon/uvd_v1_0.c

326

WREG32(UVD_SOFT_RESET, 0);

sys/dev/drm/radeon/uvd_v1_0.c

358

WREG32(UVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/radeon/uvd_v1_0.c

361

WREG32(UVD_RBC_RB_WPTR_CNTL, 0);

sys/dev/drm/radeon/uvd_v1_0.c

364

WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |

sys/dev/drm/radeon/uvd_v1_0.c

368

WREG32(UVD_RBC_RB_RPTR, 0x0);

sys/dev/drm/radeon/uvd_v1_0.c

371

WREG32(UVD_RBC_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/uvd_v1_0.c

374

WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);

sys/dev/drm/radeon/uvd_v1_0.c

394

WREG32(UVD_RBC_RB_CNTL, 0x11010101);

sys/dev/drm/radeon/uvd_v1_0.c

402

WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);

sys/dev/drm/radeon/uvd_v1_0.c

406

WREG32(UVD_VCPU_CNTL, 0x0);

sys/dev/drm/radeon/uvd_v1_0.c

427

WREG32(UVD_CONTEXT_ID, 0xCAFEDEAD);

sys/dev/drm/radeon/uvd_v1_0.c

70

WREG32(UVD_RBC_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/uvd_v2_2.c

115

WREG32(UVD_VCPU_CACHE_OFFSET0, addr);

sys/dev/drm/radeon/uvd_v2_2.c

116

WREG32(UVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/radeon/uvd_v2_2.c

120

WREG32(UVD_VCPU_CACHE_OFFSET1, addr);

sys/dev/drm/radeon/uvd_v2_2.c

121

WREG32(UVD_VCPU_CACHE_SIZE1, size);

sys/dev/drm/radeon/uvd_v2_2.c

126

WREG32(UVD_VCPU_CACHE_OFFSET2, addr);

sys/dev/drm/radeon/uvd_v2_2.c

127

WREG32(UVD_VCPU_CACHE_SIZE2, size);

sys/dev/drm/radeon/uvd_v2_2.c

131

WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));

sys/dev/drm/radeon/uvd_v2_2.c

135

WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));

sys/dev/drm/radeon/uvd_v2_2.c

196

WREG32(UVD_VCPU_CHIP_ID, chip_id);

sys/dev/drm/radeon/uvd_v4_2.c

52

WREG32(UVD_VCPU_CACHE_OFFSET0, addr);

sys/dev/drm/radeon/uvd_v4_2.c

53

WREG32(UVD_VCPU_CACHE_SIZE0, size);

sys/dev/drm/radeon/uvd_v4_2.c

57

WREG32(UVD_VCPU_CACHE_OFFSET1, addr);

sys/dev/drm/radeon/uvd_v4_2.c

58

WREG32(UVD_VCPU_CACHE_SIZE1, size);

sys/dev/drm/radeon/uvd_v4_2.c

63

WREG32(UVD_VCPU_CACHE_OFFSET2, addr);

sys/dev/drm/radeon/uvd_v4_2.c

64

WREG32(UVD_VCPU_CACHE_SIZE2, size);

sys/dev/drm/radeon/uvd_v4_2.c

68

WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));

sys/dev/drm/radeon/uvd_v4_2.c

72

WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));

sys/dev/drm/radeon/uvd_v4_2.c

75

WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles);

sys/dev/drm/radeon/vce_v1_0.c

110

WREG32(VCE_CLOCK_GATING_A, tmp);

sys/dev/drm/radeon/vce_v1_0.c

115

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v1_0.c

119

WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v1_0.c

123

WREG32(VCE_CLOCK_GATING_A, tmp);

sys/dev/drm/radeon/vce_v1_0.c

128

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v1_0.c

132

WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v1_0.c

142

WREG32(VCE_CLOCK_GATING_A, tmp);

sys/dev/drm/radeon/vce_v1_0.c

147

WREG32(VCE_CLOCK_GATING_B, tmp);

sys/dev/drm/radeon/vce_v1_0.c

151

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v1_0.c

155

WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v1_0.c

226

WREG32(VCE_CLOCK_GATING_B, 0);

sys/dev/drm/radeon/vce_v1_0.c

230

WREG32(VCE_LMI_CTRL, 0x00398000);

sys/dev/drm/radeon/vce_v1_0.c

232

WREG32(VCE_LMI_SWAP_CNTL, 0);

sys/dev/drm/radeon/vce_v1_0.c

233

WREG32(VCE_LMI_SWAP_CNTL1, 0);

sys/dev/drm/radeon/vce_v1_0.c

234

WREG32(VCE_LMI_VM_CTRL, 0);

sys/dev/drm/radeon/vce_v1_0.c

236

WREG32(VCE_VCPU_SCRATCH7, RADEON_MAX_VCE_HANDLES);

sys/dev/drm/radeon/vce_v1_0.c

240

WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);

sys/dev/drm/radeon/vce_v1_0.c

241

WREG32(VCE_VCPU_CACHE_SIZE0, size);

sys/dev/drm/radeon/vce_v1_0.c

245

WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);

sys/dev/drm/radeon/vce_v1_0.c

246

WREG32(VCE_VCPU_CACHE_SIZE1, size);

sys/dev/drm/radeon/vce_v1_0.c

250

WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);

sys/dev/drm/radeon/vce_v1_0.c

251

WREG32(VCE_VCPU_CACHE_SIZE2, size);

sys/dev/drm/radeon/vce_v1_0.c

255

WREG32(VCE_LMI_FW_START_KEYSEL, rdev->vce.keyselect);

sys/dev/drm/radeon/vce_v1_0.c

299

WREG32(VCE_RB_RPTR, ring->wptr);

sys/dev/drm/radeon/vce_v1_0.c

300

WREG32(VCE_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/vce_v1_0.c

301

WREG32(VCE_RB_BASE_LO, ring->gpu_addr);

sys/dev/drm/radeon/vce_v1_0.c

302

WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));

sys/dev/drm/radeon/vce_v1_0.c

303

WREG32(VCE_RB_SIZE, ring->ring_size / 4);

sys/dev/drm/radeon/vce_v1_0.c

306

WREG32(VCE_RB_RPTR2, ring->wptr);

sys/dev/drm/radeon/vce_v1_0.c

307

WREG32(VCE_RB_WPTR2, ring->wptr);

sys/dev/drm/radeon/vce_v1_0.c

308

WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);

sys/dev/drm/radeon/vce_v1_0.c

309

WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));

sys/dev/drm/radeon/vce_v1_0.c

310

WREG32(VCE_RB_SIZE2, ring->ring_size / 4);

sys/dev/drm/radeon/vce_v1_0.c

97

WREG32(VCE_RB_WPTR, ring->wptr);

sys/dev/drm/radeon/vce_v1_0.c

99

WREG32(VCE_RB_WPTR2, ring->wptr);

sys/dev/drm/radeon/vce_v2_0.c

104

WREG32(VCE_CGTT_CLK_OVERRIDE, 7);

sys/dev/drm/radeon/vce_v2_0.c

138

WREG32(VCE_CLOCK_GATING_A, tmp);

sys/dev/drm/radeon/vce_v2_0.c

143

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

148

WREG32(VCE_CLOCK_GATING_B, tmp);

sys/dev/drm/radeon/vce_v2_0.c

165

WREG32(VCE_CLOCK_GATING_B, 0xf7);

sys/dev/drm/radeon/vce_v2_0.c

167

WREG32(VCE_LMI_CTRL, 0x00398000);

sys/dev/drm/radeon/vce_v2_0.c

169

WREG32(VCE_LMI_SWAP_CNTL, 0);

sys/dev/drm/radeon/vce_v2_0.c

170

WREG32(VCE_LMI_SWAP_CNTL1, 0);

sys/dev/drm/radeon/vce_v2_0.c

171

WREG32(VCE_LMI_VM_CTRL, 0);

sys/dev/drm/radeon/vce_v2_0.c

173

WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);

sys/dev/drm/radeon/vce_v2_0.c

177

WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);

sys/dev/drm/radeon/vce_v2_0.c

178

WREG32(VCE_VCPU_CACHE_SIZE0, size);

sys/dev/drm/radeon/vce_v2_0.c

182

WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);

sys/dev/drm/radeon/vce_v2_0.c

183

WREG32(VCE_VCPU_CACHE_SIZE1, size);

sys/dev/drm/radeon/vce_v2_0.c

187

WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);

sys/dev/drm/radeon/vce_v2_0.c

188

WREG32(VCE_VCPU_CACHE_SIZE2, size);

sys/dev/drm/radeon/vce_v2_0.c

45

WREG32(VCE_CLOCK_GATING_B, tmp);

sys/dev/drm/radeon/vce_v2_0.c

49

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

53

WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

55

WREG32(VCE_CGTT_CLK_OVERRIDE, 0);

sys/dev/drm/radeon/vce_v2_0.c

60

WREG32(VCE_CLOCK_GATING_B, tmp);

sys/dev/drm/radeon/vce_v2_0.c

65

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

69

WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

85

WREG32(VCE_CLOCK_GATING_B, tmp);

sys/dev/drm/radeon/vce_v2_0.c

91

WREG32(VCE_UENC_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

96

WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);

sys/dev/drm/radeon/vce_v2_0.c

99

WREG32(VCE_CGTT_CLK_OVERRIDE, 0);