WR4
WR4(sc, off, RD4(sc, off) & val);
WR4(sc, off, RD4(sc, off) | val);
WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CMD);
WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR);
WR4(sc, TPM_CRB_CTRL_CANCEL, TPM_CRB_CTRL_CANCEL_CLEAR);
WR4(sc, TPM_CRB_CTRL_START, TPM_CRB_CTRL_START_CMD);
WR4(sc, TPM_INT_ENABLE, irq_mask);
WR4(sc, TPM_INT_STS, status);
WR4(sc, TPM_STS, TPM_STS_CMD_RDY);
WR4(sc, TPM_STS, TPM_STS_CMD_START);
WR4(slot, SDHCI_SIGNAL_ENABLE,
WR4(slot, SDHCI_ARGUMENT, cmd->arg);
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE);
WR4(slot, SDHCI_ADMA_ADDRESS_LOW, descmem->dmem_busaddr);
WR4(slot, SDHCI_SIGNAL_ENABLE,
WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
WR4(slot, SDHCI_SIGNAL_ENABLE,
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
WR4(slot, SDHCI_SDMA_ADDRESS, sdma->dmem_busaddr);
WR4(slot, SDHCI_INT_STATUS, intmask &
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ADMAERR);
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
WR4(slot, SDHCI_INT_STATUS, intmask);
WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
WR4(slot, SDHCI_BUFFER, data);
WR4(slot, SDHCI_BUFFER, data);
WR4(slot, SDHCI_SIGNAL_ENABLE, 0);