Symbol: WARN_ONCE
sys/dev/drm/amd/amdgpu/amdgpu_gem.c
103
WARN_ONCE(1, "Still active user space clients!\n");
sys/dev/drm/amd/amdgpu/amdgpu_gem.c
106
WARN_ONCE(1, "And also active allocations!\n");
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
3086
WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
sys/dev/drm/amd/amdgpu/amdgpu_vm.c
3215
WARN_ONCE((vm->use_cpu_for_update & !amdgpu_gmc_vram_full_visible(&adev->gmc)),
sys/dev/drm/amd/amdgpu/cik_sdma.c
363
WARN_ONCE(1,
sys/dev/drm/amd/amdgpu/sdma_v3_0.c
570
WARN_ONCE(1,
sys/dev/drm/amd/amdgpu/sdma_v4_0.c
624
WARN_ONCE(1,
sys/dev/drm/drm_atomic_helper.c
1020
WARN_ONCE(ret != -EINVAL, "driver forgot to call drm_crtc_vblank_off()\n");
sys/dev/drm/drm_vblank.c
1278
WARN_ONCE((drm_debug & DRM_UT_VBL) && !vblank->framedur_ns,
sys/dev/drm/drm_vblank.c
305
WARN_ONCE(drm_debug & DRM_UT_VBL && !dev->driver->get_vblank_timestamp,
sys/dev/drm/i915/i915_gem.c
2491
WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
sys/dev/drm/i915/i915_gem_execbuffer.c
1397
if (WARN_ONCE(err,
sys/dev/drm/i915/i915_gem_userptr.c
85
WARN_ONCE(i915_gem_object_has_pages(obj),
sys/dev/drm/i915/i915_irq.c
2058
WARN_ONCE(1,
sys/dev/drm/i915/i915_irq.c
3009
WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",
sys/dev/drm/i915/i915_irq.c
3027
WARN_ONCE(1, "unhandled engine interrupt class=0x%x, instance=0x%x\n",
sys/dev/drm/i915/i915_irq.c
3048
WARN_ONCE(1, "unknown interrupt class=0x%x, instance=0x%x, intr=0x%x\n",
sys/dev/drm/i915/i915_irq.c
696
WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
sys/dev/drm/i915/i915_irq.c
710
WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
sys/dev/drm/i915/i915_irq.c
733
WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
sys/dev/drm/i915/i915_perf.c
698
if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
sys/dev/drm/i915/i915_perf.c
984
if (WARN_ONCE(head > OA_BUFFER_SIZE || head % report_size ||
sys/dev/drm/i915/i915_utils.h
41
#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
sys/dev/drm/i915/intel_drv.h
2020
WARN_ONCE(dev_priv->runtime_pm.suspended,
sys/dev/drm/i915/intel_drv.h
2028
WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
sys/dev/drm/i915/intel_guc_submission.c
219
WARN_ONCE(true, "Doorbell never became invalid after disable\n");
sys/dev/drm/i915/intel_hotplug.c
456
WARN_ONCE(!HAS_GMCH_DISPLAY(dev_priv),
sys/dev/drm/i915/intel_mocs.c
191
WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
sys/dev/drm/i915/intel_opregion.c
403
WARN_ONCE(1, "unsupported intel_encoder type %d\n",
sys/dev/drm/i915/intel_pm.c
6533
if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
sys/dev/drm/i915/intel_pm.c
7568
WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
sys/dev/drm/i915/intel_pm.c
7663
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
sys/dev/drm/i915/intel_pm.c
7747
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
sys/dev/drm/i915/intel_runtime_pm.c
4020
WARN_ONCE(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
sys/dev/drm/i915/intel_runtime_pm.c
477
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
sys/dev/drm/i915/intel_runtime_pm.c
479
WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
sys/dev/drm/i915/intel_runtime_pm.c
481
WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) &
sys/dev/drm/i915/intel_runtime_pm.c
484
WARN_ONCE(intel_irqs_enabled(dev_priv),
sys/dev/drm/i915/intel_runtime_pm.c
498
WARN_ONCE(intel_irqs_enabled(dev_priv),
sys/dev/drm/i915/intel_runtime_pm.c
500
WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
sys/dev/drm/i915/intel_runtime_pm.c
645
WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
sys/dev/drm/i915/intel_runtime_pm.c
647
WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
sys/dev/drm/i915/intel_runtime_pm.c
648
WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
sys/dev/drm/i915/intel_runtime_pm.c
677
WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
sys/dev/drm/i915/intel_runtime_pm.c
679
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
sys/dev/drm/i915/intel_runtime_pm.c
702
WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
sys/dev/drm/i915/intel_runtime_pm.c
704
WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
sys/dev/drm/i915/intel_uncore.c
302
WARN_ONCE(wait_for_atomic_us(gt_thread_status(dev_priv) == 0, 5000),