WARN
WARN(1, "Invalid indirect register space");
WARN(1, "Invalid indirect register space");
WARN(1, "trying to unbind memory from uninitialized GART !\n");
WARN(1, "trying to bind memory to uninitialized GART !\n");
WARN(1, "trying to bind memory to uninitialized GART !\n");
WARN(1, "Invalid context priority %d\n", amdgpu_priority);
WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
WARN(1, "R600 PCIE GART already initialized\n");
WARN(1, "R600 PCIE GART already initialized\n");
WARN(1, "VEGA10 PCIE GART already initialized\n");
WARN(1, "Global lock should be Set, overall_update_type should be UPDATE_TYPE_MED or UPDATE_TYPE_FULL");
WARN(1, "Global lock should NOT be set, overall_update_type should be UPDATE_TYPE_FAST");
WARN(!ret, "[CRTC:%d:%s] vblank wait timed out\n",
WARN(1, "unknown DP link rate %d, using %x\n", link_rate,
WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw);
WARN(1, "Loading EDID firmware with extensions is untested!\n");
WARN(dev->fb_helper, "fb_helper is already set!\n");
WARN(ret, "atomic remove_fb failed with %i\n", ret);
if (WARN(!drm_mm_clean(mm),
WARN(1, "Failed to attach object property (type: 0x%x). Please "
WARN(in->hdisplay > USHRT_MAX || in->hsync_start > USHRT_MAX ||
} else if (WARN(ret < 0, "Invalid return value %i for connector detection\n", ret))
if (WARN(ret, "vblank not available on crtc %i, ret=%i\n", pipe, ret))
WARN(ret == 0, "vblank wait timed out on crtc %i\n", pipe);
if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
if (!WARN(i915_modparams.verbose_state_checks, format)) \
WARN(i915_vma_is_pinned(vma),
if (WARN(!i915_gem_object_get_stride(vma->obj) ||
if (WARN(num_entries > max_entries,
if (WARN(num_entries > max_entries,
WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val);
if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
#define MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state),
WARN(!IS_I830(dev_priv),
if (WARN((I915_READ(LCPLL_CTL) &
WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
WARN(1, "bad wrpll refclk\n");
WARN(1, "Unsupported link rate\n");
WARN(1, "Unsupported link rate\n");
WARN(1, "bad spll freq\n");
WARN(1, "bad port clock sel\n");
WARN(1, "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
WARN(1, "ddi translation table missing\n");
WARN(1, "pipe_off wait timed out\n");
if (WARN(!retry, "loop in pipe configuration computation\n")) {
WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
WARN(true, "Could not determine valid watermarks for inherited state\n");
WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
WARN((val & CCK_FREQUENCY_STATUS) !=
WARN(num_encoders != 1, "%d encoders for pipe %c\n",
if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
WARN(1, "unknown pipe linked to edp transcoder\n");
WARN(1, "eDP powered off while attempting aux channel communication.\n");
WARN(1, "dp_aux_ch not started status 0x%08x\n",
if (WARN(edp_have_panel_power(intel_dp),
WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
WARN(intel_dp->active_pipe == pipe,
WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
if (WARN(intel_dig_port->max_lanes < 1,
if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
WARN(1, "PHY not found for PORT %c", port_name(port));
if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
WARN(1, "Incorrect PDiv\n");
WARN(1, "Incorrect KDiv\n");
WARN(1, "Incorrect KDiv\n");
WARN(1, "Incorrect PDiv\n");
WARN(!crtc->primary->state->fb,
WARN(1, "Unexpected send: action=%#x\n", *action);
WARN(1, "Unexpected event: no suitable handler\n");
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
if (WARN(intel_dig_port->max_lanes < 4,
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
WARN(val & VIDEO_DIP_ENABLE,
WARN(val & VIDEO_DIP_ENABLE,
WARN(!dev_priv->vbt.int_lvds_support,
WARN(1, "bad panel fit mode: %d\n", fitting_mode);
WARN(1, "bad panel fit mode: %d\n", fitting_mode);
WARN(1, "Unsupported pixel depth %u for rotation",
WARN(actual != expected,
WARN(!power_domains->domain_use_count[domain],
WARN(!power_well->count, "Use count on power well %s is already zero",
WARN(ret < 0, "pm_runtime_get_sync() failed: %d\n", ret);
WARN(pm_runtime_get_sync(&dev_priv->drm.pdev->dev) < 0,
WARN(1, "Power well %d not defined for this platform\n", power_well_id);
WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
WARN(1, "unknown pixel multiplier specified\n");
WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
WARN(!(guc_status & GS_MIA_IN_RESET),
if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
WARN(dev_priv->uncore.fw_domains_active,
WARN(fw_domains & ~dev_priv->uncore.fw_domains_active,
WARN(entry->domains & ~dev_priv->uncore.fw_domains,
WARN(bpp != pipe_bpp,
#ifndef WARN
WARN(condition, format); \
WARN(1, "Bad infoframe type %d\n", frame->any.type);
WARN(ret, "drm_dp_aux_register() failed with error %d\n", ret);
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
WARN(1, "R100 PCI GART already initialized\n");
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
WARN(1, "RV370 PCIE GART already initialized\n");
WARN(1, "R600 PCIE GART already initialized\n");
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
WARN(1, "trying to unbind memory from uninitialized GART !\n");
WARN(1, "trying to bind memory to uninitialized GART !\n");
WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
WARN(1, "RS400 GART already initialized\n");
WARN(1, "RS600 GART already initialized\n");
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
WARN(0, "could not open %s for writing", dev);
WARN(0, "ioctl()");
WARN(0, "open(%s)", path);
WARN(0, "fstat(%s)", path);
WARN(0, "mmap(%s)", path);
WARN(0, "ioctl()");
WARN(0, "could not open %s for writing", dev);
WARN(0, "ioctl()");
WARN(0, "ioctl(%s)", dev);
WARN(0, "open(%s)", path);
WARN(0, "fstat(%s)", path);
WARN(0, "mmap(%s)", path);
WARN(0, "ioctl(%s)", dev);
WARN(0, "ioctl()");
WARN(0, "ioctl()");
WARN(0, "stat(%s)", path);
WARN(0, "error opening %s for reading", dev);
WARN(0, "ioctl(%s, CPUCTL_CPUID)", dev);
WARN(0, "error opening %s for reading", dev);
WARN(0, "ioctl(%s, CPUCTL_CPUID_COUNT)", dev);
WARN(0, "error opening %s for %s", dev,
WARN(0, "ioctl(%s, CPUCTL_%s (%lu))", dev, command_name, command);
WARN(0, "error opening %s for writing", dev);
WARN(0, "ioctl(%s, CPUCTL_EVAL_CPU_FEATURES)", dev);
WARN(0, "error opening %s for reading", dev);
WARN(0, "closedir(%s)", dir->path);
WARN(0, "could not open %s for writing", dev);
WARN(0, "ioctl(%s)", dev);
WARN(0, "ioctl(%s)", dev);
WARN(0, "ioctl(%s)", dev);
WARN(0, "open(%s)", path);
WARN(0, "fstat(%s)", path);
WARN(0, "mmap(%s)", path);
WARN(0, "ioctl()");
WARN(0, "ioctl()");
WARN(0, "could not open %s for writing", dev);
WARN(0, "ioctl(%s)", dev);
WARN(0, "ioctl(%s)", dev);
WARN(0, "ioctl(%s)", dev);
WARN(0, "open(%s)", path);
WARN(0, "fstat(%s)", path);
WARN(0, "mmap(%s)", path);
WARN(0, "ioctl()");
WARN(0, "ioctl()");