#include <machine/param.h>
#include <machine/asm.h>
#include <mips64/mips_cpu.h>
#ifndef _STANDALONE
#include "assym.h"
#endif
.set mips3
.data
.globl pmon_callvec
pmon_callvec:
.word 0
pmon_o32:
.word 0
.text
#define PMON_WRAP(name, index) \
NNON_LEAF(name, FRAMESZ(CF_SZ + 9 * REGSZ), ra); \
PTR_SUBU sp, sp, FRAMESZ(CF_SZ + 9 * REGSZ); \
REG_S ra, CF_RA_OFFS(sp); \
.mask 0xc0ff0000, (CF_RA_OFFS - FRAMESZ(CF_SZ + 9 * REGSZ)); \
REG_S s0, (0 * REGSZ + CF_SZ)(sp); \
REG_S s1, (1 * REGSZ + CF_SZ)(sp); \
REG_S s2, (2 * REGSZ + CF_SZ)(sp); \
REG_S s3, (3 * REGSZ + CF_SZ)(sp); \
REG_S s4, (4 * REGSZ + CF_SZ)(sp); \
REG_S s5, (5 * REGSZ + CF_SZ)(sp); \
REG_S s6, (6 * REGSZ + CF_SZ)(sp); \
REG_S s7, (7 * REGSZ + CF_SZ)(sp); \
REG_S s8, (8 * REGSZ + CF_SZ)(sp); \
lw t0, pmon_callvec; \
lw t0, (index) * 4 (t0); \
jalr t0; \
nop; \
REG_L s8, (8 * REGSZ + CF_SZ)(sp); \
REG_L s7, (7 * REGSZ + CF_SZ)(sp); \
REG_L s6, (6 * REGSZ + CF_SZ)(sp); \
REG_L s5, (5 * REGSZ + CF_SZ)(sp); \
REG_L s4, (4 * REGSZ + CF_SZ)(sp); \
REG_L s3, (3 * REGSZ + CF_SZ)(sp); \
REG_L s2, (2 * REGSZ + CF_SZ)(sp); \
REG_L s1, (1 * REGSZ + CF_SZ)(sp); \
REG_L s0, (0 * REGSZ + CF_SZ)(sp); \
REG_L ra, CF_RA_OFFS(sp); \
PTR_ADDU sp, sp, FRAMESZ(CF_SZ + 9 * REGSZ); \
jr ra; \
nop; \
END(name)
PMON_WRAP(pmon_printf, 5)
PMON_WRAP(pmon_gets, 7)
#ifdef _STANDALONE
PMON_WRAP(pmon_open, 0)
PMON_WRAP(pmon_close, 1)
PMON_WRAP(pmon_read, 2)
PMON_WRAP(pmon_cacheflush, 6)
#endif
#if 0
PMON_WRAP(pmon_write, 3)
#endif
NNON_LEAF(pmon_lseek, FRAMESZ(CF_SZ + 9 * REGSZ), ra)
PTR_SUBU sp, sp, FRAMESZ(CF_SZ + 9 * REGSZ)
REG_S ra, CF_RA_OFFS(sp)
.mask 0xc0ff0000, (CF_RA_OFFS - FRAMESZ(CF_SZ + 9 * REGSZ))
REG_S s0, (0 * REGSZ + CF_SZ)(sp)
REG_S s1, (1 * REGSZ + CF_SZ)(sp)
REG_S s2, (2 * REGSZ + CF_SZ)(sp)
REG_S s3, (3 * REGSZ + CF_SZ)(sp)
REG_S s4, (4 * REGSZ + CF_SZ)(sp)
REG_S s5, (5 * REGSZ + CF_SZ)(sp)
REG_S s6, (6 * REGSZ + CF_SZ)(sp)
REG_S s7, (7 * REGSZ + CF_SZ)(sp)
REG_S s8, (8 * REGSZ + CF_SZ)(sp)
lw t0, pmon_callvec
lw t0, 4 * 4 (t0)
lw t1, pmon_o32
bne t1, zero, 1f
nop
jalr t0
nop
b 2f
nop
1:
sw a2, 4 * 4 (sp)
sll a2, a1, 0 # get the low 32 bits
dsrl a3, a1, 32 # get the high 32 bits
jalr t0
nop
dsll v0, v0, 32 # clear any sign extension
dsrl v0, v0, 32
dsll v1, v1, 32
or v0, v0, v1
2:
REG_L s8, (8 * REGSZ + CF_SZ)(sp)
REG_L s7, (7 * REGSZ + CF_SZ)(sp)
REG_L s6, (6 * REGSZ + CF_SZ)(sp)
REG_L s5, (5 * REGSZ + CF_SZ)(sp)
REG_L s4, (4 * REGSZ + CF_SZ)(sp)
REG_L s3, (3 * REGSZ + CF_SZ)(sp)
REG_L s2, (2 * REGSZ + CF_SZ)(sp)
REG_L s1, (1 * REGSZ + CF_SZ)(sp)
REG_L s0, (0 * REGSZ + CF_SZ)(sp)
REG_L ra, CF_RA_OFFS(sp)
PTR_ADDU sp, sp, FRAMESZ(CF_SZ + 9 * REGSZ)
jr ra
nop
END(pmon_lseek)
NNON_LEAF(pmon_probe_abi, FRAMESZ(CF_SZ + 9 * REGSZ), ra)
PTR_SUBU sp, sp, FRAMESZ(CF_SZ + 9 * REGSZ)
REG_S ra, CF_RA_OFFS(sp)
.mask 0xc0ff0000, (CF_RA_OFFS - FRAMESZ(CF_SZ + 9 * REGSZ))
REG_S s0, (0 * REGSZ + CF_SZ)(sp)
REG_S s1, (1 * REGSZ + CF_SZ)(sp)
REG_S s2, (2 * REGSZ + CF_SZ)(sp)
REG_S s3, (3 * REGSZ + CF_SZ)(sp)
REG_S s4, (4 * REGSZ + CF_SZ)(sp)
REG_S s5, (5 * REGSZ + CF_SZ)(sp)
REG_S s6, (6 * REGSZ + CF_SZ)(sp)
REG_S s7, (7 * REGSZ + CF_SZ)(sp)
REG_S s8, (8 * REGSZ + CF_SZ)(sp)
mfc0 t0, COP_0_PRID
and t1, t0, 0xff00
li t2, 0x6300
bne t1, t2, 1f
and t1, t0, 0x00ff
li t2, 0x0005
blt t1, t2, 1f
nop
li a0, 0x10000
move a1, zero
move a2, zero
move a3, zero
sw zero, 4 * 4 (sp)
move v0, zero
move v1, zero
lw t0, pmon_callvec
lw t0, 4 * 4 (t0)
jalr t0
nop
li t0, -1
bne v0, t0, 1f
nop
bne v1, t0, 1f
li t1, 1
sw t1, pmon_o32
1:
REG_L s8, (8 * REGSZ + CF_SZ)(sp)
REG_L s7, (7 * REGSZ + CF_SZ)(sp)
REG_L s6, (6 * REGSZ + CF_SZ)(sp)
REG_L s5, (5 * REGSZ + CF_SZ)(sp)
REG_L s4, (4 * REGSZ + CF_SZ)(sp)
REG_L s3, (3 * REGSZ + CF_SZ)(sp)
REG_L s2, (2 * REGSZ + CF_SZ)(sp)
REG_L s1, (1 * REGSZ + CF_SZ)(sp)
REG_L s0, (0 * REGSZ + CF_SZ)(sp)
REG_L ra, CF_RA_OFFS(sp)
PTR_ADDU sp, sp, FRAMESZ(CF_SZ + 9 * REGSZ)
jr ra
nop
END(pmon_probe_abi)