sys/dev/pci/drm/i915/intel_mchbar_regs.h

25

#define CTG_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x34)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

26

#define ELK_STOLEN_RESERVED _MMIO(MCHBAR_MIRROR_BASE + 0x48)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

32

#define CSHRDDR3CTL _MMIO(MCHBAR_MIRROR_BASE + 0x1a8)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

36

#define DCC _MMIO(MCHBAR_MIRROR_BASE + 0x200)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

43

#define DCC2 _MMIO(MCHBAR_MIRROR_BASE + 0x204)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

47

#define C0DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x206)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

48

#define C1DRB3_BW _MMIO(MCHBAR_MIRROR_BASE + 0x606)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

51

#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

68

#define HPLLVCO_MOBILE _MMIO(MCHBAR_MIRROR_BASE + 0xc0f)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

69

#define HPLLVCO _MMIO(MCHBAR_MIRROR_BASE + 0xc38)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

71

#define TSC1 _MMIO(MCHBAR_MIRROR_BASE + 0x1001)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

73

#define TR1 _MMIO(MCHBAR_MIRROR_BASE + 0x1006)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

74

#define TSFS _MMIO(MCHBAR_MIRROR_BASE + 0x1020)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

80

#define MLTR_ILK _MMIO(MCHBAR_MIRROR_BASE + 0x1222)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

85

#define CSIPLL0 _MMIO(MCHBAR_MIRROR_BASE + 0x2c10)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

86

#define DDRMPLL1 _MMIO(MCHBAR_MIRROR_BASE + 0x2c20)

sys/dev/pci/drm/i915/intel_mchbar_regs.h

88

#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)