MB_WRITE_COMMITTED
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
(i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED);
intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);
intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
CONTROL0_MAC_TRANSMIT_LFPS, MB_WRITE_COMMITTED);
0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
MB_WRITE_COMMITTED);
0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);