Symbol: MAX_PIPES
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
10424
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
12276
struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
3081
struct dc_stream_state *del_streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1295
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1571
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1673
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1757
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1857
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
1941
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2041
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2121
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2218
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2296
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2350
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2419
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
2488
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
1230
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1101
bool tried[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1102
int kbps_increase[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1194
struct dsc_mst_fairness_params params[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1357
struct amdgpu_dm_connector *stream_on_link[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1373
for (i = 0; i < MAX_PIPES; i++)
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1488
bool computed_streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
1558
bool computed_streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
998
bool bpp_increased[MAX_PIPES];
sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
999
int initial_slack[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/basics/dce_calcs.c
3012
const struct pipe_ctx *active_pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
170
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
140
for (k = 0; k < MAX_PIPES; k++)
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
514
struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
517
for (int i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
564
uint32_t pix_clk_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
565
int p_state_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
566
int disp_src_width_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
567
int disp_src_height_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
568
uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
569
bool is_scaled_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
284
bool dppclk_active[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
330
for (i = 0; i < MAX_PIPES * 2; ++i) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
418
struct pipe_ctx *pipe_ctx_list[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
421
for (int i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
466
uint32_t pix_clk_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
467
int p_state_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
468
int disp_src_width_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
469
int disp_src_height_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
470
uint64_t disp_src_refresh_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
471
bool is_scaled_list[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/core/dc.c
1301
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
1593
struct pipe_ctx *multisync_pipes[MAX_PIPES] = { NULL };
sys/dev/pci/drm/amd/display/dc/core/dc.c
1619
struct pipe_ctx *unsynced_pipes[MAX_PIPES] = { NULL };
sys/dev/pci/drm/amd/display/dc/core/dc.c
1633
struct pipe_ctx *pipe_set[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc.c
2013
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
2255
for (k = 0; k < MAX_PIPES; k++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
2506
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
2637
for (j = 0; j < MAX_PIPES; j++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
424
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
4600
char force_odm[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc.c
488
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
525
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
5585
enum mall_stream_type subvp_pipe_type[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/core/dc.c
591
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
598
if (i == MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/core/dc.c
6141
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
6148
if (i == MAX_PIPES) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
6192
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
6199
if (i == MAX_PIPES) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
6369
for (int i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
657
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
664
if (i == MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/core/dc.c
780
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
786
if (i == MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/core/dc.c
806
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
828
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
869
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
888
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc.c
911
struct pipe_ctx *pipes_affected[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc.c
919
for (j = 0; j < MAX_PIPES; j++) {
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1155
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1172
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_hw_sequencer.c
1191
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
101
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
237
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
253
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
303
for (i = 0; i < MAX_PIPES; i++)
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
399
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
405
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
418
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
469
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
508
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
532
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
582
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
604
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
630
int eng_ids_per_ep_id[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
631
int ep_ids_per_eng_id[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
635
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
648
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
658
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
666
for (j = 0; j < MAX_PIPES; j++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
691
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_link_enc_cfg.c
735
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1412
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1704
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1958
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1968
struct pipe_ctx *opp_heads[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1984
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
1993
struct pipe_ctx *dpp_pipes[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2003
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2012
struct pipe_ctx *dpp_pipes[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2017
for (j = 0; j < MAX_PIPES; j++) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2026
if (j < MAX_PIPES) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2225
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2355
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2356
struct pipe_ctx *dpp_pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
2978
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
3384
struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4080
struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4081
struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
4082
struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5584
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
5585
struct pipe_ctx *dpp_pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/core/dc_resource.c
695
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_state.c
151
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
240
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
375
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
651
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
681
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
719
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
746
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
752
if (i == MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
776
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
782
if (i == MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/core/dc_stream.c
818
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dc.h
1141
uint32_t dml21_force_pstate_method_values[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc.h
1159
uint32_t acpi_transition_bitmasks[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc.h
1773
bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
sys/dev/pci/drm/amd/display/dc/dc.h
1843
} hubps[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc.h
1844
uint32_t curr_det_sizes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc.h
1845
uint32_t target_det_sizes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc.h
839
bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dc_dmub_srv.c
411
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
132
type OTG_ADD_PIXEL[MAX_PIPES];\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
133
type OTG_DROP_PIXEL[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
168
type DTBCLK_DTO_ENABLE[MAX_PIPES];\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
169
type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
170
type PIPE_DTO_SRC_SEL[MAX_PIPES];\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
171
type DTBCLK_DTO_DIV[MAX_PIPES];\
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
360
type DP_DTO_ENABLE[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
387
uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES]; \
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
394
uint32_t DTBCLK_DTO_MODULO[MAX_PIPES]; \
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
395
uint32_t DTBCLK_DTO_PHASE[MAX_PIPES]; \
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
427
uint32_t DP_DTO_MODULO[MAX_PIPES]; \
sys/dev/pci/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
428
uint32_t DP_DTO_PHASE[MAX_PIPES]
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
189
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dce/dce_clk_mgr.c
510
for (k = 0; k < MAX_PIPES; k++)
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
228
uint32_t PHASE[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
229
uint32_t MODULO[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dce/dce_clock_source.h
230
uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dce/dmub_psr.c
305
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dce/dmub_replay.c
128
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dml/calcs/dcn_calcs.c
709
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2036
int pipe_split_from[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
2327
int pipe_split_from[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1173
struct pipe_ctx *dpp_pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1203
int split[MAX_PIPES],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1204
bool merge[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1286
struct vba_vars_st *vba, int split[MAX_PIPES],
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1287
bool merge[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1404
unsigned int cur_policy[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1414
memset(split, 0, MAX_PIPES * sizeof(int));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1415
memset(merge, 0, MAX_PIPES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1477
memset(split, 0, MAX_PIPES * sizeof(int));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1478
memset(merge, 0, MAX_PIPES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
1945
bool newly_split[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2147
int split[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
2148
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
476
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c
492
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
47
for (int i = 0; i < MAX_PIPES; i++)
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
349
unsigned int preferred_pipe_candidates[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
350
unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
415
unsigned int preferred_pipe_candidates[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
416
unsigned int last_resort_pipe_candidates[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
47
unsigned int odm_slice_end_x[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
48
struct pipe_ctx *next_higher_pipe_for_odm_slice[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
612
unsigned int pipes[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
650
unsigned int pipes[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
911
struct pipe_ctx *dpp_pipes[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
927
struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
943
struct dml2_pipe_combine_factor odm_factors[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
960
struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
989
struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
131
struct dml2_pipe_combine_factor odm_factors[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_internal_types.h
132
struct dml2_pipe_combine_factor mpc_factors[MAX_PIPES][MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1278
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
1317
for (k = 0; k < MAX_PIPES; k++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
986
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_translation_helper.c
999
ASSERT(i < MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_utils.c
519
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
100
struct pipe_ctx *opp_heads[MAX_PIPES]);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
103
struct pipe_ctx *dpp_pipes[MAX_PIPES]);
sys/dev/pci/drm/amd/display/dc/dml2/dml2_wrapper.h
236
enum dml2_force_pstate_methods force_pstate_method_values[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
1097
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2054
for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2095
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
2296
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
3300
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1429
TRACE_DC_PIPE_STATE(pipe_ctx, i, MAX_PIPES);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1575
bool tg_enabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
1709
if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2389
uint64_t phase[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2390
uint64_t modulo[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
2401
hw_crtc_timing = kcalloc(MAX_PIPES, sizeof(*hw_crtc_timing), GFP_KERNEL);
sys/dev/pci/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
3570
for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
1195
int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
3190
for (j = 0; j < MAX_PIPES; j++)
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
841
int opp_inst[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
851
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
300
for (j = 0; j < MAX_PIPES; j++)
sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
1255
for (int i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
176
int opp_inst[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
402
bool otg_disabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
434
int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
sys/dev/pci/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
487
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1135
int opp_inst[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1247
bool otg_disabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1279
int opp_inst[MAX_PIPES] = { pipe->stream_res.opp->inst };
sys/dev/pci/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
1378
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
432
int opp_inst[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
627
bool tg_enabled[MAX_PIPES] = {false};
sys/dev/pci/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
761
if ((bot_id < MAX_MPCC) && (bot_id < MAX_PIPES) && (!tg_enabled[bot_id]))
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1027
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1529
struct pipe_ctx *old_opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1565
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1566
int opp_inst[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1666
struct pipe_ctx *opp_heads[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1667
struct pipe_ctx *dpp_pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
1761
struct pipe_ctx *wa_pipes[MAX_PIPES] = { NULL };
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
724
struct pipe_ctx *opp_heads[MAX_PIPES],
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
767
int opp_inst[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
768
struct pipe_ctx *opp_heads[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/hwss/hw_sequencer.h
208
#define MAX_HWSS_BLOCK_SEQUENCE_SIZE (HWSS_BLOCK_SEQUENCE_FUNC_COUNT * MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
244
struct mem_input *mis[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
245
struct hubp *hubps[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
246
struct input_pixel_processor *ipps[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
247
struct transform *transforms[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
248
struct dpp *dpps[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
249
struct output_pixel_processor *opps[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
250
struct timing_generator *timing_generators[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
251
struct stream_encoder *stream_enc[MAX_PIPES * 2];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
255
struct dce_aux *engines[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
256
struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
257
struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
268
struct display_stream_compressor *dscs[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
289
struct dc_3dlut *mpc_lut[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
290
struct dc_transfer_func *mpc_shaper[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
323
struct abm *multiple_abms[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
516
struct link_enc_assignment link_enc_assignments[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
518
struct link_enc_assignment transient_assignments[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
522
struct pipe_ctx pipe_ctx[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
523
bool is_stream_enc_acquired[MAX_PIPES * 2];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
524
bool is_audio_acquired[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
527
bool is_dsc_acquired[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
534
bool is_mpc_3dlut_acquired[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
545
struct dce_watermarks urgent_wm_ns[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
546
struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
547
struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
548
struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
604
struct dc_stream_state *streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/core_types.h
609
struct dc_stream_status stream_status[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
77
int pipe_dppclk_khz[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/dccg.h
79
bool dpp_clock_gated[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/hw_shared.h
46
#define MAX_PHANTOM_PIPES (MAX_PIPES / 2)
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
231
int dpp[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
232
int mpcc[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/opp.h
240
bool mpcc_disconnect_pending[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/hw/pg_cntl.h
35
bool pg_pipe_res_enable[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/inc/resource.h
390
struct pipe_ctx *opp_heads[MAX_PIPES]);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
400
struct pipe_ctx *dpp_pipes[MAX_PIPES]);
sys/dev/pci/drm/amd/display/dc/inc/resource.h
409
struct pipe_ctx *dpp_pipes[MAX_PIPES]);
sys/dev/pci/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
216
if (pipe_offset >= MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
145
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
665
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
69
struct pipe_ctx *pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
78
struct audio_output audio_output[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
79
struct dc_stream_state *streams_on_link[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
972
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/accessories/link_dp_cts.c
983
if (i == MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
151
struct pipe_ctx *pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
152
struct dc_stream_state *streams[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
209
struct pipe_ctx *pipes[MAX_PIPES])
sys/dev/pci/drm/amd/display/dc/link/link_dpms.c
215
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/link_dpms.h
42
struct pipe_ctx *pipes[MAX_PIPES]);
sys/dev/pci/drm/amd/display/dc/link/link_resource.c
40
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
376
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/link_validation.c
399
for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
267
struct pipe_ctx *pipes[MAX_PIPES];
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1030
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
1187
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
537
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
799
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
59
bool first_preferred_memory_for_opp[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
60
bool second_preferred_memory_for_opp[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
83
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/optc/dcn401/dcn401_optc.c
94
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
141
if (dsc_inst < MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
232
if (hubp_dpp_inst < MAX_PIPES) {
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
353
if (mpcc_inst < MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
363
if (opp_inst < MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
373
if (optc_inst < MAX_PIPES)
sys/dev/pci/drm/amd/display/dc/pg/dcn35/dcn35_pg_cntl.c
561
memset(base->pg_pipe_res_enable, 0, PG_HW_PIPE_RESOURCES_NUM_ELEMENT * MAX_PIPES * sizeof(bool));
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
1417
for (i = 0; i < MAX_PIPES; i++) {
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2013
int split[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2014
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
2042
for (i = 0; i < MAX_PIPES; i++)
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
775
int split[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
776
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
842
for (i = 0; i < MAX_PIPES; i++)
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1635
int split[MAX_PIPES] = { 0 };
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1636
bool merge[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
1637
bool newly_split[MAX_PIPES] = { false };
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
316
uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};
sys/dev/pci/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
317
uint8_t pipe_counted[MAX_PIPES] = {0};