sys/dev/pci/drm/amd/display/dc/core/dc.c

3326

ASSERT(stream->num_wb_info <= MAX_DWB_PIPES);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

493

if (wb_info->dwb_pipe_inst >= MAX_DWB_PIPES) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

517

ASSERT(stream->num_wb_info + 1 <= MAX_DWB_PIPES);

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

560

if (dwb_pipe_inst >= MAX_DWB_PIPES) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

565

if (stream->num_wb_info > MAX_DWB_PIPES) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

596

if (dwb_pipe_inst >= MAX_DWB_PIPES) {

sys/dev/pci/drm/amd/display/dc/core/dc_stream.c

601

if (stream->num_wb_info > MAX_DWB_PIPES) {

sys/dev/pci/drm/amd/display/dc/dc_stream.h

111

struct dc_writeback_info writeback_info[MAX_DWB_PIPES];

sys/dev/pci/drm/amd/display/dc/dc_stream.h

285

struct dc_writeback_info writeback_info[MAX_DWB_PIPES];

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2546

ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);

sys/dev/pci/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2571

ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

435

ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);

sys/dev/pci/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

558

ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

260

struct dwbc *dwbc[MAX_DWB_PIPES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

261

struct mcif_wb *mcif_wb[MAX_DWB_PIPES];

sys/dev/pci/drm/amd/display/dc/inc/core_types.h

557

struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1610

for (j = 0; j < MAX_DWB_PIPES; j++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1637

if (dwb_pipe >= MAX_DWB_PIPES)

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1391

for (j = 0; j < MAX_DWB_PIPES; j++) {

sys/dev/pci/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1418

if (dwb_pipe >= MAX_DWB_PIPES)