MASTER
if (vhe->state == MASTER)
if (vhe->state == MASTER && count < sizeof(sc->sc_lsmask) * 8)
if (vhe->state == MASTER)
active = (vhe->state == MASTER || sc->sc_balancing >= CARP_BAL_IP);
case MASTER:
carp_set_state(vhe, MASTER);
case MASTER:
case MASTER:
ismaster = (vhe->state == MASTER);
ismaster = (sc->cur_vhe->state == MASTER);
if (vhe0->state == MASTER) {
case MASTER:
if (current_state == MASTER)
if (cfgstate.runstate == MASTER) {
state = MASTER;
mode : Y_MASTER { $$ = MASTER; }
if (cfgstate.runstate == MASTER)
if (p->runstate != MASTER ||
cfgstate.runstate == MASTER) {
if (cfgstate.runstate == MASTER)
if (cfgstate.runstate == MASTER)
if (cfgstate.runstate == MASTER && nstate == MASTER) {
if (cfgstate.runstate != MASTER ||
if (cfgstate.runstate == MASTER)
master_pending = pics[MASTER].irr & ~(pics[MASTER].imr | (1 << 2));
if (pics[MASTER].asserted == 0 && pics[SLAVE].asserted == 0) {
high_prio_m = pics[MASTER].lowest_pri + 1;
if ((pics[MASTER].irr & (1 << i)) && i != 2 &&
!(pics[MASTER].imr & (1 << i))) {
pics[MASTER].irr &= ~(1 << i);
pics[MASTER].isr |= (1 << i);
if (pics[MASTER].irr == 0)
pics[MASTER].asserted = 0;
ret = i + pics[MASTER].vec;
pics[MASTER].irr &= ~(1 << 2);
pics[MASTER].isr |= (1 << 2);
if (pics[MASTER].irr == 0)
pics[MASTER].asserted = 0;
SET(pics[MASTER].irr, 1 << irq);
pics[MASTER].asserted = 1;
SET(pics[MASTER].irr, 1 << 2);
pics[MASTER].asserted = 1;
if (elcr[MASTER] & (1 << irq))
CLR(pics[MASTER].irr, 1 << irq);
CLR(pics[MASTER].irr, 1 << 2);
n = MASTER;
n = MASTER;
elcr[MASTER] |= (1 << irq);
elcr[MASTER] &= ~(1 << irq);
case MASTER: return "master";
pics[MASTER].cur_icw = 1;
elcr[MASTER] = 0;